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phy: phy-rockchip-inno-usb2: Add RK3128 support

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Add registers to support the 2-port usb2 phy found in RK312x SoC familiy.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20231119121340.109025-3-knaerzche@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Alex Bee 2023-11-19 13:13:37 +01:00 committed by Vinod Koul
parent 2fda590994
commit 62ff41017e
1 changed files with 57 additions and 0 deletions
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57
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
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@ -1487,6 +1487,14 @@ put_child:
return ret;
}
static int rk3128_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
/* Turn off differential receiver in suspend mode */
return regmap_write_bits(rphy->grf, 0x298,
BIT(2) << BIT_WRITEABLE_SHIFT | BIT(2),
BIT(2) << BIT_WRITEABLE_SHIFT | 0);
}
static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
int ret;
@ -1536,6 +1544,54 @@ static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
return ret;
}
static const struct rockchip_usb2phy_cfg rk3128_phy_cfgs[] = {
{
.reg = 0x17c,
.num_ports = 2,
.phy_tuning = rk3128_usb2phy_tuning,
.clkout_ctl = { 0x0190, 15, 15, 1, 0 },
.port_cfgs = {
[USB2PHY_PORT_OTG] = {
.phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
.bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
.bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
.bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
.idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
.idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
.idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
.idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
.idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
.idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
.ls_det_en = { 0x017c, 12, 12, 0, 1 },
.ls_det_st = { 0x017c, 13, 13, 0, 1 },
.ls_det_clr = { 0x017c, 13, 13, 0, 1 },
.utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
.utmi_id = { 0x014c, 8, 8, 0, 1 },
.utmi_ls = { 0x014c, 7, 6, 0, 1 },
},
[USB2PHY_PORT_HOST] = {
.phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
.ls_det_en = { 0x0194, 14, 14, 0, 1 },
.ls_det_st = { 0x0194, 15, 15, 0, 1 },
.ls_det_clr = { 0x0194, 15, 15, 0, 1 }
}
},
.chg_det = {
.opmode = { 0x017c, 3, 0, 5, 1 },
.cp_det = { 0x02c0, 6, 6, 0, 1 },
.dcp_det = { 0x02c0, 5, 5, 0, 1 },
.dp_det = { 0x02c0, 7, 7, 0, 1 },
.idm_sink_en = { 0x0184, 8, 8, 0, 1 },
.idp_sink_en = { 0x0184, 7, 7, 0, 1 },
.idp_src_en = { 0x0184, 9, 9, 0, 1 },
.rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 },
.vdm_src_en = { 0x0184, 12, 12, 0, 1 },
.vdp_src_en = { 0x0184, 11, 11, 0, 1 },
},
},
{ /* sentinel */ }
};
static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
{
.reg = 0x760,
@ -2031,6 +2087,7 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
{ .compatible = "rockchip,rk3128-usb2phy", .data = &rk3128_phy_cfgs },
{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },