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x86, VisWS: turn into generic arch, remove leftover files
remove leftover arch/x86/mach-visws/* files. Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Ingo Molnar
parent
26dd9fcfc2
commit
62fa572f69
@ -113,10 +113,6 @@ mcore-y := arch/x86/mach-default/
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mflags-$(CONFIG_X86_VOYAGER) := -Iinclude/asm-x86/mach-voyager
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mcore-$(CONFIG_X86_VOYAGER) := arch/x86/mach-voyager/
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# VISWS subarch support
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#mflags-$(CONFIG_X86_VISWS) := -Iinclude/asm-x86/mach-visws
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#mcore-$(CONFIG_X86_VISWS) := arch/x86/mach-visws/
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# generic subarchitecture
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mflags-$(CONFIG_X86_GENERICARCH):= -Iinclude/asm-x86/mach-generic
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fcore-$(CONFIG_X86_GENERICARCH) += arch/x86/mach-generic/
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@ -1,7 +0,0 @@
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#
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# Makefile for the linux kernel.
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#
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obj-y := setup.o setup_visws.o traps.o
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obj-$(CONFIG_X86_VISWS_APIC) += visws_apic.o
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@ -1,174 +0,0 @@
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/*
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* Machine specific setup for generic
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*/
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#include <linux/smp.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/acpi.h>
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#include <asm/arch_hooks.h>
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#include <asm/e820.h>
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#include <asm/setup.h>
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/*
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* Any quirks to be performed to initialize timers/irqs/etc?
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*/
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int (*arch_time_init_quirk)(void);
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int (*arch_pre_intr_init_quirk)(void);
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int (*arch_intr_init_quirk)(void);
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int (*arch_trap_init_quirk)(void);
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#ifdef CONFIG_HOTPLUG_CPU
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#define DEFAULT_SEND_IPI (1)
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#else
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#define DEFAULT_SEND_IPI (0)
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#endif
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int no_broadcast=DEFAULT_SEND_IPI;
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/**
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* pre_intr_init_hook - initialisation prior to setting up interrupt vectors
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*
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* Description:
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* Perform any necessary interrupt initialisation prior to setting up
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* the "ordinary" interrupt call gates. For legacy reasons, the ISA
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* interrupts should be initialised here if the machine emulates a PC
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* in any way.
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**/
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void __init pre_intr_init_hook(void)
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{
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if (arch_pre_intr_init_quirk) {
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if (arch_pre_intr_init_quirk())
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return;
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}
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init_ISA_irqs();
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}
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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/**
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* intr_init_hook - post gate setup interrupt initialisation
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*
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* Description:
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* Fill in any interrupts that may have been left out by the general
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* init_IRQ() routine. interrupts having to do with the machine rather
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* than the devices on the I/O bus (like APIC interrupts in intel MP
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* systems) are started here.
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**/
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void __init intr_init_hook(void)
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{
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if (arch_intr_init_quirk) {
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if (arch_intr_init_quirk())
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return;
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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apic_intr_init();
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#endif
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if (!acpi_ioapic)
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setup_irq(2, &irq2);
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}
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/**
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* pre_setup_arch_hook - hook called prior to any setup_arch() execution
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*
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* Description:
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* generally used to activate any machine specific identification
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* routines that may be needed before setup_arch() runs. On VISWS
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* this is used to get the board revision and type.
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**/
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void __init pre_setup_arch_hook(void)
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{
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}
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/**
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* trap_init_hook - initialise system specific traps
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*
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* Description:
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* Called as the final act of trap_init(). Used in VISWS to initialise
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* the various board specific APIC traps.
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**/
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void __init trap_init_hook(void)
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{
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if (arch_trap_init_quirk) {
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if (arch_trap_init_quirk())
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return;
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}
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}
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,
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.mask = CPU_MASK_NONE,
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.name = "timer"
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};
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/**
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* time_init_hook - do any specific initialisations for the system timer.
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*
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* Description:
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* Must plug the system timer interrupt source at HZ into the IRQ listed
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* in irq_vectors.h:TIMER_IRQ
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**/
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void __init time_init_hook(void)
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{
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if (arch_time_init_quirk) {
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/*
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* A nonzero return code does not mean failure, it means
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* that the architecture quirk does not want any
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* generic (timer) setup to be performed after this:
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*/
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if (arch_time_init_quirk())
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return;
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}
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irq0.mask = cpumask_of_cpu(0);
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setup_irq(0, &irq0);
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}
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#ifdef CONFIG_MCA
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/**
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* mca_nmi_hook - hook into MCA specific NMI chain
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*
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* Description:
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* The MCA (Microchannel Architecture) has an NMI chain for NMI sources
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* along the MCA bus. Use this to hook into that chain if you will need
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* it.
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**/
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void mca_nmi_hook(void)
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{
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/* If I recall correctly, there's a whole bunch of other things that
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* we can do to check for NMI problems, but that's all I know about
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* at the moment.
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*/
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printk("NMI generated from unknown source!\n");
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}
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#endif
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static __init int no_ipi_broadcast(char *str)
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{
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get_option(&str, &no_broadcast);
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printk ("Using %s mode\n", no_broadcast ? "No IPI Broadcast" :
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"IPI Broadcast");
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return 1;
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}
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__setup("no_ipi_broadcast=", no_ipi_broadcast);
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static int __init print_ipi_mode(void)
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{
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printk ("Using IPI %s mode\n", no_broadcast ? "No-Shortcut" :
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"Shortcut");
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return 0;
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}
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late_initcall(print_ipi_mode);
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@ -1,331 +0,0 @@
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/*
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* Unmaintained SGI Visual Workstation support.
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* Split out from setup.c by davej@suse.de
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/visws/cobalt.h>
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#include <asm/visws/piix4.h>
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#include <asm/arch_hooks.h>
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#include <asm/fixmap.h>
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#include <asm/reboot.h>
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#include <asm/setup.h>
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#include <asm/e820.h>
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#include <asm/smp.h>
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#include <asm/io.h>
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#include <mach_ipi.h>
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#include "mach_apic.h"
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#include <linux/init.h>
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#include <linux/smp.h>
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char visws_board_type = -1;
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char visws_board_rev = -1;
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int is_visws_box(void)
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{
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return visws_board_type >= 0;
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}
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static int __init visws_time_init_quirk(void)
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{
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printk(KERN_INFO "Starting Cobalt Timer system clock\n");
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/* Set the countdown value */
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co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
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/* Start the timer */
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co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
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/* Enable (unmask) the timer interrupt */
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co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
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/*
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* Zero return means the generic timer setup code will set up
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* the standard vector:
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*/
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return 0;
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}
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static int __init visws_pre_intr_init_quirk(void)
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{
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init_VISWS_APIC_irqs();
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/*
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* We dont want ISA irqs to be set up by the generic code:
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*/
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return 1;
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}
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/* Quirk for machine specific memory setup. */
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#define MB (1024 * 1024)
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unsigned long sgivwfb_mem_phys;
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unsigned long sgivwfb_mem_size;
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EXPORT_SYMBOL(sgivwfb_mem_phys);
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EXPORT_SYMBOL(sgivwfb_mem_size);
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long long mem_size __initdata = 0;
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static char * __init visws_memory_setup_quirk(void)
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{
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long long gfx_mem_size = 8 * MB;
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mem_size = boot_params.alt_mem_k;
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if (!mem_size) {
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printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
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mem_size = 128 * MB;
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}
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/*
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* this hardcodes the graphics memory to 8 MB
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* it really should be sized dynamically (or at least
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* set as a boot param)
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*/
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if (!sgivwfb_mem_size) {
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printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
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sgivwfb_mem_size = 8 * MB;
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}
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/*
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* Trim to nearest MB
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*/
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sgivwfb_mem_size &= ~((1 << 20) - 1);
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sgivwfb_mem_phys = mem_size - gfx_mem_size;
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e820_add_region(0, LOWMEMSIZE(), E820_RAM);
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e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
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e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
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return "PROM";
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}
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static void visws_machine_emergency_restart(void)
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{
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/*
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* Visual Workstations restart after this
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* register is poked on the PIIX4
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*/
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outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
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}
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static void visws_machine_power_off(void)
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{
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unsigned short pm_status;
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/* extern unsigned int pci_bus0; */
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while ((pm_status = inw(PMSTS_PORT)) & 0x100)
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outw(pm_status, PMSTS_PORT);
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outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
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mdelay(10);
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#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
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(0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
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/* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
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outl(PIIX_SPECIAL_STOP, 0xCFC);
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}
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static int __init visws_get_smp_config_quirk(unsigned int early)
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{
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/*
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* Prevent MP-table parsing by the generic code:
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*/
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return 1;
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}
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extern unsigned int __cpuinitdata maxcpus;
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/*
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* The Visual Workstation is Intel MP compliant in the hardware
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* sense, but it doesn't have a BIOS(-configuration table).
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* No problem for Linux.
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*/
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static void __init MP_processor_info (struct mpc_config_processor *m)
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{
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int ver, logical_apicid;
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physid_mask_t apic_cpus;
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if (!(m->mpc_cpuflag & CPU_ENABLED))
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return;
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logical_apicid = m->mpc_apicid;
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printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
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m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
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m->mpc_apicid,
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(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
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(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
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m->mpc_apicver);
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if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
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boot_cpu_physical_apicid = m->mpc_apicid;
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ver = m->mpc_apicver;
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if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
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printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
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m->mpc_apicid, MAX_APICS);
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return;
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}
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apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
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physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
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/*
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* Validate version
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*/
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if (ver == 0x0) {
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printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
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"fixing up to 0x10. (tell your hw vendor)\n",
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m->mpc_apicid);
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ver = 0x10;
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}
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apic_version[m->mpc_apicid] = ver;
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}
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int __init visws_find_smp_config_quirk(unsigned int reserve)
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{
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struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);
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unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
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if (ncpus > CO_CPU_MAX) {
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printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
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ncpus, mp);
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ncpus = CO_CPU_MAX;
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}
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if (ncpus > maxcpus)
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ncpus = maxcpus;
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#ifdef CONFIG_X86_LOCAL_APIC
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smp_found_config = 1;
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#endif
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while (ncpus--)
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MP_processor_info(mp++);
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mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
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return 1;
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}
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extern int visws_trap_init_quirk(void);
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void __init visws_early_detect(void)
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{
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int raw;
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visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
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>> PIIX_GPI_BD_SHIFT;
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if (visws_board_type < 0)
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return;
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/*
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* Install special quirks for timer, interrupt and memory setup:
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*/
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arch_time_init_quirk = visws_time_init_quirk;
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arch_pre_intr_init_quirk = visws_pre_intr_init_quirk;
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arch_memory_setup_quirk = visws_memory_setup_quirk;
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/*
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* Fall back to generic behavior for traps:
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*/
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arch_intr_init_quirk = NULL;
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arch_trap_init_quirk = visws_trap_init_quirk;
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/*
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* Install reboot quirks:
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*/
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pm_power_off = visws_machine_power_off;
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machine_ops.emergency_restart = visws_machine_emergency_restart;
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/*
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* Do not use broadcast IPIs:
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*/
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no_broadcast = 0;
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/*
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* Override generic MP-table parsing:
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*/
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mach_get_smp_config_quirk = visws_get_smp_config_quirk;
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mach_find_smp_config_quirk = visws_find_smp_config_quirk;
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/*
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* Get Board rev.
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* First, we have to initialize the 307 part to allow us access
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* to the GPIO registers. Let's map them at 0x0fc0 which is right
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* after the PIIX4 PM section.
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*/
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outb_p(SIO_DEV_SEL, SIO_INDEX);
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outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
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outb_p(SIO_DEV_MSB, SIO_INDEX);
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outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
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outb_p(SIO_DEV_LSB, SIO_INDEX);
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outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
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outb_p(SIO_DEV_ENB, SIO_INDEX);
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outb_p(1, SIO_DATA); /* Enable GPIO registers. */
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/*
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* Now, we have to map the power management section to write
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* a bit which enables access to the GPIO registers.
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* What lunatic came up with this shit?
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*/
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outb_p(SIO_DEV_SEL, SIO_INDEX);
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outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
|
||||
|
||||
outb_p(SIO_DEV_MSB, SIO_INDEX);
|
||||
outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
|
||||
|
||||
outb_p(SIO_DEV_LSB, SIO_INDEX);
|
||||
outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
|
||||
|
||||
outb_p(SIO_DEV_ENB, SIO_INDEX);
|
||||
outb_p(1, SIO_DATA); /* Enable PM registers. */
|
||||
|
||||
/*
|
||||
* Now, write the PM register which enables the GPIO registers.
|
||||
*/
|
||||
outb_p(SIO_PM_FER2, SIO_PM_INDEX);
|
||||
outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
|
||||
|
||||
/*
|
||||
* Now, initialize the GPIO registers.
|
||||
* We want them all to be inputs which is the
|
||||
* power on default, so let's leave them alone.
|
||||
* So, let's just read the board rev!
|
||||
*/
|
||||
raw = inb_p(SIO_GP_DATA1);
|
||||
raw &= 0x7f; /* 7 bits of valid board revision ID. */
|
||||
|
||||
if (visws_board_type == VISWS_320) {
|
||||
if (raw < 0x6) {
|
||||
visws_board_rev = 4;
|
||||
} else if (raw < 0xc) {
|
||||
visws_board_rev = 5;
|
||||
} else {
|
||||
visws_board_rev = 6;
|
||||
}
|
||||
} else if (visws_board_type == VISWS_540) {
|
||||
visws_board_rev = 2;
|
||||
} else {
|
||||
visws_board_rev = raw;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
|
||||
(visws_board_type == VISWS_320 ? "320" :
|
||||
(visws_board_type == VISWS_540 ? "540" :
|
||||
"unknown")), visws_board_rev);
|
||||
}
|
||||
@ -1,71 +0,0 @@
|
||||
/* VISWS traps */
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci_ids.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/apic.h>
|
||||
#include <asm/arch_hooks.h>
|
||||
#include <asm/visws/cobalt.h>
|
||||
#include <asm/visws/lithium.h>
|
||||
|
||||
|
||||
#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
|
||||
#define BCD (LI_INTB | LI_INTC | LI_INTD)
|
||||
#define ALLDEVS (A01234 | BCD)
|
||||
|
||||
static __init void lithium_init(void)
|
||||
{
|
||||
set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
|
||||
set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
|
||||
|
||||
if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
|
||||
(li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
|
||||
printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
|
||||
/* panic("This machine is not SGI Visual Workstation 320/540"); */
|
||||
}
|
||||
|
||||
if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
|
||||
(li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
|
||||
printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
|
||||
/* panic("This machine is not SGI Visual Workstation 320/540"); */
|
||||
}
|
||||
|
||||
li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
|
||||
li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
|
||||
}
|
||||
|
||||
static __init void cobalt_init(void)
|
||||
{
|
||||
/*
|
||||
* On normal SMP PC this is used only with SMP, but we have to
|
||||
* use it and set it up here to start the Cobalt clock
|
||||
*/
|
||||
set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
|
||||
setup_local_APIC();
|
||||
printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
|
||||
(unsigned int)apic_read(APIC_LVR),
|
||||
(unsigned int)apic_read(APIC_ID));
|
||||
|
||||
set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
|
||||
set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
|
||||
printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
|
||||
co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
|
||||
|
||||
/* Enable Cobalt APIC being careful to NOT change the ID! */
|
||||
co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
|
||||
|
||||
printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
|
||||
co_apic_read(CO_APIC_ID));
|
||||
}
|
||||
|
||||
int __init visws_trap_init_quirk(void)
|
||||
{
|
||||
lithium_init();
|
||||
cobalt_init();
|
||||
|
||||
return 1;
|
||||
}
|
||||
@ -1,295 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 1999 Bent Hagemark, Ingo Molnar
|
||||
*
|
||||
* SGI Visual Workstation interrupt controller
|
||||
*
|
||||
* The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
|
||||
* which serves as the main interrupt controller in the system. Non-legacy
|
||||
* hardware in the system uses this controller directly. Legacy devices
|
||||
* are connected to the PIIX4 which in turn has its 8259(s) connected to
|
||||
* a of the Cobalt APIC entry.
|
||||
*
|
||||
* 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
|
||||
*
|
||||
* 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
|
||||
*/
|
||||
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/apic.h>
|
||||
#include <asm/i8259.h>
|
||||
#include <asm/irq_vectors.h>
|
||||
#include <asm/visws/cobalt.h>
|
||||
|
||||
static DEFINE_SPINLOCK(cobalt_lock);
|
||||
|
||||
/*
|
||||
* Set the given Cobalt APIC Redirection Table entry to point
|
||||
* to the given IDT vector/index.
|
||||
*/
|
||||
static inline void co_apic_set(int entry, int irq)
|
||||
{
|
||||
co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
|
||||
co_apic_write(CO_APIC_HI(entry), 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Cobalt (IO)-APIC functions to handle PCI devices.
|
||||
*/
|
||||
static inline int co_apic_ide0_hack(void)
|
||||
{
|
||||
extern char visws_board_type;
|
||||
extern char visws_board_rev;
|
||||
|
||||
if (visws_board_type == VISWS_320 && visws_board_rev == 5)
|
||||
return 5;
|
||||
return CO_APIC_IDE0;
|
||||
}
|
||||
|
||||
static int is_co_apic(unsigned int irq)
|
||||
{
|
||||
if (IS_CO_APIC(irq))
|
||||
return CO_APIC(irq);
|
||||
|
||||
switch (irq) {
|
||||
case 0: return CO_APIC_CPU;
|
||||
case CO_IRQ_IDE0: return co_apic_ide0_hack();
|
||||
case CO_IRQ_IDE1: return CO_APIC_IDE1;
|
||||
default: return -1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This is the SGI Cobalt (IO-)APIC:
|
||||
*/
|
||||
|
||||
static void enable_cobalt_irq(unsigned int irq)
|
||||
{
|
||||
co_apic_set(is_co_apic(irq), irq);
|
||||
}
|
||||
|
||||
static void disable_cobalt_irq(unsigned int irq)
|
||||
{
|
||||
int entry = is_co_apic(irq);
|
||||
|
||||
co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
|
||||
co_apic_read(CO_APIC_LO(entry));
|
||||
}
|
||||
|
||||
/*
|
||||
* "irq" really just serves to identify the device. Here is where we
|
||||
* map this to the Cobalt APIC entry where it's physically wired.
|
||||
* This is called via request_irq -> setup_irq -> irq_desc->startup()
|
||||
*/
|
||||
static unsigned int startup_cobalt_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&cobalt_lock, flags);
|
||||
if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
|
||||
irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
|
||||
enable_cobalt_irq(irq);
|
||||
spin_unlock_irqrestore(&cobalt_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ack_cobalt_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&cobalt_lock, flags);
|
||||
disable_cobalt_irq(irq);
|
||||
apic_write(APIC_EOI, APIC_EIO_ACK);
|
||||
spin_unlock_irqrestore(&cobalt_lock, flags);
|
||||
}
|
||||
|
||||
static void end_cobalt_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&cobalt_lock, flags);
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
|
||||
enable_cobalt_irq(irq);
|
||||
spin_unlock_irqrestore(&cobalt_lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip cobalt_irq_type = {
|
||||
.typename = "Cobalt-APIC",
|
||||
.startup = startup_cobalt_irq,
|
||||
.shutdown = disable_cobalt_irq,
|
||||
.enable = enable_cobalt_irq,
|
||||
.disable = disable_cobalt_irq,
|
||||
.ack = ack_cobalt_irq,
|
||||
.end = end_cobalt_irq,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
|
||||
* -- not the manner expected by the code in i8259.c.
|
||||
*
|
||||
* there is a 'master' physical interrupt source that gets sent to
|
||||
* the CPU. But in the chipset there are various 'virtual' interrupts
|
||||
* waiting to be handled. We represent this to Linux through a 'master'
|
||||
* interrupt controller type, and through a special virtual interrupt-
|
||||
* controller. Device drivers only see the virtual interrupt sources.
|
||||
*/
|
||||
static unsigned int startup_piix4_master_irq(unsigned int irq)
|
||||
{
|
||||
init_8259A(0);
|
||||
|
||||
return startup_cobalt_irq(irq);
|
||||
}
|
||||
|
||||
static void end_piix4_master_irq(unsigned int irq)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&cobalt_lock, flags);
|
||||
enable_cobalt_irq(irq);
|
||||
spin_unlock_irqrestore(&cobalt_lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip piix4_master_irq_type = {
|
||||
.typename = "PIIX4-master",
|
||||
.startup = startup_piix4_master_irq,
|
||||
.ack = ack_cobalt_irq,
|
||||
.end = end_piix4_master_irq,
|
||||
};
|
||||
|
||||
|
||||
static struct irq_chip piix4_virtual_irq_type = {
|
||||
.typename = "PIIX4-virtual",
|
||||
.shutdown = disable_8259A_irq,
|
||||
.enable = enable_8259A_irq,
|
||||
.disable = disable_8259A_irq,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* PIIX4-8259 master/virtual functions to handle interrupt requests
|
||||
* from legacy devices: floppy, parallel, serial, rtc.
|
||||
*
|
||||
* None of these get Cobalt APIC entries, neither do they have IDT
|
||||
* entries. These interrupts are purely virtual and distributed from
|
||||
* the 'master' interrupt source: CO_IRQ_8259.
|
||||
*
|
||||
* When the 8259 interrupts its handler figures out which of these
|
||||
* devices is interrupting and dispatches to its handler.
|
||||
*
|
||||
* CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
|
||||
* enable_irq gets the right irq. This 'master' irq is never directly
|
||||
* manipulated by any driver.
|
||||
*/
|
||||
static irqreturn_t piix4_master_intr(int irq, void *dev_id)
|
||||
{
|
||||
int realirq;
|
||||
irq_desc_t *desc;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&i8259A_lock, flags);
|
||||
|
||||
/* Find out what's interrupting in the PIIX4 master 8259 */
|
||||
outb(0x0c, 0x20); /* OCW3 Poll command */
|
||||
realirq = inb(0x20);
|
||||
|
||||
/*
|
||||
* Bit 7 == 0 means invalid/spurious
|
||||
*/
|
||||
if (unlikely(!(realirq & 0x80)))
|
||||
goto out_unlock;
|
||||
|
||||
realirq &= 7;
|
||||
|
||||
if (unlikely(realirq == 2)) {
|
||||
outb(0x0c, 0xa0);
|
||||
realirq = inb(0xa0);
|
||||
|
||||
if (unlikely(!(realirq & 0x80)))
|
||||
goto out_unlock;
|
||||
|
||||
realirq = (realirq & 7) + 8;
|
||||
}
|
||||
|
||||
/* mask and ack interrupt */
|
||||
cached_irq_mask |= 1 << realirq;
|
||||
if (unlikely(realirq > 7)) {
|
||||
inb(0xa1);
|
||||
outb(cached_slave_mask, 0xa1);
|
||||
outb(0x60 + (realirq & 7), 0xa0);
|
||||
outb(0x60 + 2, 0x20);
|
||||
} else {
|
||||
inb(0x21);
|
||||
outb(cached_master_mask, 0x21);
|
||||
outb(0x60 + realirq, 0x20);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
||||
|
||||
desc = irq_desc + realirq;
|
||||
|
||||
/*
|
||||
* handle this 'virtual interrupt' as a Cobalt one now.
|
||||
*/
|
||||
kstat_cpu(smp_processor_id()).irqs[realirq]++;
|
||||
|
||||
if (likely(desc->action != NULL))
|
||||
handle_IRQ_event(realirq, desc->action);
|
||||
|
||||
if (!(desc->status & IRQ_DISABLED))
|
||||
enable_8259A_irq(realirq);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
||||
out_unlock:
|
||||
spin_unlock_irqrestore(&i8259A_lock, flags);
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
static struct irqaction master_action = {
|
||||
.handler = piix4_master_intr,
|
||||
.name = "PIIX4-8259",
|
||||
};
|
||||
|
||||
static struct irqaction cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade",
|
||||
};
|
||||
|
||||
|
||||
void init_VISWS_APIC_irqs(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
|
||||
irq_desc[i].status = IRQ_DISABLED;
|
||||
irq_desc[i].action = 0;
|
||||
irq_desc[i].depth = 1;
|
||||
|
||||
if (i == 0) {
|
||||
irq_desc[i].chip = &cobalt_irq_type;
|
||||
}
|
||||
else if (i == CO_IRQ_IDE0) {
|
||||
irq_desc[i].chip = &cobalt_irq_type;
|
||||
}
|
||||
else if (i == CO_IRQ_IDE1) {
|
||||
irq_desc[i].chip = &cobalt_irq_type;
|
||||
}
|
||||
else if (i == CO_IRQ_8259) {
|
||||
irq_desc[i].chip = &piix4_master_irq_type;
|
||||
}
|
||||
else if (i < CO_IRQ_APIC0) {
|
||||
irq_desc[i].chip = &piix4_virtual_irq_type;
|
||||
}
|
||||
else if (IS_CO_APIC(i)) {
|
||||
irq_desc[i].chip = &cobalt_irq_type;
|
||||
}
|
||||
}
|
||||
|
||||
setup_irq(CO_IRQ_8259, &master_action);
|
||||
setup_irq(2, &cascade_action);
|
||||
}
|
||||
@ -9,8 +9,6 @@ pci-y := fixup.o
|
||||
pci-$(CONFIG_ACPI) += acpi.o
|
||||
pci-y += legacy.o irq.o
|
||||
|
||||
# Careful: VISWS overrule the pci-y above. The colons are
|
||||
# therefor correct. This needs a proper fix by distangling the code.
|
||||
pci-$(CONFIG_X86_VISWS) += visws.o
|
||||
|
||||
pci-$(CONFIG_X86_NUMAQ) += numa.o
|
||||
|
||||
Loading…
Reference in New Issue
Block a user