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crypto: caam - enable LARGE_BURST for enhancing DMA transactions size

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Increasing CAAM DMA engine transaction size either
-reduces the number of required transactions or
-adds the ability to transfer more data with same transaction count

Signed-off-by: Horia Geant? <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Horia Geant? 2016-01-12 17:14:10 +02:00 committed by Herbert Xu
parent ba171135bf
commit 624144a7eb
2 changed files with 3 additions and 2 deletions
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2
drivers/crypto/caam/ctrl.c
View File

@ -534,7 +534,7 @@ static int caam_probe(struct platform_device *pdev)
* long pointers in master configuration register * long pointers in master configuration register
*/ */
clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH | clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE | MCFGR_AWCACHE_BUFF | MCFGR_WDENABLE | MCFGR_LARGE_BURST |
(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
/* /*

3
drivers/crypto/caam/regs.h
View File

@ -455,7 +455,8 @@ struct caam_ctrl {
#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
#define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
#define MCFGR_BURST_64 0x00000001 /* Max burst size */ #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */
#define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */
/* JRSTART register offsets */ /* JRSTART register offsets */
#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */