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drm/radeon/kms/r4xx: cleanup atom path
most of radeon_legacy_atom_set_surface() is taken care of in atombios_set_base(), so remove the duplicate setup and move the remaining bits (DISP_MERGE setup and FP2 sync) to atombios_crtc.c where they are used. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
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@ -718,6 +718,30 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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return radeon_crtc_set_base(crtc, x, y, old_fb);
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}
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/* properly set additional regs when using atombios */
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static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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u32 disp_merge_cntl;
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switch (radeon_crtc->crtc_id) {
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case 0:
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disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
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disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
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WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
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break;
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case 1:
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disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
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disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
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WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
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WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
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WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
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break;
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}
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}
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int atombios_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -740,7 +764,7 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
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if (radeon_crtc->crtc_id == 0)
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atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
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atombios_crtc_set_base(crtc, x, y, old_fb);
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radeon_legacy_atom_set_surface(crtc);
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radeon_legacy_atom_fixup(crtc);
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}
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atombios_overscan_setup(crtc, mode, adjusted_mode);
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atombios_scaler_setup(crtc);
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@ -339,69 +339,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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}
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}
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/* properly set crtc bpp when using atombios */
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void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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int format;
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uint32_t crtc_gen_cntl;
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uint32_t disp_merge_cntl;
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uint32_t crtc_pitch;
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switch (crtc->fb->bits_per_pixel) {
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case 8:
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format = 2;
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break;
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case 15: /* 555 */
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format = 3;
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break;
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case 16: /* 565 */
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format = 4;
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break;
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case 24: /* RGB */
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format = 5;
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break;
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case 32: /* xRGB */
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format = 6;
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break;
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default:
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return;
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}
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crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
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((crtc->fb->bits_per_pixel * 8) - 1)) /
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(crtc->fb->bits_per_pixel * 8));
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crtc_pitch |= crtc_pitch << 16;
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WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
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switch (radeon_crtc->crtc_id) {
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case 0:
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disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
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disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
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WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
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crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
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crtc_gen_cntl |= (format << 8);
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crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
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WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
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break;
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case 1:
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disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
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disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
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WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
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crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
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crtc_gen_cntl |= (format << 8);
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WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
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WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
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WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
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break;
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}
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}
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int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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@ -453,7 +453,6 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
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extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb);
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extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
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extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
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struct drm_file *file_priv,
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