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drm/radeon: set speakers allocation earlier
Do it before enabling audio channels (in AFMT_AUDIO_PACKET_CONTROL2 register). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -94,17 +94,62 @@ void dce6_afmt_select_pin(struct drm_encoder *encoder)
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WREG32(AFMT_AUDIO_SRC_CONTROL + offset, AFMT_AUDIO_SRC_SELECT(id));
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}
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void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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u32 offset, tmp;
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u8 *sadb;
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int sad_count;
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if (!dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder)
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radeon_connector = to_radeon_connector(connector);
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
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if (sad_count < 0) {
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DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
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return;
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}
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set HDMI mode */
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tmp |= HDMI_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
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kfree(sadb);
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}
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void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 offset, tmp;
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u32 offset;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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struct cea_sad *sads;
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int i, sad_count, sadb_count;
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u8 *sadb;
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int i, sad_count;
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static const u16 eld_reg_to_type[][2] = {
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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@ -143,23 +188,6 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
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}
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BUG_ON(!sads);
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sadb_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
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if (sadb_count < 0) {
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DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);
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return;
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}
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set HDMI mode */
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tmp |= HDMI_CONNECTION;
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if (sadb_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 value = 0;
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int j;
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@ -180,7 +208,6 @@ void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
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}
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kfree(sads);
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kfree(sadb);
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}
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static int dce6_audio_chipset_supported(struct radeon_device *rdev)
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@ -32,6 +32,7 @@
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#include "evergreend.h"
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#include "atom.h"
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extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
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extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
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extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
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@ -267,7 +268,11 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
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AFMT_60958_CS_CHANNEL_NUMBER_7(8));
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/* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
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if (ASIC_IS_DCE6(rdev)) {
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dce6_afmt_write_speaker_allocation(encoder);
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} else {
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/* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
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}
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WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
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AFMT_AUDIO_CHANNEL_ENABLE(0xff));
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