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[ARM] 3826/1: iop3xx: remove IOP3??_IRQ_OFS irq offset
Get rid of the unused IOP3??_IRQ_OFS irq offset define, start IRQ numbering from zero. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek
Russell King
parent
38ce73ebd7
commit
610300e8f4
@ -43,7 +43,7 @@ static void
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iop321_irq_mask (unsigned int irq)
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{
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iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS));
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iop321_mask &= ~(1 << irq);
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intctl_write(iop321_mask);
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}
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@ -51,7 +51,7 @@ iop321_irq_mask (unsigned int irq)
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static void
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iop321_irq_unmask (unsigned int irq)
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{
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iop321_mask |= (1 << (irq - IOP321_IRQ_OFS));
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iop321_mask |= (1 << irq);
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intctl_write(iop321_mask);
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}
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@ -73,7 +73,7 @@ void __init iop321_init_irq(void)
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machine_is_iq31244()) // all interrupts are inputs to chip
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*IOP3XX_PCIIRSR = 0x0f;
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for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++)
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for(i = 0; i < NR_IRQS; i++)
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{
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set_irq_chip(i, &ext_chip);
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set_irq_handler(i, do_level_IRQ);
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@ -60,28 +60,28 @@ static inline void intstr_write1(u32 val)
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static void
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iop331_irq_mask1 (unsigned int irq)
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{
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iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS));
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iop331_mask0 &= ~(1 << irq);
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intctl_write0(iop331_mask0);
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}
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static void
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iop331_irq_mask2 (unsigned int irq)
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{
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iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32));
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iop331_mask1 &= ~(1 << (irq - 32));
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intctl_write1(iop331_mask1);
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}
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static void
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iop331_irq_unmask1(unsigned int irq)
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{
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iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS));
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iop331_mask0 |= (1 << irq);
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intctl_write0(iop331_mask0);
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}
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static void
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iop331_irq_unmask2(unsigned int irq)
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{
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iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32));
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iop331_mask1 |= (1 << (irq - 32));
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intctl_write1(iop331_mask1);
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}
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@ -110,7 +110,7 @@ void __init iop331_init_irq(void)
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if(machine_is_iq80331()) // all interrupts are inputs to chip
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*IOP3XX_PCIIRSR = 0x0f;
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for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++)
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for(i = 0; i < NR_IRQS; i++)
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{
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set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
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set_irq_handler(i, do_level_IRQ);
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@ -24,6 +24,5 @@
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clz \irqnr, \irqstat
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mov \base, #31
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subs \irqnr,\base,\irqnr
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add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
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1001:
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.endm
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@ -15,46 +15,36 @@
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/*
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* IOP80321 chipset interrupts
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*/
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#define IOP321_IRQ_OFS 0
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#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x))
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#define IRQ_IOP321_DMA0_EOT 0
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#define IRQ_IOP321_DMA0_EOC 1
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#define IRQ_IOP321_DMA1_EOT 2
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#define IRQ_IOP321_DMA1_EOC 3
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#define IRQ_IOP321_AA_EOT 6
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#define IRQ_IOP321_AA_EOC 7
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#define IRQ_IOP321_CORE_PMON 8
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#define IRQ_IOP321_TIMER0 9
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#define IRQ_IOP321_TIMER1 10
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#define IRQ_IOP321_I2C_0 11
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#define IRQ_IOP321_I2C_1 12
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#define IRQ_IOP321_MESSAGING 13
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#define IRQ_IOP321_ATU_BIST 14
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#define IRQ_IOP321_PERFMON 15
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#define IRQ_IOP321_CORE_PMU 16
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#define IRQ_IOP321_BIU_ERR 17
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#define IRQ_IOP321_ATU_ERR 18
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#define IRQ_IOP321_MCU_ERR 19
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#define IRQ_IOP321_DMA0_ERR 20
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#define IRQ_IOP321_DMA1_ERR 21
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#define IRQ_IOP321_AA_ERR 23
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#define IRQ_IOP321_MSG_ERR 24
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#define IRQ_IOP321_SSP 25
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#define IRQ_IOP321_XINT0 27
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#define IRQ_IOP321_XINT1 28
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#define IRQ_IOP321_XINT2 29
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#define IRQ_IOP321_XINT3 30
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#define IRQ_IOP321_HPI 31
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/*
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* On IRQ or FIQ register
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*/
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#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0)
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#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1)
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#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2)
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#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3)
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#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4)
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#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5)
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#define IRQ_IOP321_AA_EOT IOP321_IRQ(6)
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#define IRQ_IOP321_AA_EOC IOP321_IRQ(7)
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#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8)
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#define IRQ_IOP321_TIMER0 IOP321_IRQ(9)
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#define IRQ_IOP321_TIMER1 IOP321_IRQ(10)
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#define IRQ_IOP321_I2C_0 IOP321_IRQ(11)
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#define IRQ_IOP321_I2C_1 IOP321_IRQ(12)
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#define IRQ_IOP321_MESSAGING IOP321_IRQ(13)
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#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14)
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#define IRQ_IOP321_PERFMON IOP321_IRQ(15)
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#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16)
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#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17)
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#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18)
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#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19)
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#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20)
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#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21)
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#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22)
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#define IRQ_IOP321_AA_ERR IOP321_IRQ(23)
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#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24)
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#define IRQ_IOP321_SSP IOP321_IRQ(25)
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#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26)
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#define IRQ_IOP321_XINT0 IOP321_IRQ(27)
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#define IRQ_IOP321_XINT1 IOP321_IRQ(28)
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#define IRQ_IOP321_XINT2 IOP321_IRQ(29)
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#define IRQ_IOP321_XINT3 IOP321_IRQ(30)
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#define IRQ_IOP321_HPI IOP321_IRQ(31)
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#define NR_IRQS (IOP321_IRQ(31) + 1)
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#define NR_IRQS 32
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/*
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@ -30,6 +30,5 @@
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b 1001f
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1002: clz \irqnr, \irqstat
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rsbs \irqnr,\irqnr,#31 @ recommend by RMK
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add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
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1001:
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.endm
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@ -15,78 +15,46 @@
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/*
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* IOP80331 chipset interrupts
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*/
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#define IOP331_IRQ_OFS 0
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#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x))
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#define IRQ_IOP331_DMA0_EOT 0
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#define IRQ_IOP331_DMA0_EOC 1
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#define IRQ_IOP331_DMA1_EOT 2
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#define IRQ_IOP331_DMA1_EOC 3
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#define IRQ_IOP331_AA_EOT 6
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#define IRQ_IOP331_AA_EOC 7
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#define IRQ_IOP331_TIMER0 8
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#define IRQ_IOP331_TIMER1 9
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#define IRQ_IOP331_I2C_0 10
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#define IRQ_IOP331_I2C_1 11
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#define IRQ_IOP331_MSG 12
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#define IRQ_IOP331_MSGIBQ 13
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#define IRQ_IOP331_ATU_BIST 14
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#define IRQ_IOP331_PERFMON 15
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#define IRQ_IOP331_CORE_PMU 16
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#define IRQ_IOP331_XINT0 24
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#define IRQ_IOP331_XINT1 25
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#define IRQ_IOP331_XINT2 26
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#define IRQ_IOP331_XINT3 27
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#define IRQ_IOP331_XINT8 32
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#define IRQ_IOP331_XINT9 33
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#define IRQ_IOP331_XINT10 34
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#define IRQ_IOP331_XINT11 35
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#define IRQ_IOP331_XINT12 36
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#define IRQ_IOP331_XINT13 37
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#define IRQ_IOP331_XINT14 38
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#define IRQ_IOP331_XINT15 39
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#define IRQ_IOP331_UART0 51
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#define IRQ_IOP331_UART1 52
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#define IRQ_IOP331_PBIE 53
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#define IRQ_IOP331_ATU_CRW 54
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#define IRQ_IOP331_ATU_ERR 55
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#define IRQ_IOP331_MCU_ERR 56
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#define IRQ_IOP331_DMA0_ERR 57
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#define IRQ_IOP331_DMA1_ERR 58
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#define IRQ_IOP331_AA_ERR 60
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#define IRQ_IOP331_MSG_ERR 62
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#define IRQ_IOP331_HPI 63
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/*
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* On IRQ or FIQ register
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*/
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#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
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#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
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#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
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#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
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#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
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#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
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#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
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#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
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#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
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#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
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#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
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#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
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#define IRQ_IOP331_MSG IOP331_IRQ(12)
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#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
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#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
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#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
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#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
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#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
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#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
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#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
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#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
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#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
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#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
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#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
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#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
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#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
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#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
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#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
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#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
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#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
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#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
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#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
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#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
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#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
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#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
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#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
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#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
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#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
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#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
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#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
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#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
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#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
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#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
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#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
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#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
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#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
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#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
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#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
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#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
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#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
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#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
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#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
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#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
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#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
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#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
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#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
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#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
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#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
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#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
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#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
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#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
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#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
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#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
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#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
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#define NR_IRQS (IOP331_IRQ(63) + 1)
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#define NR_IRQS 64
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/*
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