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i2c: i2c-stm32f7: Add slave support
This patch adds slave support for I2C controller embedded in STM32F7 SoC Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com> Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Pierre-Yves MORDRET
Wolfram Sang
parent
8c7ecc9953
commit
60d609f30d
@ -944,6 +944,7 @@ config I2C_STM32F4
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config I2C_STM32F7
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tristate "STMicroelectronics STM32F7 I2C support"
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depends on ARCH_STM32 || COMPILE_TEST
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select I2C_SLAVE
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help
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Enable this option to add support for STM32 I2C controller embedded
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in STM32F7 SoCs.
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@ -35,6 +35,8 @@
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/* STM32F7 I2C registers */
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#define STM32F7_I2C_CR1 0x00
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#define STM32F7_I2C_CR2 0x04
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#define STM32F7_I2C_OAR1 0x08
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#define STM32F7_I2C_OAR2 0x0C
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#define STM32F7_I2C_TIMINGR 0x10
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#define STM32F7_I2C_ISR 0x18
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#define STM32F7_I2C_ICR 0x1C
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@ -42,6 +44,7 @@
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#define STM32F7_I2C_TXDR 0x28
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/* STM32F7 I2C control 1 */
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#define STM32F7_I2C_CR1_SBC BIT(16)
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#define STM32F7_I2C_CR1_ANFOFF BIT(12)
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#define STM32F7_I2C_CR1_ERRIE BIT(7)
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#define STM32F7_I2C_CR1_TCIE BIT(6)
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@ -57,6 +60,11 @@
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| STM32F7_I2C_CR1_NACKIE \
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| STM32F7_I2C_CR1_RXIE \
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| STM32F7_I2C_CR1_TXIE)
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#define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
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| STM32F7_I2C_CR1_STOPIE \
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| STM32F7_I2C_CR1_NACKIE \
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| STM32F7_I2C_CR1_RXIE \
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| STM32F7_I2C_CR1_TXIE)
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/* STM32F7 I2C control 2 */
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#define STM32F7_I2C_CR2_RELOAD BIT(24)
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@ -74,7 +82,34 @@
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#define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
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#define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
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/* STM32F7 I2C Own Address 1 */
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#define STM32F7_I2C_OAR1_OA1EN BIT(15)
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#define STM32F7_I2C_OAR1_OA1MODE BIT(10)
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#define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
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#define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
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STM32F7_I2C_OAR1_OA1_10_MASK))
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#define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
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#define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
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#define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
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| STM32F7_I2C_OAR1_OA1_10_MASK \
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| STM32F7_I2C_OAR1_OA1EN \
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| STM32F7_I2C_OAR1_OA1MODE)
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/* STM32F7 I2C Own Address 2 */
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#define STM32F7_I2C_OAR2_OA2EN BIT(15)
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#define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
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#define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
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#define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
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#define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
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#define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
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| STM32F7_I2C_OAR2_OA2_7_MASK \
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| STM32F7_I2C_OAR2_OA2EN)
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/* STM32F7 I2C Interrupt Status */
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#define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
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#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
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(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
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#define STM32F7_I2C_ISR_DIR BIT(16)
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#define STM32F7_I2C_ISR_BUSY BIT(15)
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#define STM32F7_I2C_ISR_ARLO BIT(9)
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#define STM32F7_I2C_ISR_BERR BIT(8)
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@ -82,14 +117,17 @@
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#define STM32F7_I2C_ISR_TC BIT(6)
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#define STM32F7_I2C_ISR_STOPF BIT(5)
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#define STM32F7_I2C_ISR_NACKF BIT(4)
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#define STM32F7_I2C_ISR_ADDR BIT(3)
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#define STM32F7_I2C_ISR_RXNE BIT(2)
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#define STM32F7_I2C_ISR_TXIS BIT(1)
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#define STM32F7_I2C_ISR_TXE BIT(0)
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/* STM32F7 I2C Interrupt Clear */
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#define STM32F7_I2C_ICR_ARLOCF BIT(9)
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#define STM32F7_I2C_ICR_BERRCF BIT(8)
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#define STM32F7_I2C_ICR_STOPCF BIT(5)
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#define STM32F7_I2C_ICR_NACKCF BIT(4)
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#define STM32F7_I2C_ICR_ADDRCF BIT(3)
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/* STM32F7 I2C Timing */
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#define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
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@ -99,6 +137,7 @@
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#define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
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#define STM32F7_I2C_MAX_LEN 0xff
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#define STM32F7_I2C_MAX_SLAVE 0x2
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#define STM32F7_I2C_DNF_DEFAULT 0
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#define STM32F7_I2C_DNF_MAX 16
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@ -209,6 +248,11 @@ struct stm32f7_i2c_msg {
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* @f7_msg: customized i2c msg for driver usage
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* @setup: I2C timing input setup
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* @timing: I2C computed timings
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* @slave: list of slave devices registered on the I2C bus
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* @slave_running: slave device currently used
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* @slave_dir: transfer direction for the current slave device
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* @master_mode: boolean to know in which mode the I2C is running (master or
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* slave)
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*/
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struct stm32f7_i2c_dev {
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struct i2c_adapter adap;
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@ -223,6 +267,10 @@ struct stm32f7_i2c_dev {
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struct stm32f7_i2c_msg f7_msg;
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struct stm32f7_i2c_setup setup;
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struct stm32f7_i2c_timings timing;
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struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
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struct i2c_client *slave_running;
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u32 slave_dir;
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bool master_mode;
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};
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/**
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@ -288,6 +336,11 @@ static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
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writel_relaxed(readl_relaxed(reg) & ~mask, reg);
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}
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static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
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{
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stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
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}
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static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
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struct stm32f7_i2c_setup *setup,
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struct stm32f7_i2c_timings *output)
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@ -572,6 +625,9 @@ static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
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if (f7_msg->count) {
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*f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
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f7_msg->count--;
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} else {
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/* Flush RX buffer has no data is expected */
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readb_relaxed(base + STM32F7_I2C_RXDR);
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}
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}
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@ -669,14 +725,250 @@ static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
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/* Configure Start/Repeated Start */
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cr2 |= STM32F7_I2C_CR2_START;
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i2c_dev->master_mode = true;
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/* Write configurations registers */
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writel_relaxed(cr1, base + STM32F7_I2C_CR1);
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writel_relaxed(cr2, base + STM32F7_I2C_CR2);
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}
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static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
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static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
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{
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stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
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u32 addr;
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if (!slave)
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return false;
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if (slave->flags & I2C_CLIENT_TEN) {
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/*
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* For 10-bit addr, addcode = 11110XY with
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* X = Bit 9 of slave address
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* Y = Bit 8 of slave address
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*/
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addr = slave->addr >> 8;
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addr |= 0x78;
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if (addr == addcode)
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return true;
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} else {
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addr = slave->addr & 0x7f;
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if (addr == addcode)
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return true;
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}
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return false;
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}
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static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
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{
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struct i2c_client *slave = i2c_dev->slave_running;
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void __iomem *base = i2c_dev->base;
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u32 mask;
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u8 value = 0;
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if (i2c_dev->slave_dir) {
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/* Notify i2c slave that new read transfer is starting */
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i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
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/*
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* Disable slave TX config in case of I2C combined message
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* (I2C Write followed by I2C Read)
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*/
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mask = STM32F7_I2C_CR2_RELOAD;
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stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
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mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
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STM32F7_I2C_CR1_TCIE;
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stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
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/* Enable TX empty, STOP, NACK interrupts */
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mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
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STM32F7_I2C_CR1_TXIE;
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stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
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} else {
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/* Notify i2c slave that new write transfer is starting */
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i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
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/* Set reload mode to be able to ACK/NACK each received byte */
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mask = STM32F7_I2C_CR2_RELOAD;
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stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
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/*
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* Set STOP, NACK, RX empty and transfer complete interrupts.*
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* Set Slave Byte Control to be able to ACK/NACK each data
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* byte received
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*/
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mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
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STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
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STM32F7_I2C_CR1_TCIE;
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stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
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}
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}
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static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
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{
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void __iomem *base = i2c_dev->base;
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u32 isr, addcode, dir, mask;
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int i;
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isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
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addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
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dir = isr & STM32F7_I2C_ISR_DIR;
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for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
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if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
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i2c_dev->slave_running = i2c_dev->slave[i];
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i2c_dev->slave_dir = dir;
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/* Start I2C slave processing */
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stm32f7_i2c_slave_start(i2c_dev);
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/* Clear ADDR flag */
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mask = STM32F7_I2C_ICR_ADDRCF;
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writel_relaxed(mask, base + STM32F7_I2C_ICR);
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break;
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}
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}
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}
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static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
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struct i2c_client *slave, int *id)
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{
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int i;
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for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
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if (i2c_dev->slave[i] == slave) {
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*id = i;
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return 0;
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}
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}
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dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
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return -ENODEV;
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}
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static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
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struct i2c_client *slave, int *id)
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{
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struct device *dev = i2c_dev->dev;
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int i;
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/*
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* slave[0] supports 7-bit and 10-bit slave address
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* slave[1] supports 7-bit slave address only
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*/
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for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
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if (i == 1 && (slave->flags & I2C_CLIENT_PEC))
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continue;
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if (!i2c_dev->slave[i]) {
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*id = i;
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return 0;
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}
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}
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dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
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return -EINVAL;
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}
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static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
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{
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int i;
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for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
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if (i2c_dev->slave[i])
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return true;
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}
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return false;
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}
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static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
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{
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int i, busy;
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busy = 0;
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for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
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if (i2c_dev->slave[i])
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busy++;
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}
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return i == busy;
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}
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static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
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{
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void __iomem *base = i2c_dev->base;
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u32 cr2, status, mask;
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u8 val;
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int ret;
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status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
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/* Slave transmitter mode */
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if (status & STM32F7_I2C_ISR_TXIS) {
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i2c_slave_event(i2c_dev->slave_running,
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I2C_SLAVE_READ_PROCESSED,
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&val);
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/* Write data byte */
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writel_relaxed(val, base + STM32F7_I2C_TXDR);
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}
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/* Transfer Complete Reload for Slave receiver mode */
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if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
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/*
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* Read data byte then set NBYTES to receive next byte or NACK
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* the current received byte
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*/
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val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
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ret = i2c_slave_event(i2c_dev->slave_running,
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I2C_SLAVE_WRITE_RECEIVED,
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&val);
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if (!ret) {
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cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
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cr2 |= STM32F7_I2C_CR2_NBYTES(1);
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writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
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} else {
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mask = STM32F7_I2C_CR2_NACK;
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stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
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}
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}
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/* NACK received */
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if (status & STM32F7_I2C_ISR_NACKF) {
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dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
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writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
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}
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/* STOP received */
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if (status & STM32F7_I2C_ISR_STOPF) {
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/* Disable interrupts */
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stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
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if (i2c_dev->slave_dir) {
|
||||
/*
|
||||
* Flush TX buffer in order to not used the byte in
|
||||
* TXDR for the next transfer
|
||||
*/
|
||||
mask = STM32F7_I2C_ISR_TXE;
|
||||
stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
|
||||
}
|
||||
|
||||
/* Clear STOP flag */
|
||||
writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
|
||||
|
||||
/* Notify i2c slave that a STOP flag has been detected */
|
||||
i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
|
||||
|
||||
i2c_dev->slave_running = NULL;
|
||||
}
|
||||
|
||||
/* Address match received */
|
||||
if (status & STM32F7_I2C_ISR_ADDR)
|
||||
stm32f7_i2c_slave_addr(i2c_dev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
||||
@ -685,6 +977,13 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
u32 status, mask;
|
||||
int ret;
|
||||
|
||||
/* Check if the interrupt if for a slave device */
|
||||
if (!i2c_dev->master_mode) {
|
||||
ret = stm32f7_i2c_slave_isr_event(i2c_dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
||||
|
||||
@ -706,11 +1005,16 @@ static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
|
||||
/* STOP detection flag */
|
||||
if (status & STM32F7_I2C_ISR_STOPF) {
|
||||
/* Disable interrupts */
|
||||
stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
||||
if (stm32f7_i2c_is_slave_registered(i2c_dev))
|
||||
mask = STM32F7_I2C_XFER_IRQ_MASK;
|
||||
else
|
||||
mask = STM32F7_I2C_ALL_IRQ_MASK;
|
||||
stm32f7_i2c_disable_irq(i2c_dev, mask);
|
||||
|
||||
/* Clear STOP flag */
|
||||
writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
|
||||
|
||||
i2c_dev->master_mode = false;
|
||||
complete(&i2c_dev->complete);
|
||||
}
|
||||
|
||||
@ -743,7 +1047,7 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
|
||||
struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
|
||||
void __iomem *base = i2c_dev->base;
|
||||
struct device *dev = i2c_dev->dev;
|
||||
u32 status;
|
||||
u32 mask, status;
|
||||
|
||||
status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
|
||||
|
||||
@ -761,8 +1065,14 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
|
||||
f7_msg->result = -EAGAIN;
|
||||
}
|
||||
|
||||
stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
||||
/* Disable interrupts */
|
||||
if (stm32f7_i2c_is_slave_registered(i2c_dev))
|
||||
mask = STM32F7_I2C_XFER_IRQ_MASK;
|
||||
else
|
||||
mask = STM32F7_I2C_ALL_IRQ_MASK;
|
||||
stm32f7_i2c_disable_irq(i2c_dev, mask);
|
||||
|
||||
i2c_dev->master_mode = false;
|
||||
complete(&i2c_dev->complete);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
@ -808,14 +1118,126 @@ clk_free:
|
||||
return (ret < 0) ? ret : num;
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
|
||||
{
|
||||
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
|
||||
void __iomem *base = i2c_dev->base;
|
||||
struct device *dev = i2c_dev->dev;
|
||||
u32 oar1, oar2, mask;
|
||||
int id, ret;
|
||||
|
||||
if (slave->flags & I2C_CLIENT_PEC) {
|
||||
dev_err(dev, "SMBus PEC not supported in slave mode\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
|
||||
dev_err(dev, "Too much slave registered\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
|
||||
ret = clk_enable(i2c_dev->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable clock\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
if (id == 0) {
|
||||
/* Configure Own Address 1 */
|
||||
oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
|
||||
oar1 &= ~STM32F7_I2C_OAR1_MASK;
|
||||
if (slave->flags & I2C_CLIENT_TEN) {
|
||||
oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
|
||||
oar1 |= STM32F7_I2C_OAR1_OA1MODE;
|
||||
} else {
|
||||
oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
|
||||
}
|
||||
oar1 |= STM32F7_I2C_OAR1_OA1EN;
|
||||
i2c_dev->slave[id] = slave;
|
||||
writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
|
||||
} else if (id == 1) {
|
||||
/* Configure Own Address 2 */
|
||||
oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
|
||||
oar2 &= ~STM32F7_I2C_OAR2_MASK;
|
||||
if (slave->flags & I2C_CLIENT_TEN) {
|
||||
ret = -EOPNOTSUPP;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
|
||||
oar2 |= STM32F7_I2C_OAR2_OA2EN;
|
||||
i2c_dev->slave[id] = slave;
|
||||
writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
|
||||
} else {
|
||||
ret = -ENODEV;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* Enable ACK */
|
||||
stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
|
||||
|
||||
/* Enable Address match interrupt, error interrupt and enable I2C */
|
||||
mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
|
||||
STM32F7_I2C_CR1_PE;
|
||||
stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
|
||||
|
||||
return 0;
|
||||
|
||||
exit:
|
||||
if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
|
||||
clk_disable(i2c_dev->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
|
||||
{
|
||||
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
|
||||
void __iomem *base = i2c_dev->base;
|
||||
u32 mask;
|
||||
int id, ret;
|
||||
|
||||
ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
WARN_ON(!i2c_dev->slave[id]);
|
||||
|
||||
if (id == 0) {
|
||||
mask = STM32F7_I2C_OAR1_OA1EN;
|
||||
stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
|
||||
} else {
|
||||
mask = STM32F7_I2C_OAR2_OA2EN;
|
||||
stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
|
||||
}
|
||||
|
||||
i2c_dev->slave[id] = NULL;
|
||||
|
||||
if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
|
||||
stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
|
||||
clk_disable(i2c_dev->clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
|
||||
I2C_FUNC_SLAVE;
|
||||
}
|
||||
|
||||
static struct i2c_algorithm stm32f7_i2c_algo = {
|
||||
.master_xfer = stm32f7_i2c_xfer,
|
||||
.functionality = stm32f7_i2c_func,
|
||||
.reg_slave = stm32f7_i2c_reg_slave,
|
||||
.unreg_slave = stm32f7_i2c_unreg_slave,
|
||||
};
|
||||
|
||||
static int stm32f7_i2c_probe(struct platform_device *pdev)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user