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[TG3]: Power down/up 5906 PHY correctly.

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The 5906 PHY requires a special register bit to power down and up the
PHY.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan 2006-12-17 17:08:07 -08:00 committed by David S. Miller
parent c49a1561ee
commit 60189ddff0
2 changed files with 17 additions and 1 deletions
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17
drivers/net/tg3.c
View File

@ -959,6 +959,13 @@ static int tg3_phy_reset(struct tg3 *tp)
u32 phy_status;
int err;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
u32 val;
val = tr32(GRC_MISC_CFG);
tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
udelay(40);
}
err = tg3_readphy(tp, MII_BMSR, &phy_status);
err |= tg3_readphy(tp, MII_BMSR, &phy_status);
if (err != 0)
@ -1170,7 +1177,15 @@ static void tg3_power_down_phy(struct tg3 *tp)
if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
return;
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
u32 val;
tg3_bmcr_reset(tp);
val = tr32(GRC_MISC_CFG);
tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
udelay(40);
return;
} else {
tg3_writephy(tp, MII_TG3_EXT_CTRL,
MII_TG3_EXT_CTRL_FORCE_LED_OFF);
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);

1
drivers/net/tg3.h
View File

@ -1350,6 +1350,7 @@
#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
#define GRC_LOCAL_CTRL 0x00006808
#define GRC_LCLCTRL_INT_ACTIVE 0x00000001