dt-bindings: ata: Add i.MX8QM AHCI compatible string

Add i.MX8QM AHCI "fsl,imx8qm-ahci" compatible strings.

i.MX8QM AHCI SATA doesn't require AHB clock rate to set the vendor
specified TIMER1MS register. ahb clock is not required by i.MX8QM AHCI.

Update the description of clocks in the dt-binding accordingly.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/1723428055-27021-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Niklas Cassel <cassel@kernel.org>
This commit is contained in:
Richard Zhu 2024-08-12 10:00:51 +08:00 committed by Niklas Cassel
parent bf1807c6ee
commit 5ff80684fb

View File

@ -19,6 +19,7 @@ properties:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
- fsl,imx8qm-ahci
reg:
maxItems: 1
@ -27,12 +28,14 @@ properties:
maxItems: 1
clocks:
minItems: 2
items:
- description: sata clock
- description: sata reference clock
- description: ahb clock
clock-names:
minItems: 2
items:
- const: sata
- const: sata_ref
@ -58,6 +61,25 @@ properties:
$ref: /schemas/types.yaml#/definitions/flag
description: if present, disable spread-spectrum clocking on the SATA link.
phys:
items:
- description: phandle to SATA PHY.
Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
calibration result will be stored, passed through second lane, and
shared with all three lanes PHY. The first two lanes PHY are used as
calibration PHYs, although only the third lane PHY is used by SATA.
- description: phandle to the first lane PHY of i.MX8QM.
- description: phandle to the second lane PHY of i.MX8QM.
phy-names:
items:
- const: sata-phy
- const: cali-phy0
- const: cali-phy1
power-domains:
maxItems: 1
required:
- compatible
- reg
@ -65,6 +87,31 @@ required:
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
then:
properties:
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-ahci
then:
properties:
clock-names:
minItems: 2
additionalProperties: false
examples: