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A couple fixes to the core framework logic that finds clk parents, a
handful of samsung clk driver fixes for audio and display clks, and a small fix for the Stratix10 SoC driver that was checking the wrong register for validity. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl1bI8sRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWJYRAAsaZUCBcuLpHXRBZDnO2/wWRQMxcl5yFi PDyaSfhqJ8M7IQJZ2pLY9eImVfKwzfJ0Xes2fMw5xAqVJsiXoRPgwEP1SuigTvEt qB9Ao3lXZkl37B5Hc/gKS/2xeDAdZfaAGE9ZwxYvVs38kikbBpxdOl8pTQbC8unt Cr6Ay+Gxh20FTDR68ug3jkWOtg3NfLMoM/Ynu+0WwAzsESGfcBZhOJRp50jaqe51 d+jO3YkUU5tA/YcJrJM5PWyZDb5EK2ONUcr7Em+/MvJlz80rPgdkwLGYz+5fgJBz QtDp664Gxaq+Uqq8GW/Uz+zvkoEnFKWbyAxXMwRHwDLVzaPO0Nm0LKFPLRcRNOuL qYe6hB+MekDelmeBoVYQ7JQEiPdZx5i9JcldZase+5hUzr5co1SVfl84LTz3il6d JJdm/PBv0AXQJXg39H3zcbbjEtVzfOI7FZqTLiruxm9wkT7kRyEcj5BB9zpIMEY1 4MatzJL5uiZnAuPA3BA/FB/5lK6bJu6arIdRK4pXRYZvvw5gEvGBJCCvA6pY+z6n iqPazWPcyRIiBon2o3UqRkZxBeiKhfsXyeNNq15jQh7pq7W+D6r+G/NSbV5hv2Ji OeqXV/zhdIfYayfJXzpSxiLYaNDq+qPn0AWLPcm35Sj5wfOZKM3jg6ZFkPgaq6n8 kr7r417ixuc= =1qKh -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A couple fixes to the core framework logic that finds clk parents, a handful of samsung clk driver fixes for audio and display clks, and a small fix for the Stratix10 SoC driver that was checking the wrong register for validity" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: Fix potential NULL dereference in clk_fetch_parent_index() clk: Fix falling back to legacy parent string matching clk: socfpga: stratix10: fix rate caclulationg for cnt_clks clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU clk: samsung: Change signature of exynos5_subcmus_init() function
This commit is contained in:
Linus Torvalds
commit
5f97cbe22b
@ -324,6 +324,25 @@ static struct clk_core *clk_core_lookup(const char *name)
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return NULL;
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}
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#ifdef CONFIG_OF
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static int of_parse_clkspec(const struct device_node *np, int index,
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const char *name, struct of_phandle_args *out_args);
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static struct clk_hw *
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of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec);
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#else
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static inline int of_parse_clkspec(const struct device_node *np, int index,
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const char *name,
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struct of_phandle_args *out_args)
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{
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return -ENOENT;
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}
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static inline struct clk_hw *
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of_clk_get_hw_from_clkspec(struct of_phandle_args *clkspec)
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{
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return ERR_PTR(-ENOENT);
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}
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#endif
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/**
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* clk_core_get - Find the clk_core parent of a clk
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* @core: clk to find parent of
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@ -355,8 +374,9 @@ static struct clk_core *clk_core_lookup(const char *name)
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* };
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*
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* Returns: -ENOENT when the provider can't be found or the clk doesn't
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* exist in the provider. -EINVAL when the name can't be found. NULL when the
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* provider knows about the clk but it isn't provided on this system.
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* exist in the provider or the name can't be found in the DT node or
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* in a clkdev lookup. NULL when the provider knows about the clk but it
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* isn't provided on this system.
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* A valid clk_core pointer when the clk can be found in the provider.
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*/
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static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
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@ -367,17 +387,19 @@ static struct clk_core *clk_core_get(struct clk_core *core, u8 p_index)
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struct device *dev = core->dev;
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const char *dev_id = dev ? dev_name(dev) : NULL;
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struct device_node *np = core->of_node;
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struct of_phandle_args clkspec;
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if (np && (name || index >= 0))
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hw = of_clk_get_hw(np, index, name);
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/*
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* If the DT search above couldn't find the provider or the provider
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* didn't know about this clk, fallback to looking up via clkdev based
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* clk_lookups
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*/
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if (PTR_ERR(hw) == -ENOENT && name)
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if (np && (name || index >= 0) &&
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!of_parse_clkspec(np, index, name, &clkspec)) {
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hw = of_clk_get_hw_from_clkspec(&clkspec);
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of_node_put(clkspec.np);
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} else if (name) {
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/*
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* If the DT search above couldn't find the provider fallback to
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* looking up via clkdev based clk_lookups.
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*/
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hw = clk_find_hw(dev_id, name);
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}
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if (IS_ERR(hw))
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return ERR_CAST(hw);
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@ -401,7 +423,7 @@ static void clk_core_fill_parent_index(struct clk_core *core, u8 index)
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parent = ERR_PTR(-EPROBE_DEFER);
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} else {
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parent = clk_core_get(core, index);
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if (IS_ERR(parent) && PTR_ERR(parent) == -ENOENT)
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if (IS_ERR(parent) && PTR_ERR(parent) == -ENOENT && entry->name)
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parent = clk_core_lookup(entry->name);
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}
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@ -1632,7 +1654,8 @@ static int clk_fetch_parent_index(struct clk_core *core,
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break;
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/* Fallback to comparing globally unique names */
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if (!strcmp(parent->name, core->parents[i].name))
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if (core->parents[i].name &&
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!strcmp(parent->name, core->parents[i].name))
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break;
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}
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@ -14,7 +14,7 @@
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#include "clk-exynos5-subcmu.h"
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static struct samsung_clk_provider *ctx;
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static const struct exynos5_subcmu_info *cmu;
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static const struct exynos5_subcmu_info **cmu;
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static int nr_cmus;
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static void exynos5_subcmu_clk_save(void __iomem *base,
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@ -56,17 +56,17 @@ static void exynos5_subcmu_defer_gate(struct samsung_clk_provider *ctx,
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* when OF-core populates all device-tree nodes.
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*/
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void exynos5_subcmus_init(struct samsung_clk_provider *_ctx, int _nr_cmus,
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const struct exynos5_subcmu_info *_cmu)
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const struct exynos5_subcmu_info **_cmu)
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{
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ctx = _ctx;
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cmu = _cmu;
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nr_cmus = _nr_cmus;
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for (; _nr_cmus--; _cmu++) {
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exynos5_subcmu_defer_gate(ctx, _cmu->gate_clks,
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_cmu->nr_gate_clks);
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exynos5_subcmu_clk_save(ctx->reg_base, _cmu->suspend_regs,
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_cmu->nr_suspend_regs);
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exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks,
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(*_cmu)->nr_gate_clks);
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exynos5_subcmu_clk_save(ctx->reg_base, (*_cmu)->suspend_regs,
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(*_cmu)->nr_suspend_regs);
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}
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}
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@ -163,9 +163,9 @@ static int __init exynos5_clk_probe(struct platform_device *pdev)
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if (of_property_read_string(np, "label", &name) < 0)
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continue;
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for (i = 0; i < nr_cmus; i++)
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if (strcmp(cmu[i].pd_name, name) == 0)
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if (strcmp(cmu[i]->pd_name, name) == 0)
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exynos5_clk_register_subcmu(&pdev->dev,
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&cmu[i], np);
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cmu[i], np);
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}
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return 0;
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}
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@ -21,6 +21,6 @@ struct exynos5_subcmu_info {
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};
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void exynos5_subcmus_init(struct samsung_clk_provider *ctx, int nr_cmus,
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const struct exynos5_subcmu_info *cmu);
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const struct exynos5_subcmu_info **cmu);
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#endif
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@ -681,6 +681,10 @@ static const struct exynos5_subcmu_info exynos5250_disp_subcmu = {
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.pd_name = "DISP1",
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};
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static const struct exynos5_subcmu_info *exynos5250_subcmus[] = {
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&exynos5250_disp_subcmu,
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};
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static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = {
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/* sorted in descending order */
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/* PLL_36XX_RATE(rate, m, p, s, k) */
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@ -843,7 +847,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
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samsung_clk_sleep_init(reg_base, exynos5250_clk_regs,
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ARRAY_SIZE(exynos5250_clk_regs));
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exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu);
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exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5250_subcmus),
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exynos5250_subcmus);
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samsung_clk_of_add_provider(np, ctx);
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@ -534,8 +534,6 @@ static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
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GATE_BUS_TOP, 24, 0, 0),
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GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
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GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
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GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
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SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
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};
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static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
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@ -577,8 +575,13 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
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static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
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GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
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/* Maudio Block */
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GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
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SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
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GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
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GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
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};
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static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
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@ -890,9 +893,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
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/* GSCL Block */
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DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
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/* MSCL Block */
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DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
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/* PSGEN */
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DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
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DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
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@ -1017,12 +1017,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
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GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
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GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
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/* Maudio Block */
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GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
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GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
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GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
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/* FSYS Block */
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GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
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GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
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@ -1162,17 +1156,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
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GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
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GATE_IP_GSCL1, 17, 0, 0),
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/* MSCL Block */
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GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
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GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
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GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
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GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
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GATE_IP_MSCL, 8, 0, 0),
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GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
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GATE_IP_MSCL, 9, 0, 0),
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GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
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GATE_IP_MSCL, 10, 0, 0),
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/* ISP */
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GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
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GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
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@ -1281,32 +1264,103 @@ static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
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{ DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
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};
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static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
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{
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.div_clks = exynos5x_disp_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
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.gate_clks = exynos5x_disp_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
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.suspend_regs = exynos5x_disp_suspend_regs,
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.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
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.pd_name = "DISP",
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}, {
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.div_clks = exynos5x_gsc_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
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.gate_clks = exynos5x_gsc_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
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.suspend_regs = exynos5x_gsc_suspend_regs,
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.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
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.pd_name = "GSC",
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}, {
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.div_clks = exynos5x_mfc_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
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.gate_clks = exynos5x_mfc_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
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.suspend_regs = exynos5x_mfc_suspend_regs,
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.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
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.pd_name = "MFC",
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},
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static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
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/* MSCL Block */
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GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
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GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
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GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
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GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
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GATE_IP_MSCL, 8, 0, 0),
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GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
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GATE_IP_MSCL, 9, 0, 0),
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GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
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GATE_IP_MSCL, 10, 0, 0),
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};
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static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
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DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
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};
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static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
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{ GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
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{ SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
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{ DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
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};
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static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
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GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
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SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
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GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
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GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
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};
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static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
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{ SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
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};
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static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
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.div_clks = exynos5x_disp_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
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.gate_clks = exynos5x_disp_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
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.suspend_regs = exynos5x_disp_suspend_regs,
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.nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
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.pd_name = "DISP",
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};
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|
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static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
|
||||
.div_clks = exynos5x_gsc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
|
||||
.gate_clks = exynos5x_gsc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
|
||||
.suspend_regs = exynos5x_gsc_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
|
||||
.pd_name = "GSC",
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
|
||||
.div_clks = exynos5x_mfc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
|
||||
.gate_clks = exynos5x_mfc_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
|
||||
.suspend_regs = exynos5x_mfc_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
|
||||
.pd_name = "MFC",
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
|
||||
.div_clks = exynos5x_mscl_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
|
||||
.gate_clks = exynos5x_mscl_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
|
||||
.suspend_regs = exynos5x_mscl_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
|
||||
.pd_name = "MSC",
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
|
||||
.gate_clks = exynos5800_mau_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
|
||||
.suspend_regs = exynos5800_mau_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
|
||||
.pd_name = "MAU",
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
|
||||
&exynos5x_disp_subcmu,
|
||||
&exynos5x_gsc_subcmu,
|
||||
&exynos5x_mfc_subcmu,
|
||||
&exynos5x_mscl_subcmu,
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
|
||||
&exynos5x_disp_subcmu,
|
||||
&exynos5x_gsc_subcmu,
|
||||
&exynos5x_mfc_subcmu,
|
||||
&exynos5x_mscl_subcmu,
|
||||
&exynos5800_mau_subcmu,
|
||||
};
|
||||
|
||||
static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
|
||||
@ -1539,11 +1593,17 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
||||
samsung_clk_extended_sleep_init(reg_base,
|
||||
exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
|
||||
exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
|
||||
if (soc == EXYNOS5800)
|
||||
|
||||
if (soc == EXYNOS5800) {
|
||||
samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
|
||||
ARRAY_SIZE(exynos5800_clk_regs));
|
||||
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
|
||||
exynos5x_subcmus);
|
||||
|
||||
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
|
||||
exynos5800_subcmus);
|
||||
} else {
|
||||
exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
|
||||
exynos5x_subcmus);
|
||||
}
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
|
||||
if (socfpgaclk->fixed_div) {
|
||||
div = socfpgaclk->fixed_div;
|
||||
} else {
|
||||
if (!socfpgaclk->bypass_reg)
|
||||
if (socfpgaclk->hw.reg)
|
||||
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user