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KVM: arm/arm64: vgic: Handle GICR_PENDBASER.PTZ filed as RAZ

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Although guest will hardly read and use the PTZ (Pending Table Zero)
bit in GICR_PENDBASER, let us emulate the architecture strictly.
As per IHI 0069E 9.11.30, PTZ field is WO, and reads as 0.

Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20191220111833.1422-1-yuzenghui@huawei.com
This commit is contained in:
Zenghui Yu 2019-12-20 19:18:33 +08:00 committed by Marc Zyngier
parent 8c58be3449
commit 5f675c56ed
1 changed files with 4 additions and 1 deletions
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5
virt/kvm/arm/vgic/vgic-mmio-v3.c
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@ -414,8 +414,11 @@ static unsigned long vgic_mmio_read_pendbase(struct kvm_vcpu *vcpu,
gpa_t addr, unsigned int len)
{
struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
u64 value = vgic_cpu->pendbaser;
return extract_bytes(vgic_cpu->pendbaser, addr & 7, len);
value &= ~GICR_PENDBASER_PTZ;
return extract_bytes(value, addr & 7, len);
}
static void vgic_mmio_write_pendbase(struct kvm_vcpu *vcpu,