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drm/amd/display: quality improvements for EASF and ISHARP

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[Why]
Update coefficients and LUT tables for scaler and sharpener
 to improve quality and support different use cases (SDR/HDR)

[How]
Move scaler coefficients to new file dc_spl_scl_easf_filters.c
Remove older coefficients file dc_sp_scl_filters_old.c
Update default taps for EASF support
Update LLS policy for DON'T CARE case
Update cositing offset from 0.5 to 0.25
Add support to adjust sharpness based on level, use case,
 and scaling ratio ( using discrete levels )
Apply sharpness to all RGB surfaces and both NV12 and P010
 video ( in fullscreen only ).  Upscale and 1:1 ratios only
Enable scaler when sharpening 1:1 ratios
Add support for coefficients that are in S1.10 format
 (convert to S1.12 format)

Reviewed-by: Jun Lei <jun.lei@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Samson Tam <samson.tam@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Samson Tam 2024-06-20 15:42:45 -04:00 committed by Alex Deucher
parent 4ccc8fdcca
commit 5f30ee4930
19 changed files with 3201 additions and 750 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
View File

@ -1286,3 +1286,15 @@ enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link)
return as_type;
}
bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream)
{
// TODO
return false;
}
bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream)
{
// TODO
return false;
}

7
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View File

@ -763,13 +763,6 @@ enum scanning_type {
SCANNING_TYPE_UNDEFINED
};
enum chroma_cositing {
CHROMA_COSITING_NONE,
CHROMA_COSITING_LEFT,
CHROMA_COSITING_TOPLEFT,
CHROMA_COSITING_COUNT
};
struct dc_crtc_timing_flags {
uint32_t INTERLACE :1;
uint32_t HSYNC_POSITIVE_POLARITY :1; /* when set to 1,

5
drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
View File

@ -170,6 +170,11 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
/* Translate transfer function */
spl_in->basic_in.tf_type = (enum spl_transfer_func_type) plane_state->in_transfer_func.type;
spl_in->basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state->in_transfer_func.tf;
/* Check if it is stream is in fullscreen and if its HDR.
* Use this to determine sharpness levels
*/
spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream);
spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream);
}

1
drivers/gpu/drm/amd/display/dc/dc_spl_translate.h
View File

@ -6,6 +6,7 @@
#define __DC_SPL_TRANSLATE_H__
#include "dc.h"
#include "resource.h"
#include "dm_helpers.h"
/* Map SPL input parameters to pipe context
* @pipe_ctx: pipe context

3
drivers/gpu/drm/amd/display/dc/dm_helpers.h
View File

@ -210,4 +210,7 @@ enum adaptive_sync_type dm_get_adaptive_sync_support_type(struct dc_link *link);
enum dc_edid_status dm_helpers_get_sbios_edid(struct dc_link *link, struct dc_edid *edid);
bool dm_helpers_is_fullscreen(struct dc_context *ctx, struct dc_stream_state *stream);
bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream);
#endif /* __DM_HELPERS__ */

8
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
View File

@ -788,6 +788,14 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm
* certain cases. Hence do corrective active and disable scaling.
*/
plane->composition.scaler_info.enabled = false;
} else if ((plane_state->ctx->dc->config.use_spl == true) &&
(plane->composition.scaler_info.enabled == false)) {
/* To enable sharpener for 1:1, scaler must be enabled. If use_spl is set, then
* allow case where ratio is 1 but taps > 1
*/
if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) ||
(scaler_data->taps.h_taps_c > 1) || (scaler_data->taps.v_taps_c > 1))
plane->composition.scaler_info.enabled = true;
}
/* always_scale is only used for debug purposes not used in production but has to be

618
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c
View File

@ -655,6 +655,226 @@ static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp,
/* Number of RECOUT vertical lines */
RECOUT_HEIGHT, recout->height);
}
/**
* dpp401_dscl_program_easf_v - Program EASF_V
*
* @dpp_base: High level DPP struct
* @scl_data: scalaer_data info
*
* This is the primary function to program vertical EASF registers
*
*/
static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data)
{
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
PERF_TRACE();
/* DSCL_EASF_V_MODE */
REG_SET_3(DSCL_EASF_V_MODE, 0,
SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en,
SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor,
SCL_EASF_V_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_v_ring);
if (!scl_data->dscl_prog_data.easf_v_en) {
PERF_TRACE();
return;
}
/* DSCL_EASF_V_BF_CNTL */
REG_SET_6(DSCL_EASF_V_BF_CNTL, 0,
SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en,
SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode,
SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode,
SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain,
SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain,
SCL_EASF_V_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_v_bf2_roc_gain);
/* DSCL_EASF_V_RINGEST_3TAP_CNTLn */
REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL1, 0,
SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt,
SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt_max);
REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL2, 0,
SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope,
SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope);
REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL3, 0,
SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope,
SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset);
/* DSCL_EASF_V_RINGEST_EVENTAP_REDUCE */
REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, 0,
SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1,
SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg2);
/* DSCL_EASF_V_RINGEST_EVENTAP_GAIN */
REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, 0,
SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1,
SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain2);
/* DSCL_EASF_V_BF_FINAL_MAX_MIN */
REG_SET_4(DSCL_EASF_V_BF_FINAL_MAX_MIN, 0,
SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa,
SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb,
SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina,
SCL_EASF_V_BF_MINB, scl_data->dscl_prog_data.easf_v_bf_minb);
/* DSCL_EASF_V_BF1_PWL_SEGn */
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG0, 0,
SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0,
SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0,
SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg0);
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG1, 0,
SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1,
SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1,
SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg1);
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG2, 0,
SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2,
SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2,
SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg2);
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG3, 0,
SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3,
SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3,
SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg3);
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG4, 0,
SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4,
SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4,
SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg4);
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG5, 0,
SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5,
SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5,
SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg5);
REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG6, 0,
SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6,
SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6,
SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg6);
REG_SET_2(DSCL_EASF_V_BF1_PWL_SEG7, 0,
SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7,
SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg7);
/* DSCL_EASF_V_BF3_PWL_SEGn */
REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG0, 0,
SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0,
SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0,
SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set0);
REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG1, 0,
SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1,
SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1,
SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set1);
REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG2, 0,
SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2,
SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2,
SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set2);
REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG3, 0,
SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3,
SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3,
SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set3);
REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG4, 0,
SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4,
SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4,
SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set4);
REG_SET_2(DSCL_EASF_V_BF3_PWL_SEG5, 0,
SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5,
SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set5);
PERF_TRACE();
}
/**
* dpp401_dscl_program_easf_h - Program EASF_H
*
* @dpp_base: High level DPP struct
* @scl_data: scalaer_data info
*
* This is the primary function to program horizontal EASF registers
*
*/
static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data)
{
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
PERF_TRACE();
/* DSCL_EASF_H_MODE */
REG_SET_3(DSCL_EASF_H_MODE, 0,
SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en,
SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor,
SCL_EASF_H_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_h_ring);
if (!scl_data->dscl_prog_data.easf_h_en) {
PERF_TRACE();
return;
}
/* DSCL_EASF_H_BF_CNTL */
REG_SET_6(DSCL_EASF_H_BF_CNTL, 0,
SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en,
SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode,
SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode,
SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain,
SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain,
SCL_EASF_H_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_h_bf2_roc_gain);
/* DSCL_EASF_H_RINGEST_EVENTAP_REDUCE */
REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, 0,
SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1,
SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg2);
/* DSCL_EASF_H_RINGEST_EVENTAP_GAIN */
REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, 0,
SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1,
SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain2);
/* DSCL_EASF_H_BF_FINAL_MAX_MIN */
REG_SET_4(DSCL_EASF_H_BF_FINAL_MAX_MIN, 0,
SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa,
SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb,
SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina,
SCL_EASF_H_BF_MINB, scl_data->dscl_prog_data.easf_h_bf_minb);
/* DSCL_EASF_H_BF1_PWL_SEGn */
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG0, 0,
SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0,
SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0,
SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg0);
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG1, 0,
SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1,
SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1,
SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg1);
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG2, 0,
SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2,
SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2,
SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg2);
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG3, 0,
SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3,
SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3,
SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg3);
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG4, 0,
SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4,
SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4,
SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg4);
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG5, 0,
SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5,
SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5,
SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg5);
REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG6, 0,
SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6,
SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6,
SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg6);
REG_SET_2(DSCL_EASF_H_BF1_PWL_SEG7, 0,
SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7,
SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg7);
/* DSCL_EASF_H_BF3_PWL_SEGn */
REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG0, 0,
SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0,
SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0,
SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set0);
REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG1, 0,
SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1,
SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1,
SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set1);
REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG2, 0,
SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2,
SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2,
SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set2);
REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG3, 0,
SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3,
SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3,
SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set3);
REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG4, 0,
SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4,
SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4,
SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set4);
REG_SET_2(DSCL_EASF_H_BF3_PWL_SEG5, 0,
SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5,
SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set5);
PERF_TRACE();
}
/**
* dpp401_dscl_program_easf - Program EASF
*
@ -669,261 +889,19 @@ static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_d
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
PERF_TRACE();
REG_UPDATE(DSCL_SC_MODE,
SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode);
REG_UPDATE(DSCL_SC_MODE,
/* DSCL_SC_MODE */
REG_SET_2(DSCL_SC_MODE, 0,
SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode,
SCL_SC_LTONL_EN, scl_data->dscl_prog_data.easf_ltonl_en);
/* DSCL_EASF_V_MODE */
REG_UPDATE(DSCL_EASF_V_MODE,
SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en);
REG_UPDATE(DSCL_EASF_V_MODE,
SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor);
REG_UPDATE(DSCL_EASF_V_MODE,
SCL_EASF_V_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_v_ring);
REG_UPDATE(DSCL_EASF_V_BF_CNTL,
SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en);
REG_UPDATE(DSCL_EASF_V_BF_CNTL,
SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode);
REG_UPDATE(DSCL_EASF_V_BF_CNTL,
SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode);
REG_UPDATE(DSCL_EASF_V_BF_CNTL,
SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain);
REG_UPDATE(DSCL_EASF_V_BF_CNTL,
SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain);
REG_UPDATE(DSCL_EASF_V_BF_CNTL,
SCL_EASF_V_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_v_bf2_roc_gain);
REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL1,
SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt);
REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL1,
SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt_max);
REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL2,
SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope);
REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL2,
SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope);
REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL3,
SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope);
REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL3,
SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset);
REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE,
SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1);
REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE,
SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg2);
REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_GAIN,
SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1);
REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_GAIN,
SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain2);
REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN,
SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa);
REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN,
SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb);
REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN,
SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina);
REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN,
SCL_EASF_V_BF_MINB, scl_data->dscl_prog_data.easf_v_bf_minb);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG0,
SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG0,
SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG0,
SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg0);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG1,
SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG1,
SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG1,
SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg1);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG2,
SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG2,
SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG2,
SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg2);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG3,
SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG3,
SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG3,
SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg3);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG4,
SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG4,
SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG4,
SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg4);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG5,
SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG5,
SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG5,
SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg5);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG6,
SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG6,
SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG6,
SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg6);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG7,
SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7);
REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG7,
SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg7);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG0,
SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG0,
SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG0,
SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set0);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG1,
SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG1,
SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG1,
SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set1);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG2,
SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG2,
SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG2,
SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set2);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG3,
SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG3,
SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG3,
SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set3);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG4,
SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG4,
SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG4,
SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set4);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG5,
SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5);
REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG5,
SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set5);
/* DSCL_EASF_H_MODE */
REG_UPDATE(DSCL_EASF_H_MODE,
SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en);
REG_UPDATE(DSCL_EASF_H_MODE,
SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor);
REG_UPDATE(DSCL_EASF_H_MODE,
SCL_EASF_H_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_h_ring);
REG_UPDATE(DSCL_EASF_H_BF_CNTL,
SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en);
REG_UPDATE(DSCL_EASF_H_BF_CNTL,
SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode);
REG_UPDATE(DSCL_EASF_H_BF_CNTL,
SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode);
REG_UPDATE(DSCL_EASF_H_BF_CNTL,
SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain);
REG_UPDATE(DSCL_EASF_H_BF_CNTL,
SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain);
REG_UPDATE(DSCL_EASF_H_BF_CNTL,
SCL_EASF_H_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_h_bf2_roc_gain);
REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE,
SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1);
REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE,
SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg2);
REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_GAIN,
SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1);
REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_GAIN,
SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain2);
REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN,
SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa);
REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN,
SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb);
REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN,
SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina);
REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN,
SCL_EASF_H_BF_MINB, scl_data->dscl_prog_data.easf_h_bf_minb);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG0,
SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG0,
SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG0,
SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg0);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG1,
SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG1,
SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG1,
SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg1);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG2,
SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG2,
SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG2,
SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg2);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG3,
SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG3,
SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG3,
SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg3);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG4,
SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG4,
SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG4,
SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg4);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG5,
SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG5,
SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG5,
SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg5);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG6,
SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG6,
SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG6,
SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg6);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG7,
SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7);
REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG7,
SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg7);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG0,
SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG0,
SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG0,
SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set0);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG1,
SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG1,
SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG1,
SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set1);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG2,
SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG2,
SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG2,
SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set2);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG3,
SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG3,
SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG3,
SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set3);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG4,
SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG4,
SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG4,
SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set4);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG5,
SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5);
REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG5,
SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set5);
/* DSCL_EASF_SC_MATRIX_C0C1, DSCL_EASF_SC_MATRIX_C2C3 */
REG_UPDATE(DSCL_SC_MATRIX_C0C1,
SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0);
REG_UPDATE(DSCL_SC_MATRIX_C0C1,
REG_SET_2(DSCL_SC_MATRIX_C0C1, 0,
SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0,
SCL_SC_MATRIX_C1, scl_data->dscl_prog_data.easf_matrix_c1);
REG_UPDATE(DSCL_SC_MATRIX_C2C3,
SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2);
REG_UPDATE(DSCL_SC_MATRIX_C2C3,
REG_SET_2(DSCL_SC_MATRIX_C2C3, 0,
SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2,
SCL_SC_MATRIX_C3, scl_data->dscl_prog_data.easf_matrix_c3);
dpp401_dscl_program_easf_v(dpp_base, scl_data);
dpp401_dscl_program_easf_h(dpp_base, scl_data);
PERF_TRACE();
}
/**
@ -958,10 +936,11 @@ static void dpp401_dscl_set_isharp_filter(
REG_UPDATE(ISHARP_DELTA_CTRL,
ISHARP_DELTA_LUT_HOST_SELECT, 0);
/* LUT data write is auto-indexed. Write index once */
REG_SET(ISHARP_DELTA_INDEX, 0,
ISHARP_DELTA_INDEX, 0);
for (level = 0; level < NUM_LEVELS; level++) {
filter_data = filter[level];
REG_SET(ISHARP_DELTA_INDEX, 0,
ISHARP_DELTA_INDEX, level);
REG_SET(ISHARP_DELTA_DATA, 0,
ISHARP_DELTA_DATA, filter_data);
}
@ -981,102 +960,67 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base,
struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
PERF_TRACE();
/* ISHARP_EN */
REG_UPDATE(ISHARP_MODE,
ISHARP_EN, scl_data->dscl_prog_data.isharp_en);
/* ISHARP_NOISEDET_EN */
REG_UPDATE(ISHARP_MODE,
ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable);
/* ISHARP_NOISEDET_MODE */
REG_UPDATE(ISHARP_MODE,
ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode);
/* ISHARP_NOISEDET_UTHRE */
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold);
/* ISHARP_NOISEDET_DTHRE */
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
/* ISHARP_MODE */
REG_SET_6(ISHARP_MODE, 0,
ISHARP_EN, scl_data->dscl_prog_data.isharp_en,
ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable,
ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode,
ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode,
ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode,
ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);
/* Skip remaining register programming if ISHARP is disabled */
if (!scl_data->dscl_prog_data.isharp_en) {
PERF_TRACE();
return;
}
/* ISHARP_NOISEDET_THRESHOLD */
REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0,
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold,
ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);
REG_UPDATE(ISHARP_MODE,
ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode);
/* ISHARP_NOISEDET_UTHRE */
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold);
/* ISHARP_NOISEDET_DTHRE */
REG_UPDATE(ISHARP_NOISEDET_THRESHOLD,
ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);
/* ISHARP_NOISEDET_PWL_START_IN */
REG_UPDATE(ISHARP_NOISE_GAIN_PWL,
ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in);
/* ISHARP_NOISEDET_PWL_END_IN */
REG_UPDATE(ISHARP_NOISE_GAIN_PWL,
ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in);
/* ISHARP_NOISEDET_PWL_SLOPE */
REG_UPDATE(ISHARP_NOISE_GAIN_PWL,
/* ISHARP_NOISE_GAIN_PWL */
REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0,
ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in,
ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in,
ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope);
/* ISHARP_LBA_MODE */
REG_UPDATE(ISHARP_MODE,
ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode);
/* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */
REG_UPDATE(ISHARP_LBA_PWL_SEG0,
ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0]);
REG_UPDATE(ISHARP_LBA_PWL_SEG0,
ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0]);
REG_UPDATE(ISHARP_LBA_PWL_SEG0,
REG_SET_3(ISHARP_LBA_PWL_SEG0, 0,
ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0],
ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0],
ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);
REG_UPDATE(ISHARP_LBA_PWL_SEG1,
ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1]);
REG_UPDATE(ISHARP_LBA_PWL_SEG1,
ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1]);
REG_UPDATE(ISHARP_LBA_PWL_SEG1,
REG_SET_3(ISHARP_LBA_PWL_SEG1, 0,
ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1],
ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1],
ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);
REG_UPDATE(ISHARP_LBA_PWL_SEG2,
ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2]);
REG_UPDATE(ISHARP_LBA_PWL_SEG2,
ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2]);
REG_UPDATE(ISHARP_LBA_PWL_SEG2,
REG_SET_3(ISHARP_LBA_PWL_SEG2, 0,
ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2],
ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2],
ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);
REG_UPDATE(ISHARP_LBA_PWL_SEG3,
ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3]);
REG_UPDATE(ISHARP_LBA_PWL_SEG3,
ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3]);
REG_UPDATE(ISHARP_LBA_PWL_SEG3,
REG_SET_3(ISHARP_LBA_PWL_SEG3, 0,
ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3],
ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3],
ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);
REG_UPDATE(ISHARP_LBA_PWL_SEG4,
ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4]);
REG_UPDATE(ISHARP_LBA_PWL_SEG4,
ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4]);
REG_UPDATE(ISHARP_LBA_PWL_SEG4,
REG_SET_3(ISHARP_LBA_PWL_SEG4, 0,
ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4],
ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4],
ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);
REG_UPDATE(ISHARP_LBA_PWL_SEG5,
ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5]);
REG_UPDATE(ISHARP_LBA_PWL_SEG5,
REG_SET_2(ISHARP_LBA_PWL_SEG5, 0,
ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5],
ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);
/* ISHARP_FMT_MODE */
REG_UPDATE(ISHARP_MODE,
ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode);
/* ISHARP_FMT_NORM */
REG_UPDATE(ISHARP_MODE,
ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);
/* ISHARP_DELTA_LUT */
dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);
/* ISHARP_NLDELTA_SCLIP_EN_P */
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p);
/* ISHARP_NLDELTA_SCLIP_PIVOT_P */
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p);
/* ISHARP_NLDELTA_SCLIP_SLOPE_P */
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p);
/* ISHARP_NLDELTA_SCLIP_EN_N */
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n);
/* ISHARP_NLDELTA_SCLIP_PIVOT_N */
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n);
/* ISHARP_NLDELTA_SCLIP_SLOPE_N */
REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP,
/* ISHARP_NLDELTA_SOFT_CLIP */
REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0,
ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p,
ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p,
ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p,
ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n,
ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n,
ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);
/* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */

7
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
View File

@ -76,6 +76,9 @@
#include "dml2/dml2_wrapper.h"
#include "spl/dc_spl_scl_easf_filters.h"
#include "spl/dc_spl_isharp_filters.h"
#define DC_LOGGER_INIT(logger)
enum dcn401_clk_src_array_id {
@ -2123,6 +2126,10 @@ static bool dcn401_resource_construct(
dc->dml2_options.max_segments_per_hubp = 20;
dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
/* SPL */
spl_init_easf_filter_coeffs();
spl_init_blur_scale_coeffs();
return true;
create_fail:

2
drivers/gpu/drm/amd/display/dc/spl/Makefile
View File

@ -23,7 +23,7 @@
# Makefile for the 'spl' sub-component of DAL.
# It provides the scaling library interface.
SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_isharp_filters.o
SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o
AMD_DAL_SPL = $(addprefix $(AMDDALPATH)/dc/spl/,$(SPL))

958
drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
View File

File diff suppressed because it is too large Load Diff

15
drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.c Normal file
View File

@ -0,0 +1,15 @@
// SPDX-License-Identifier: MIT
//
// Copyright 2024 Advanced Micro Devices, Inc.
#include "dc_spl_filters.h"
void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter,
uint16_t *s1_12_filter, int num_taps)
{
int num_entries = NUM_PHASES_COEFF * num_taps;
int i;
for (i = 0; i < num_entries; i++)
*(s1_12_filter + i) = *(s1_10_filter + i) * 4;
}

15
drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.h Normal file
View File

@ -0,0 +1,15 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2024 Advanced Micro Devices, Inc. */
#ifndef __DC_SPL_FILTERS_H__
#define __DC_SPL_FILTERS_H__
#include "dc_spl_types.h"
#define NUM_PHASES_COEFF 33
void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter,
uint16_t *s1_12_filter, int num_taps);
#endif /* __DC_SPL_FILTERS_H__ */

427
drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c
View File

@ -3,6 +3,7 @@
// Copyright 2024 Advanced Micro Devices, Inc.
#include "dc_spl_types.h"
#include "dc_spl_filters.h"
#include "dc_spl_isharp_filters.h"
//========================================
@ -231,6 +232,53 @@ static const uint32_t filter_isharp_1D_lut_2p0x[32] = {
0x080B0D0E,
0x00020406,
};
//========================================
// Delta Gain 1DLUT
// LUT content is packed as 4-bytes into one DWORD/entry
// A_start = 0.000000
// A_end = 10.000000
// A_gain = 3.000000
// B_start = 11.000000
// B_end = 127.000000
// C_start = 40.000000
// C_end = 127.000000
//========================================
static const uint32_t filter_isharp_1D_lut_3p0x[32] = {
0x03010000,
0x0F0B0805,
0x211E1813,
0x2B292624,
0x3533302E,
0x3E3C3A37,
0x46444240,
0x4D4B4A48,
0x5352504F,
0x59575655,
0x5D5C5B5A,
0x61605F5E,
0x64646362,
0x66666565,
0x68686767,
0x68686868,
0x68686868,
0x67676868,
0x65656666,
0x62636464,
0x5E5F6061,
0x5A5B5C5D,
0x55565759,
0x4F505253,
0x484A4B4D,
0x40424446,
0x373A3C3E,
0x2E303335,
0x2426292B,
0x191B1E21,
0x0D101316,
0x0003060A,
};
//========================================
// Wide scaler coefficients
//========================================================
// <using> gen_scaler_coeffs.m
@ -285,7 +333,7 @@ static const uint16_t filter_isharp_wide_6tap_64p[198] = {
// <CoefType> Blur & Scale LPF
// <CoefQuant> S1.10
//========================================================
static const uint16_t filter_isharp_bs_4tap_64p[198] = {
static const uint16_t filter_isharp_bs_4tap_in_6_64p[198] = {
0x0000, 0x00E5, 0x0237, 0x00E4, 0x0000, 0x0000,
0x0000, 0x00DE, 0x0237, 0x00EB, 0x0000, 0x0000,
0x0000, 0x00D7, 0x0236, 0x00F2, 0x0001, 0x0000,
@ -320,6 +368,228 @@ static const uint16_t filter_isharp_bs_4tap_64p[198] = {
0x0000, 0x003B, 0x01CF, 0x01C2, 0x0034, 0x0000,
0x0000, 0x0037, 0x01C9, 0x01C9, 0x0037, 0x0000
};
//========================================================
// <using> gen_BlurScale_coeffs.m
// <date> 25-Apr-2022
// <num_taps> 4
// <num_phases> 64
// <CoefType> Blur & Scale LPF
// <CoefQuant> S1.10
//========================================================
static const uint16_t filter_isharp_bs_4tap_64p[132] = {
0x00E5, 0x0237, 0x00E4, 0x0000,
0x00DE, 0x0237, 0x00EB, 0x0000,
0x00D7, 0x0236, 0x00F2, 0x0001,
0x00D0, 0x0235, 0x00FA, 0x0001,
0x00C9, 0x0234, 0x0101, 0x0002,
0x00C2, 0x0233, 0x0108, 0x0003,
0x00BB, 0x0232, 0x0110, 0x0003,
0x00B5, 0x0230, 0x0117, 0x0004,
0x00AE, 0x022E, 0x011F, 0x0005,
0x00A8, 0x022C, 0x0126, 0x0006,
0x00A2, 0x022A, 0x012D, 0x0007,
0x009C, 0x0228, 0x0134, 0x0008,
0x0096, 0x0225, 0x013C, 0x0009,
0x0090, 0x0222, 0x0143, 0x000B,
0x008A, 0x021F, 0x014B, 0x000C,
0x0085, 0x021C, 0x0151, 0x000E,
0x007F, 0x0218, 0x015A, 0x000F,
0x007A, 0x0215, 0x0160, 0x0011,
0x0074, 0x0211, 0x0168, 0x0013,
0x006F, 0x020D, 0x016F, 0x0015,
0x006A, 0x0209, 0x0176, 0x0017,
0x0065, 0x0204, 0x017E, 0x0019,
0x0060, 0x0200, 0x0185, 0x001B,
0x005C, 0x01FB, 0x018C, 0x001D,
0x0057, 0x01F6, 0x0193, 0x0020,
0x0053, 0x01F1, 0x019A, 0x0022,
0x004E, 0x01EC, 0x01A1, 0x0025,
0x004A, 0x01E6, 0x01A8, 0x0028,
0x0046, 0x01E1, 0x01AF, 0x002A,
0x0042, 0x01DB, 0x01B6, 0x002D,
0x003F, 0x01D5, 0x01BB, 0x0031,
0x003B, 0x01CF, 0x01C2, 0x0034,
0x0037, 0x01C9, 0x01C9, 0x0037,
};
//========================================================
// <using> gen_BlurScale_coeffs.m
// <date> 09-Jun-2022
// <num_taps> 3
// <num_phases> 64
// <CoefType> Blur & Scale LPF
// <CoefQuant> S1.10
//========================================================
static const uint16_t filter_isharp_bs_3tap_64p[99] = {
0x0200, 0x0200, 0x0000,
0x01F6, 0x0206, 0x0004,
0x01EC, 0x020B, 0x0009,
0x01E2, 0x0211, 0x000D,
0x01D8, 0x0216, 0x0012,
0x01CE, 0x021C, 0x0016,
0x01C4, 0x0221, 0x001B,
0x01BA, 0x0226, 0x0020,
0x01B0, 0x022A, 0x0026,
0x01A6, 0x022F, 0x002B,
0x019C, 0x0233, 0x0031,
0x0192, 0x0238, 0x0036,
0x0188, 0x023C, 0x003C,
0x017E, 0x0240, 0x0042,
0x0174, 0x0244, 0x0048,
0x016A, 0x0248, 0x004E,
0x0161, 0x024A, 0x0055,
0x0157, 0x024E, 0x005B,
0x014D, 0x0251, 0x0062,
0x0144, 0x0253, 0x0069,
0x013A, 0x0256, 0x0070,
0x0131, 0x0258, 0x0077,
0x0127, 0x025B, 0x007E,
0x011E, 0x025C, 0x0086,
0x0115, 0x025E, 0x008D,
0x010B, 0x0260, 0x0095,
0x0102, 0x0262, 0x009C,
0x00F9, 0x0263, 0x00A4,
0x00F0, 0x0264, 0x00AC,
0x00E7, 0x0265, 0x00B4,
0x00DF, 0x0264, 0x00BD,
0x00D6, 0x0265, 0x00C5,
0x00CD, 0x0266, 0x00CD,
};
/* Converted Blur & Scale coeff tables from S1.10 to S1.12 */
static uint16_t filter_isharp_bs_4tap_in_6_64p_s1_12[198];
static uint16_t filter_isharp_bs_4tap_64p_s1_12[132];
static uint16_t filter_isharp_bs_3tap_64p_s1_12[99];
struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_sdr_nl[3][6] = {
{ /* LOW */
{1125, 1000, 75, 100},
{11, 10, 6, 10},
{1075, 1000, 45, 100},
{105, 100, 3, 10},
{1025, 1000, 15, 100},
{1, 1, 0, 1},
},
{ /* MID */
{1125, 1000, 2, 1},
{11, 10, 175, 100},
{1075, 1000, 15, 10},
{105, 100, 125, 100},
{1025, 1000, 1, 1},
{1, 1, 75, 100},
},
{ /* HIGH */
{1125, 1000, 35, 10},
{11, 10, 32, 10},
{1075, 1000, 29, 10},
{105, 100, 26, 10},
{1025, 1000, 23, 10},
{1, 1, 2, 1},
},
};
struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_sdr_l[3][6] = {
{ /* LOW */
{1125, 1000, 75, 100},
{11, 10, 6, 10},
{1075, 1000, 45, 100},
{105, 100, 3, 10},
{1025, 1000, 15, 100},
{1, 1, 0, 1},
},
{ /* MID */
{1125, 1000, 15, 10},
{11, 10, 135, 100},
{1075, 1000, 12, 10},
{105, 100, 105, 100},
{1025, 1000, 9, 10},
{1, 1, 75, 100},
},
{ /* HIGH */
{1125, 1000, 25, 10},
{11, 10, 23, 10},
{1075, 1000, 21, 10},
{105, 100, 19, 10},
{1025, 1000, 17, 10},
{1, 1, 15, 10},
},
};
struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_hdr_nl[3][6] = {
{ /* LOW */
{1125, 1000, 5, 10},
{11, 10, 4, 10},
{1075, 1000, 3, 10},
{105, 100, 2, 10},
{1025, 1000, 1, 10},
{1, 1, 0, 1},
},
{ /* MID */
{1125, 1000, 1, 1},
{11, 10, 9, 10},
{1075, 1000, 8, 10},
{105, 100, 7, 10},
{1025, 1000, 6, 10},
{1, 1, 5, 10},
},
{ /* HIGH */
{1125, 1000, 15, 10},
{11, 10, 14, 10},
{1075, 1000, 13, 10},
{105, 100, 12, 10},
{1025, 1000, 11, 10},
{1, 1, 1, 1},
},
};
struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_hdr_l[3][6] = {
{ /* LOW */
{1125, 1000, 75, 100},
{11, 10, 6, 10},
{1075, 1000, 45, 100},
{105, 100, 3, 10},
{1025, 1000, 15, 100},
{1, 1, 0, 1},
},
{ /* MID */
{1125, 1000, 15, 10},
{11, 10, 135, 100},
{1075, 1000, 12, 10},
{105, 100, 105, 100},
{1025, 1000, 9, 10},
{1, 1, 75, 100},
},
{ /* HIGH */
{1125, 1000, 25, 10},
{11, 10, 23, 10},
{1075, 1000, 21, 10},
{105, 100, 19, 10},
{1025, 1000, 17, 10},
{1, 1, 15, 10},
},
};
/* Pre-generated 1DLUT for LOW for given setup and sharpness level */
uint32_t filter_isharp_1D_lut_pregen[3][32] = {
{
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
{
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
},
};
const uint32_t *spl_get_filter_isharp_1D_lut_0(void)
{
return filter_isharp_1D_lut_0;
@ -340,11 +610,162 @@ const uint32_t *spl_get_filter_isharp_1D_lut_2p0x(void)
{
return filter_isharp_1D_lut_2p0x;
}
const uint32_t *spl_get_filter_isharp_1D_lut_3p0x(void)
{
return filter_isharp_1D_lut_3p0x;
}
const uint16_t *spl_get_filter_isharp_wide_6tap_64p(void)
{
return filter_isharp_wide_6tap_64p;
}
const uint16_t *spl_get_filter_isharp_bs_4tap_64p(void)
uint16_t *spl_get_filter_isharp_bs_4tap_in_6_64p(void)
{
return filter_isharp_bs_4tap_64p;
return filter_isharp_bs_4tap_in_6_64p_s1_12;
}
uint16_t *spl_get_filter_isharp_bs_4tap_64p(void)
{
return filter_isharp_bs_4tap_64p_s1_12;
}
uint16_t *spl_get_filter_isharp_bs_3tap_64p(void)
{
return filter_isharp_bs_3tap_64p_s1_12;
}
void spl_build_isharp_1dlut_from_reference_curve(struct fixed31_32 ratio, enum system_setup setup)
{
uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst;
struct fixed31_32 sharp_base, sharp_calc, sharp_level, ratio_level;
int i, j;
struct scale_ratio_to_sharpness_level_lookup *setup_lookup_ptr;
int num_sharp_ramp_levels;
int size_1dlut;
int sharp_calc_int;
uint32_t filter_pregen_store[32];
/*
* Given scaling ratio and current system setup, build pregenerated
* 1DLUT tables for three sharpness levels - LOW, MID, HIGH
*/
for (i = 0; i < 3; i++) {
/*
* Based on setup ( HDR/SDR, L/NL ), get base scale ratio to
* sharpness curve
*/
switch (setup) {
case HDR_L:
setup_lookup_ptr = scale_to_sharp_hdr_l[i];
num_sharp_ramp_levels = sizeof(scale_to_sharp_hdr_l[i])/
sizeof(struct scale_ratio_to_sharpness_level_lookup);
break;
case HDR_NL:
setup_lookup_ptr = scale_to_sharp_hdr_nl[i];
num_sharp_ramp_levels = sizeof(scale_to_sharp_hdr_nl[i])/
sizeof(struct scale_ratio_to_sharpness_level_lookup);
break;
case SDR_L:
setup_lookup_ptr = scale_to_sharp_sdr_l[i];
num_sharp_ramp_levels = sizeof(scale_to_sharp_sdr_l[i])/
sizeof(struct scale_ratio_to_sharpness_level_lookup);
break;
case SDR_NL:
default:
setup_lookup_ptr = scale_to_sharp_sdr_nl[i];
num_sharp_ramp_levels = sizeof(scale_to_sharp_sdr_nl[i])/
sizeof(struct scale_ratio_to_sharpness_level_lookup);
break;
}
/*
* Compare desired scaling ratio and find adjusted sharpness from
* base scale ratio to sharpness curve
*/
j = 0;
sharp_level = dc_fixpt_zero;
while (j < num_sharp_ramp_levels) {
ratio_level = dc_fixpt_from_fraction(setup_lookup_ptr->ratio_numer,
setup_lookup_ptr->ratio_denom);
if (ratio.value >= ratio_level.value) {
sharp_level = dc_fixpt_from_fraction(setup_lookup_ptr->sharpness_numer,
setup_lookup_ptr->sharpness_denom);
break;
}
setup_lookup_ptr++;
j++;
}
/*
* Calculate LUT_128_gained with this equation:
*
* LUT_128_gained[i] = (uint8)(0.5 + min(255,(double)(LUT_128[i])*sharpLevel/iGain))
* where LUT_128[i] is contents of 3p0x isharp 1dlut
* where sharpLevel is desired sharpness level
* where iGain is base sharpness level 3.0
* where LUT_128_gained[i] is adjusted 1dlut value based on desired sharpness level
*/
byte_ptr_1dlut_src = (uint8_t *)filter_isharp_1D_lut_3p0x;
byte_ptr_1dlut_dst = (uint8_t *)filter_pregen_store;
size_1dlut = sizeof(filter_isharp_1D_lut_3p0x);
memset(byte_ptr_1dlut_dst, 0, size_1dlut);
for (j = 0; j < size_1dlut; j++) {
sharp_base = dc_fixpt_from_int((int)*byte_ptr_1dlut_src);
sharp_calc = dc_fixpt_mul(sharp_base, sharp_level);
sharp_calc = dc_fixpt_div(sharp_calc, dc_fixpt_from_int(3));
sharp_calc = dc_fixpt_min(dc_fixpt_from_int(255), sharp_calc);
sharp_calc = dc_fixpt_add(sharp_calc, dc_fixpt_from_fraction(1, 2));
sharp_calc_int = dc_fixpt_floor(sharp_calc);
if (sharp_calc_int > 255)
sharp_calc_int = 255;
*byte_ptr_1dlut_dst = (uint8_t)sharp_calc_int;
byte_ptr_1dlut_src++;
byte_ptr_1dlut_dst++;
}
/* Compare if filter has change, if so update */
if (memcmp((void *)filter_isharp_1D_lut_pregen[i], (void *)filter_pregen_store, size_1dlut) != 0)
memcpy((void *)filter_isharp_1D_lut_pregen[i], (void *)filter_pregen_store, size_1dlut);
}
}
uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum explicit_sharpness sharpness)
{
return filter_isharp_1D_lut_pregen[sharpness];
}
void spl_init_blur_scale_coeffs(void)
{
convert_filter_s1_10_to_s1_12(filter_isharp_bs_3tap_64p,
filter_isharp_bs_3tap_64p_s1_12, 3);
convert_filter_s1_10_to_s1_12(filter_isharp_bs_4tap_64p,
filter_isharp_bs_4tap_64p_s1_12, 4);
convert_filter_s1_10_to_s1_12(filter_isharp_bs_4tap_in_6_64p,
filter_isharp_bs_4tap_in_6_64p_s1_12, 6);
}
#ifdef CONFIG_DRM_AMD_DC_FP
uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps)
{
if (taps == 3)
return spl_get_filter_isharp_bs_3tap_64p();
else if (taps == 4)
return spl_get_filter_isharp_bs_4tap_64p();
else if (taps == 6)
return spl_get_filter_isharp_bs_4tap_in_6_64p();
else {
/* should never happen, bug */
BREAK_TO_DEBUGGER();
return NULL;
}
}
void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,
const struct spl_scaler_data *data)
{
dscl_prog_data->filter_blur_scale_h =
spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps);
dscl_prog_data->filter_blur_scale_v =
spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps);
}
#endif

33
drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h
View File

@ -12,6 +12,37 @@ const uint32_t *spl_get_filter_isharp_1D_lut_0p5x(void);
const uint32_t *spl_get_filter_isharp_1D_lut_1p0x(void);
const uint32_t *spl_get_filter_isharp_1D_lut_1p5x(void);
const uint32_t *spl_get_filter_isharp_1D_lut_2p0x(void);
const uint16_t *spl_get_filter_isharp_bs_4tap_64p(void);
const uint32_t *spl_get_filter_isharp_1D_lut_3p0x(void);
uint16_t *spl_get_filter_isharp_bs_4tap_in_6_64p(void);
uint16_t *spl_get_filter_isharp_bs_4tap_64p(void);
uint16_t *spl_get_filter_isharp_bs_3tap_64p(void);
const uint16_t *spl_get_filter_isharp_wide_6tap_64p(void);
uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps);
struct scale_ratio_to_sharpness_level_lookup {
unsigned int ratio_numer;
unsigned int ratio_denom;
unsigned int sharpness_numer;
unsigned int sharpness_denom;
};
struct sharpness_level_mapping {
unsigned int level;
unsigned int level_numer;
unsigned int level_denom;
};
enum system_setup {
SDR_NL = 0,
SDR_L,
HDR_NL,
HDR_L
};
void spl_init_blur_scale_coeffs(void);
void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,
const struct spl_scaler_data *data);
void spl_build_isharp_1dlut_from_reference_curve(struct fixed31_32 ratio, enum system_setup setup);
uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum explicit_sharpness sharpness);
#endif /* __DC_SPL_ISHARP_FILTERS_H__ */

1725
drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.c Normal file
View File

File diff suppressed because it is too large Load Diff

38
drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.h Normal file
View File

@ -0,0 +1,38 @@
/* SPDX-License-Identifier: MIT */
/* Copyright 2024 Advanced Micro Devices, Inc. */
#ifndef __DC_SPL_SCL_EASF_FILTERS_H__
#define __DC_SPL_SCL_EASF_FILTERS_H__
#include "dc_spl_types.h"
struct scale_ratio_to_reg_value_lookup {
int numer;
int denom;
const uint32_t reg_value;
};
void spl_init_easf_filter_coeffs(void);
uint16_t *spl_get_easf_filter_3tap_64p(struct fixed31_32 ratio);
uint16_t *spl_get_easf_filter_4tap_64p(struct fixed31_32 ratio);
uint16_t *spl_get_easf_filter_6tap_64p(struct fixed31_32 ratio);
uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct fixed31_32 ratio);
void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,
const struct spl_scaler_data *data, bool enable_easf_v,
bool enable_easf_h);
uint32_t spl_get_v_bf3_mode(struct fixed31_32 ratio);
uint32_t spl_get_h_bf3_mode(struct fixed31_32 ratio);
uint32_t spl_get_reducer_gain6(int taps, struct fixed31_32 ratio);
uint32_t spl_get_reducer_gain4(int taps, struct fixed31_32 ratio);
uint32_t spl_get_gainRing6(int taps, struct fixed31_32 ratio);
uint32_t spl_get_gainRing4(int taps, struct fixed31_32 ratio);
uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct fixed31_32 ratio);
uint32_t spl_get_3tap_uptilt_maxval(int taps, struct fixed31_32 ratio);
uint32_t spl_get_3tap_dntilt_slope(int taps, struct fixed31_32 ratio);
uint32_t spl_get_3tap_uptilt1_slope(int taps, struct fixed31_32 ratio);
uint32_t spl_get_3tap_uptilt2_slope(int taps, struct fixed31_32 ratio);
uint32_t spl_get_3tap_uptilt2_offset(int taps, struct fixed31_32 ratio);
#endif /* __DC_SPL_SCL_EASF_FILTERS_H__ */

26
drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.c
View File

@ -1423,3 +1423,29 @@ const uint16_t *spl_get_filter_2tap_64p(void)
{
return filter_2tap_64p;
}
const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
{
if (taps == 8)
return spl_get_filter_8tap_64p(ratio);
else if (taps == 7)
return spl_get_filter_7tap_64p(ratio);
else if (taps == 6)
return spl_get_filter_6tap_64p(ratio);
else if (taps == 5)
return spl_get_filter_5tap_64p(ratio);
else if (taps == 4)
return spl_get_filter_4tap_64p(ratio);
else if (taps == 3)
return spl_get_filter_3tap_64p(ratio);
else if (taps == 2)
return spl_get_filter_2tap_64p();
else if (taps == 1)
return NULL;
else {
/* should never happen, bug */
BREAK_TO_DEBUGGER();
return NULL;
}
}

39
drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.h
View File

@ -17,43 +17,6 @@ const uint16_t *spl_get_filter_7tap_64p(struct fixed31_32 ratio);
const uint16_t *spl_get_filter_8tap_64p(struct fixed31_32 ratio);
const uint16_t *spl_get_filter_2tap_16p(void);
const uint16_t *spl_get_filter_2tap_64p(void);
const uint16_t *spl_get_filter_3tap_16p_upscale(void);
const uint16_t *spl_get_filter_3tap_16p_116(void);
const uint16_t *spl_get_filter_3tap_16p_149(void);
const uint16_t *spl_get_filter_3tap_16p_183(void);
const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio);
const uint16_t *spl_get_filter_4tap_16p_upscale(void);
const uint16_t *spl_get_filter_4tap_16p_116(void);
const uint16_t *spl_get_filter_4tap_16p_149(void);
const uint16_t *spl_get_filter_4tap_16p_183(void);
const uint16_t *spl_get_filter_3tap_64p_upscale(void);
const uint16_t *spl_get_filter_3tap_64p_116(void);
const uint16_t *spl_get_filter_3tap_64p_149(void);
const uint16_t *spl_get_filter_3tap_64p_183(void);
const uint16_t *spl_get_filter_4tap_64p_upscale(void);
const uint16_t *spl_get_filter_4tap_64p_116(void);
const uint16_t *spl_get_filter_4tap_64p_149(void);
const uint16_t *spl_get_filter_4tap_64p_183(void);
const uint16_t *spl_get_filter_5tap_64p_upscale(void);
const uint16_t *spl_get_filter_5tap_64p_116(void);
const uint16_t *spl_get_filter_5tap_64p_149(void);
const uint16_t *spl_get_filter_5tap_64p_183(void);
const uint16_t *spl_get_filter_6tap_64p_upscale(void);
const uint16_t *spl_get_filter_6tap_64p_116(void);
const uint16_t *spl_get_filter_6tap_64p_149(void);
const uint16_t *spl_get_filter_6tap_64p_183(void);
const uint16_t *spl_get_filter_7tap_64p_upscale(void);
const uint16_t *spl_get_filter_7tap_64p_116(void);
const uint16_t *spl_get_filter_7tap_64p_149(void);
const uint16_t *spl_get_filter_7tap_64p_183(void);
const uint16_t *spl_get_filter_8tap_64p_upscale(void);
const uint16_t *spl_get_filter_8tap_64p_116(void);
const uint16_t *spl_get_filter_8tap_64p_149(void);
const uint16_t *spl_get_filter_8tap_64p_183(void);
#endif /* __DC_SPL_SCL_FILTERS_H__ */

12
drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
View File

@ -81,6 +81,8 @@ enum spl_pixel_format {
SPL_PIXEL_FORMAT_420BPP10,
/*end of pixel format definition*/
SPL_PIXEL_FORMAT_INVALID,
SPL_PIXEL_FORMAT_422BPP8,
SPL_PIXEL_FORMAT_422BPP10,
SPL_PIXEL_FORMAT_GRPH_BEGIN = SPL_PIXEL_FORMAT_INDEX8,
SPL_PIXEL_FORMAT_GRPH_END = SPL_PIXEL_FORMAT_FP16,
SPL_PIXEL_FORMAT_VIDEO_BEGIN = SPL_PIXEL_FORMAT_420BPP8,
@ -120,6 +122,13 @@ enum spl_color_space {
SPL_COLOR_SPACE_YCBCR709_BLACK,
};
enum chroma_cositing {
CHROMA_COSITING_NONE,
CHROMA_COSITING_LEFT,
CHROMA_COSITING_TOPLEFT,
CHROMA_COSITING_COUNT
};
// Scratch space for calculating scaler params
struct spl_scaler_data {
int h_active;
@ -129,6 +138,7 @@ struct spl_scaler_data {
struct spl_rect viewport_c;
struct spl_rect recout;
struct spl_ratios ratios;
struct spl_ratios recip_ratios;
struct spl_inits inits;
};
@ -485,6 +495,8 @@ struct spl_in {
bool prefer_easf;
bool disable_easf;
struct spl_debug debug;
bool is_fullscreen;
bool is_hdr_on;
};
// end of SPL inputs