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drm/xe/gsc: Add debugfs to print GSC info
This is useful for debug, in case something goes wrong with the GSC. The info includes the version information and the current value of the HECI1 status registers. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240828215158.2743994-5-daniele.ceraolospurio@intel.com
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@ -40,6 +40,7 @@ xe-y += xe_bb.o \
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xe_ggtt.o \
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xe_gpu_scheduler.o \
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xe_gsc.o \
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xe_gsc_debugfs.o \
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xe_gsc_proxy.o \
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xe_gsc_submit.o \
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xe_gt.o \
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@ -32,8 +32,12 @@
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#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
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#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
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#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
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#define HECI_FWSTS2(base) XE_REG((base) + 0xc48)
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#define HECI_FWSTS3(base) XE_REG((base) + 0xc60)
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#define HECI_FWSTS4(base) XE_REG((base) + 0xc64)
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#define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
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#define HECI1_FWSTS5_HUC_AUTH_DONE REG_BIT(19)
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#define HECI_FWSTS6(base) XE_REG((base) + 0xc6c)
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#define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
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#define HECI_H_GS1_ER_PREP REG_BIT(0)
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@ -8,6 +8,7 @@
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#include <linux/delay.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include <generated/xe_wa_oob.h>
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@ -587,3 +588,35 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
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msleep(200);
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}
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}
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/**
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* xe_gsc_print_info - print info about GSC FW status
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* @gsc: the GSC structure
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* @p: the printer to be used to print the info
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*/
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void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
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{
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struct xe_gt *gt = gsc_to_gt(gsc);
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int err;
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xe_uc_fw_print(&gsc->fw, p);
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drm_printf(p, "\tfound security version %u\n", gsc->security_version);
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if (!xe_uc_fw_is_enabled(&gsc->fw))
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return;
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err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC);
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if (err)
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return;
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drm_printf(p, "\nHECI1 FWSTS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
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xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
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xe_mmio_read32(gt, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
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xe_mmio_read32(gt, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
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xe_mmio_read32(gt, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
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xe_mmio_read32(gt, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
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xe_mmio_read32(gt, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
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xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);
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}
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@ -8,6 +8,7 @@
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#include <linux/types.h>
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struct drm_printer;
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struct xe_gsc;
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struct xe_gt;
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struct xe_hw_engine;
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@ -21,4 +22,6 @@ void xe_gsc_hwe_irq_handler(struct xe_hw_engine *hwe, u16 intr_vec);
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void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep);
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void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p);
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#endif
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71
drivers/gpu/drm/xe/xe_gsc_debugfs.c
Normal file
71
drivers/gpu/drm/xe/xe_gsc_debugfs.c
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@ -0,0 +1,71 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_gsc_debugfs.h"
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#include <drm/drm_debugfs.h>
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#include <drm/drm_managed.h>
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#include "xe_device.h"
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#include "xe_gt.h"
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#include "xe_gsc.h"
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#include "xe_macros.h"
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#include "xe_pm.h"
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static struct xe_gt *
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gsc_to_gt(struct xe_gsc *gsc)
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{
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return container_of(gsc, struct xe_gt, uc.gsc);
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}
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static struct xe_device *
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gsc_to_xe(struct xe_gsc *gsc)
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{
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return gt_to_xe(gsc_to_gt(gsc));
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}
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static struct xe_gsc *node_to_gsc(struct drm_info_node *node)
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{
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return node->info_ent->data;
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}
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static int gsc_info(struct seq_file *m, void *data)
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{
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struct xe_gsc *gsc = node_to_gsc(m->private);
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struct xe_device *xe = gsc_to_xe(gsc);
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struct drm_printer p = drm_seq_file_printer(m);
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xe_pm_runtime_get(xe);
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xe_gsc_print_info(gsc, &p);
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xe_pm_runtime_put(xe);
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return 0;
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}
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static const struct drm_info_list debugfs_list[] = {
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{"gsc_info", gsc_info, 0},
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};
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void xe_gsc_debugfs_register(struct xe_gsc *gsc, struct dentry *parent)
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{
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struct drm_minor *minor = gsc_to_xe(gsc)->drm.primary;
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struct drm_info_list *local;
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int i;
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#define DEBUGFS_SIZE (ARRAY_SIZE(debugfs_list) * sizeof(struct drm_info_list))
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local = drmm_kmalloc(&gsc_to_xe(gsc)->drm, DEBUGFS_SIZE, GFP_KERNEL);
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if (!local)
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return;
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memcpy(local, debugfs_list, DEBUGFS_SIZE);
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#undef DEBUGFS_SIZE
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for (i = 0; i < ARRAY_SIZE(debugfs_list); ++i)
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local[i].data = gsc;
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drm_debugfs_create_files(local,
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ARRAY_SIZE(debugfs_list),
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parent, minor);
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}
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14
drivers/gpu/drm/xe/xe_gsc_debugfs.h
Normal file
14
drivers/gpu/drm/xe/xe_gsc_debugfs.h
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@ -0,0 +1,14 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_GSC_DEBUGFS_H_
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#define _XE_GSC_DEBUGFS_H_
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struct dentry;
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struct xe_gsc;
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void xe_gsc_debugfs_register(struct xe_gsc *gsc, struct dentry *parent);
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#endif
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@ -8,6 +8,7 @@
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#include <drm/drm_debugfs.h>
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#include "xe_gt.h"
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#include "xe_gsc_debugfs.h"
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#include "xe_guc_debugfs.h"
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#include "xe_huc_debugfs.h"
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#include "xe_macros.h"
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@ -23,6 +24,7 @@ void xe_uc_debugfs_register(struct xe_uc *uc, struct dentry *parent)
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return;
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}
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xe_gsc_debugfs_register(&uc->gsc, root);
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xe_guc_debugfs_register(&uc->guc, root);
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xe_huc_debugfs_register(&uc->huc, root);
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}
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