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iio: adc: at91-sama5d2_adc: add hw trigger and buffer support
Added support for the external hardware trigger on pin ADTRG, integrated the three possible edges into the driver and created buffer management for data retrieval Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Eugen Hristev
Jonathan Cameron
parent
6ab6b4ec00
commit
5e1a1da0f8
@ -25,6 +25,10 @@
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#include <linux/wait.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/regulator/consumer.h>
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/* Control Register */
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@ -132,6 +136,17 @@
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#define AT91_SAMA5D2_PRESSR 0xbc
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/* Trigger Register */
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#define AT91_SAMA5D2_TRGR 0xc0
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/* Mask for TRGMOD field of TRGR register */
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#define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
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/* No trigger, only software trigger can start conversions */
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#define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
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/* Trigger Mode external trigger rising edge */
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#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
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/* Trigger Mode external trigger falling edge */
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#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
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/* Trigger Mode external trigger any edge */
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#define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
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/* Correction Select Register */
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#define AT91_SAMA5D2_COSR 0xd0
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/* Correction Value Register */
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@ -145,14 +160,29 @@
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/* Version Register */
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#define AT91_SAMA5D2_VERSION 0xfc
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#define AT91_SAMA5D2_HW_TRIG_CNT 3
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#define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
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#define AT91_SAMA5D2_DIFF_CHAN_CNT 6
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/*
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* Maximum number of bytes to hold conversion from all channels
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* plus the timestamp
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*/
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#define AT91_BUFFER_MAX_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
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AT91_SAMA5D2_DIFF_CHAN_CNT) * 2 + 8)
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#define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
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#define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
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{ \
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.type = IIO_VOLTAGE, \
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.channel = num, \
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.address = addr, \
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.scan_index = num, \
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.scan_type = { \
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.sign = 'u', \
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.realbits = 12, \
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.storagebits = 16, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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@ -168,9 +198,11 @@
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.channel = num, \
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.channel2 = num2, \
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.address = addr, \
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.scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 12, \
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.storagebits = 16, \
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}, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
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@ -188,6 +220,12 @@ struct at91_adc_soc_info {
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unsigned max_sample_rate;
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};
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struct at91_adc_trigger {
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char *name;
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unsigned int trgmod_value;
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unsigned int edge_type;
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};
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struct at91_adc_state {
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void __iomem *base;
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int irq;
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@ -195,11 +233,14 @@ struct at91_adc_state {
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struct regulator *reg;
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struct regulator *vref;
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int vref_uv;
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struct iio_trigger *trig;
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const struct at91_adc_trigger *selected_trig;
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const struct iio_chan_spec *chan;
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bool conversion_done;
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u32 conversion_value;
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struct at91_adc_soc_info soc_info;
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wait_queue_head_t wq_data_available;
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u16 buffer[AT91_BUFFER_MAX_HWORDS];
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/*
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* lock to prevent concurrent 'single conversion' requests through
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* sysfs.
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@ -207,6 +248,24 @@ struct at91_adc_state {
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struct mutex lock;
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};
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static const struct at91_adc_trigger at91_adc_trigger_list[] = {
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{
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.name = "external_rising",
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.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
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.edge_type = IRQ_TYPE_EDGE_RISING,
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},
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{
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.name = "external_falling",
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.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
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.edge_type = IRQ_TYPE_EDGE_FALLING,
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},
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{
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.name = "external_any",
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.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
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.edge_type = IRQ_TYPE_EDGE_BOTH,
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},
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};
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static const struct iio_chan_spec at91_adc_channels[] = {
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AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
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AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
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@ -226,8 +285,128 @@ static const struct iio_chan_spec at91_adc_channels[] = {
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AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
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AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
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AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
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IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_SINGLE_CHAN_CNT
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+ AT91_SAMA5D2_DIFF_CHAN_CNT + 1),
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};
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static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
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{
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struct iio_dev *indio = iio_trigger_get_drvdata(trig);
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struct at91_adc_state *st = iio_priv(indio);
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u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
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u8 bit;
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/* clear TRGMOD */
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status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
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if (state)
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status |= st->selected_trig->trgmod_value;
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/* set/unset hw trigger */
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at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
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for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
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struct iio_chan_spec const *chan = indio->channels + bit;
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if (state) {
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at91_adc_writel(st, AT91_SAMA5D2_CHER,
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BIT(chan->channel));
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at91_adc_writel(st, AT91_SAMA5D2_IER,
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BIT(chan->channel));
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} else {
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at91_adc_writel(st, AT91_SAMA5D2_IDR,
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BIT(chan->channel));
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at91_adc_writel(st, AT91_SAMA5D2_CHDR,
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BIT(chan->channel));
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}
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}
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return 0;
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}
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static int at91_adc_reenable_trigger(struct iio_trigger *trig)
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{
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struct iio_dev *indio = iio_trigger_get_drvdata(trig);
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struct at91_adc_state *st = iio_priv(indio);
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enable_irq(st->irq);
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/* Needed to ACK the DRDY interruption */
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at91_adc_readl(st, AT91_SAMA5D2_LCDR);
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return 0;
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}
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static const struct iio_trigger_ops at91_adc_trigger_ops = {
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.owner = THIS_MODULE,
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.set_trigger_state = &at91_adc_configure_trigger,
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.try_reenable = &at91_adc_reenable_trigger,
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};
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static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
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char *trigger_name)
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{
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struct iio_trigger *trig;
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int ret;
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trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
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indio->id, trigger_name);
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if (!trig)
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return NULL;
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trig->dev.parent = indio->dev.parent;
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iio_trigger_set_drvdata(trig, indio);
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trig->ops = &at91_adc_trigger_ops;
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ret = devm_iio_trigger_register(&indio->dev, trig);
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if (ret)
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return ERR_PTR(ret);
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return trig;
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}
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static int at91_adc_trigger_init(struct iio_dev *indio)
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{
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struct at91_adc_state *st = iio_priv(indio);
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st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
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if (IS_ERR(st->trig)) {
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dev_err(&indio->dev,
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"could not allocate trigger\n");
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return PTR_ERR(st->trig);
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}
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return 0;
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}
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static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
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{
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struct iio_poll_func *pf = p;
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struct iio_dev *indio = pf->indio_dev;
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struct at91_adc_state *st = iio_priv(indio);
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int i = 0;
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u8 bit;
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for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
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struct iio_chan_spec const *chan = indio->channels + bit;
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st->buffer[i] = at91_adc_readl(st, chan->address);
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i++;
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}
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iio_push_to_buffers_with_timestamp(indio, st->buffer, pf->timestamp);
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iio_trigger_notify_done(indio->trig);
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return IRQ_HANDLED;
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}
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static int at91_adc_buffer_init(struct iio_dev *indio)
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{
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return devm_iio_triggered_buffer_setup(&indio->dev, indio,
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&iio_pollfunc_store_time,
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&at91_adc_trigger_handler, NULL);
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}
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static unsigned at91_adc_startup_time(unsigned startup_time_min,
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unsigned adc_clk_khz)
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{
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@ -293,14 +472,18 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private)
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u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
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u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
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if (status & imr) {
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if (!(status & imr))
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return IRQ_NONE;
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if (iio_buffer_enabled(indio)) {
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disable_irq_nosync(irq);
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iio_trigger_poll(indio->trig);
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} else {
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st->conversion_value = at91_adc_readl(st, st->chan->address);
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st->conversion_done = true;
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wake_up_interruptible(&st->wq_data_available);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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return IRQ_HANDLED;
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}
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static int at91_adc_read_raw(struct iio_dev *indio_dev,
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@ -313,6 +496,11 @@ static int at91_adc_read_raw(struct iio_dev *indio_dev,
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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/* we cannot use software trigger if hw trigger enabled */
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ret = iio_device_claim_direct_mode(indio_dev);
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if (ret)
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return ret;
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mutex_lock(&st->lock);
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st->chan = chan;
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@ -344,6 +532,8 @@ static int at91_adc_read_raw(struct iio_dev *indio_dev,
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at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
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mutex_unlock(&st->lock);
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iio_device_release_direct_mode(indio_dev);
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return ret;
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case IIO_CHAN_INFO_SCALE:
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@ -391,7 +581,8 @@ static int at91_adc_probe(struct platform_device *pdev)
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struct iio_dev *indio_dev;
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struct at91_adc_state *st;
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struct resource *res;
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int ret;
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int ret, i;
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u32 edge_type;
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indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
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if (!indio_dev)
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@ -432,6 +623,27 @@ static int at91_adc_probe(struct platform_device *pdev)
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return ret;
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}
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ret = of_property_read_u32(pdev->dev.of_node,
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"atmel,trigger-edge-type", &edge_type);
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if (ret) {
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dev_err(&pdev->dev,
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"invalid or missing value for atmel,trigger-edge-type\n");
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return ret;
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}
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st->selected_trig = NULL;
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for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT; i++)
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if (at91_adc_trigger_list[i].edge_type == edge_type) {
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st->selected_trig = &at91_adc_trigger_list[i];
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break;
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}
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if (!st->selected_trig) {
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dev_err(&pdev->dev, "invalid external trigger edge value\n");
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return -EINVAL;
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}
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init_waitqueue_head(&st->wq_data_available);
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mutex_init(&st->lock);
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@ -499,10 +711,25 @@ static int at91_adc_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, indio_dev);
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ret = at91_adc_buffer_init(indio_dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
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goto per_clk_disable_unprepare;
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}
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ret = at91_adc_trigger_init(indio_dev);
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if (ret < 0) {
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dev_err(&pdev->dev, "couldn't setup the triggers.\n");
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goto per_clk_disable_unprepare;
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}
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ret = iio_device_register(indio_dev);
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if (ret < 0)
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goto per_clk_disable_unprepare;
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dev_info(&pdev->dev, "setting up trigger as %s\n",
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st->selected_trig->name);
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dev_info(&pdev->dev, "version: %x\n",
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readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
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