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dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data
Add PSIL EP data and PDMA data for AM62x. [p.yadav@ti.com: Add CSIRX data] Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Link: https://lore.kernel.org/r/20220219083220.489420-3-vigneshr@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Vignesh Raghavendra
Vinod Koul
parent
03cbdf8b12
commit
5ac6bfb587
@ -9,5 +9,6 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o \
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k3-psil-j721e.o \
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k3-psil-j7200.o \
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k3-psil-am64.o \
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k3-psil-j721s2.o
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k3-psil-j721s2.o \
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k3-psil-am62.o
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obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o
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186
drivers/dma/ti/k3-psil-am62.c
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186
drivers/dma/ti/k3-psil-am62.c
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@ -0,0 +1,186 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
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*/
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#include <linux/kernel.h>
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#include "k3-psil-priv.h"
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#define PSIL_PDMA_XY_PKT(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.mapped_channel_id = -1, \
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.default_flow_id = -1, \
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.pkt_mode = 1, \
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}, \
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}
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#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 16, \
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.mapped_channel_id = ch, \
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.flow_start = flow_base, \
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.flow_num = flow_cnt, \
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.default_flow_id = flow_base, \
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}, \
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}
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#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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.pkt_mode = 1, \
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.needs_epib = 1, \
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.psd_size = 64, \
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.mapped_channel_id = ch, \
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.flow_start = flow_base, \
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.flow_num = flow_cnt, \
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.default_flow_id = default_flow, \
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.notdpkt = tx, \
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}, \
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}
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#define PSIL_PDMA_MCASP(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_PDMA_XY, \
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.pdma_acc32 = 1, \
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.pdma_burst = 1, \
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}, \
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}
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#define PSIL_CSI2RX(x) \
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{ \
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.thread_id = x, \
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.ep_config = { \
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.ep_type = PSIL_EP_NATIVE, \
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}, \
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}
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/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
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static struct psil_ep am62_src_ep_map[] = {
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/* SAUL */
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PSIL_SAUL(0x7500, 20, 35, 8, 35, 0),
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PSIL_SAUL(0x7501, 21, 35, 8, 36, 0),
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PSIL_SAUL(0x7502, 22, 43, 8, 43, 0),
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PSIL_SAUL(0x7503, 23, 43, 8, 44, 0),
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/* PDMA_MAIN0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0x4302),
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PSIL_PDMA_XY_PKT(0x4303),
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PSIL_PDMA_XY_PKT(0x4304),
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PSIL_PDMA_XY_PKT(0x4305),
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PSIL_PDMA_XY_PKT(0x4306),
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PSIL_PDMA_XY_PKT(0x4307),
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PSIL_PDMA_XY_PKT(0x4308),
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PSIL_PDMA_XY_PKT(0x4309),
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PSIL_PDMA_XY_PKT(0x430a),
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PSIL_PDMA_XY_PKT(0x430b),
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PSIL_PDMA_XY_PKT(0x430c),
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PSIL_PDMA_XY_PKT(0x430d),
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/* PDMA_MAIN1 - UART0-6 */
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PSIL_PDMA_XY_PKT(0x4400),
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PSIL_PDMA_XY_PKT(0x4401),
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PSIL_PDMA_XY_PKT(0x4402),
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PSIL_PDMA_XY_PKT(0x4403),
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PSIL_PDMA_XY_PKT(0x4404),
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PSIL_PDMA_XY_PKT(0x4405),
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PSIL_PDMA_XY_PKT(0x4406),
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/* PDMA_MAIN2 - MCASP0-2 */
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PSIL_PDMA_MCASP(0x4500),
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PSIL_PDMA_MCASP(0x4501),
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PSIL_PDMA_MCASP(0x4502),
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/* CPSW3G */
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PSIL_ETHERNET(0x4600, 19, 19, 16),
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/* CSI2RX */
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PSIL_CSI2RX(0x4700),
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PSIL_CSI2RX(0x4701),
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PSIL_CSI2RX(0x4702),
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PSIL_CSI2RX(0x4703),
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PSIL_CSI2RX(0x4704),
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PSIL_CSI2RX(0x4705),
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PSIL_CSI2RX(0x4706),
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PSIL_CSI2RX(0x4707),
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PSIL_CSI2RX(0x4708),
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PSIL_CSI2RX(0x4709),
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PSIL_CSI2RX(0x470a),
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PSIL_CSI2RX(0x470b),
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PSIL_CSI2RX(0x470c),
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PSIL_CSI2RX(0x470d),
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PSIL_CSI2RX(0x470e),
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PSIL_CSI2RX(0x470f),
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PSIL_CSI2RX(0x4710),
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PSIL_CSI2RX(0x4711),
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PSIL_CSI2RX(0x4712),
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PSIL_CSI2RX(0x4713),
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PSIL_CSI2RX(0x4714),
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PSIL_CSI2RX(0x4715),
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PSIL_CSI2RX(0x4716),
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PSIL_CSI2RX(0x4717),
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PSIL_CSI2RX(0x4718),
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PSIL_CSI2RX(0x4719),
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PSIL_CSI2RX(0x471a),
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PSIL_CSI2RX(0x471b),
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PSIL_CSI2RX(0x471c),
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PSIL_CSI2RX(0x471d),
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PSIL_CSI2RX(0x471e),
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PSIL_CSI2RX(0x471f),
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};
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/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
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static struct psil_ep am62_dst_ep_map[] = {
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/* SAUL */
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PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
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PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
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/* PDMA_MAIN0 - SPI0-3 */
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PSIL_PDMA_XY_PKT(0xc302),
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PSIL_PDMA_XY_PKT(0xc303),
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PSIL_PDMA_XY_PKT(0xc304),
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PSIL_PDMA_XY_PKT(0xc305),
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PSIL_PDMA_XY_PKT(0xc306),
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PSIL_PDMA_XY_PKT(0xc307),
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PSIL_PDMA_XY_PKT(0xc308),
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PSIL_PDMA_XY_PKT(0xc309),
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PSIL_PDMA_XY_PKT(0xc30a),
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PSIL_PDMA_XY_PKT(0xc30b),
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PSIL_PDMA_XY_PKT(0xc30c),
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PSIL_PDMA_XY_PKT(0xc30d),
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/* PDMA_MAIN1 - UART0-6 */
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PSIL_PDMA_XY_PKT(0xc400),
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PSIL_PDMA_XY_PKT(0xc401),
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PSIL_PDMA_XY_PKT(0xc402),
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PSIL_PDMA_XY_PKT(0xc403),
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PSIL_PDMA_XY_PKT(0xc404),
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PSIL_PDMA_XY_PKT(0xc405),
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PSIL_PDMA_XY_PKT(0xc406),
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/* PDMA_MAIN2 - MCASP0-2 */
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PSIL_PDMA_MCASP(0xc500),
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PSIL_PDMA_MCASP(0xc501),
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PSIL_PDMA_MCASP(0xc502),
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/* CPSW3G */
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PSIL_ETHERNET(0xc600, 19, 19, 8),
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PSIL_ETHERNET(0xc601, 20, 27, 8),
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PSIL_ETHERNET(0xc602, 21, 35, 8),
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PSIL_ETHERNET(0xc603, 22, 43, 8),
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PSIL_ETHERNET(0xc604, 23, 51, 8),
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PSIL_ETHERNET(0xc605, 24, 59, 8),
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PSIL_ETHERNET(0xc606, 25, 67, 8),
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PSIL_ETHERNET(0xc607, 26, 75, 8),
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};
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struct psil_ep_map am62_ep_map = {
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.name = "am62",
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.src = am62_src_ep_map,
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.src_count = ARRAY_SIZE(am62_src_ep_map),
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.dst = am62_dst_ep_map,
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.dst_count = ARRAY_SIZE(am62_dst_ep_map),
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};
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@ -42,5 +42,6 @@ extern struct psil_ep_map j721e_ep_map;
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extern struct psil_ep_map j7200_ep_map;
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extern struct psil_ep_map am64_ep_map;
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extern struct psil_ep_map j721s2_ep_map;
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extern struct psil_ep_map am62_ep_map;
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#endif /* K3_PSIL_PRIV_H_ */
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@ -22,6 +22,7 @@ static const struct soc_device_attribute k3_soc_devices[] = {
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{ .family = "J7200", .data = &j7200_ep_map },
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{ .family = "AM64X", .data = &am64_ep_map },
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{ .family = "J721S2", .data = &j721s2_ep_map },
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{ .family = "AM62X", .data = &am62_ep_map },
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{ /* sentinel */ }
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};
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