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[ARM] 5032/1: Added cpufreq support for pxa27x CPU
PXA cpus maximum frequency depends on the cpu (624 for pxa270, 520 for pxa272, 416 for pxa271). It should be provided on kernel or module start (cpu-pxa pxa27x_maxfreq parameter). Make use of cpufreq_frequency_table_cpuinfo (patch by Bill Reese provided by Philipp Zabel). Some additionnal fixes from Philipp Zabel include : * rename PXA cpufreq driver to reflect added PXA27x support * remove unused variable ramstart from PXA cpufreq driver Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Robert Jarzmik <rjarzmik@free.fr> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Robert Jarzmik
Russell King
parent
3679389b88
commit
592eb9997d
@ -49,76 +49,170 @@ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
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#define freq_debug 0
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#endif
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static unsigned int pxa27x_maxfreq;
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module_param(pxa27x_maxfreq, uint, 0);
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MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
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"(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
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typedef struct {
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unsigned int khz;
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unsigned int membus;
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unsigned int cccr;
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unsigned int div2;
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unsigned int cclkcfg;
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} pxa_freqs_t;
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
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#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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#define PXA25x_MIN_FREQ 99500
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#define PXA25x_MAX_FREQ 398100
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#define CCLKCFG_HALFTURBO 0x4
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#define CCLKCFG_FASTBUS 0x8
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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/*
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* PXA255 definitions
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*/
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/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
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#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
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static pxa_freqs_t pxa255_run_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1}, /* 99, 99, 50, 50 */
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{132700, 132700, 0x123, 1}, /* 133, 133, 66, 66 */
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{199100, 99500, 0x141, 0}, /* 199, 199, 99, 99 */
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{265400, 132700, 0x143, 1}, /* 265, 265, 133, 66 */
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{331800, 165900, 0x145, 1}, /* 331, 331, 166, 83 */
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{398100, 99500, 0x161, 0}, /* 398, 398, 196, 99 */
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{0,}
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
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{132700, 132700, 0x123, 1, CCLKCFG}, /* 133, 133, 66, 66 */
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{199100, 99500, 0x141, 0, CCLKCFG}, /* 199, 199, 99, 99 */
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{265400, 132700, 0x143, 1, CCLKCFG}, /* 265, 265, 133, 66 */
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{331800, 165900, 0x145, 1, CCLKCFG}, /* 331, 331, 166, 83 */
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{398100, 99500, 0x161, 0, CCLKCFG}, /* 398, 398, 196, 99 */
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};
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#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
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static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
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/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
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static pxa_freqs_t pxa255_turbo_freqs[] =
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{
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/* CPU MEMBUS CCCR DIV2 run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1}, /* 99, 99, 50, 50 */
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{199100, 99500, 0x221, 0}, /* 99, 199, 50, 99 */
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{298500, 99500, 0x321, 0}, /* 99, 287, 50, 99 */
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{298600, 99500, 0x1c1, 0}, /* 199, 287, 99, 99 */
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{398100, 99500, 0x241, 0}, /* 199, 398, 99, 99 */
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{0,}
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/* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
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{ 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
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{199100, 99500, 0x221, 0, CCLKCFG}, /* 99, 199, 50, 99 */
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{298500, 99500, 0x321, 0, CCLKCFG}, /* 99, 287, 50, 99 */
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{298600, 99500, 0x1c1, 0, CCLKCFG}, /* 199, 287, 99, 99 */
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{398100, 99500, 0x241, 0, CCLKCFG}, /* 199, 398, 99, 99 */
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};
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#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
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#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
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#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
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static struct cpufreq_frequency_table
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pxa255_turbo_freq_table[NUM_TURBO_FREQS+1];
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pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
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static struct cpufreq_frequency_table
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pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
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/*
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* PXA270 definitions
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*
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* For the PXA27x:
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* Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
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*
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* A = 0 => memory controller clock from table 3-7,
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* A = 1 => memory controller clock = system bus clock
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* Run mode frequency = 13 MHz * L
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* Turbo mode frequency = 13 MHz * L * N
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* System bus frequency = 13 MHz * L / (B + 1)
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*
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* In CCCR:
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* A = 1
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* L = 16 oscillator to run mode ratio
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* 2N = 6 2 * (turbo mode to run mode ratio)
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*
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* In CCLKCFG:
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* B = 1 Fast bus mode
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* HT = 0 Half-Turbo mode
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* T = 1 Turbo mode
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*
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* For now, just support some of the combinations in table 3-7 of
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* PXA27x Processor Family Developer's Manual to simplify frequency
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* change sequences.
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*/
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#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
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#define CCLKCFG2(B, HT, T) \
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(CCLKCFG_FCS | \
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((B) ? CCLKCFG_FASTBUS : 0) | \
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((HT) ? CCLKCFG_HALFTURBO : 0) | \
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((T) ? CCLKCFG_TURBO : 0))
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static pxa_freqs_t pxa27x_freqs[] = {
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{104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1)},
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{156000, 104000, PXA27x_CCCR(1, 8, 6), 0, CCLKCFG2(1, 1, 1)},
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{208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
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{312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
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{416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
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{520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
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{624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
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};
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#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
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static struct cpufreq_frequency_table
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pxa27x_freq_table[NUM_PXA27x_FREQS+1];
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extern unsigned get_clk_frequency_khz(int info);
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static void find_freq_tables(struct cpufreq_policy *policy,
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struct cpufreq_frequency_table **freq_table,
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pxa_freqs_t **pxa_freqs)
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{
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if (cpu_is_pxa25x()) {
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if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
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*pxa_freqs = pxa255_run_freqs;
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*freq_table = pxa255_run_freq_table;
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} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
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*pxa_freqs = pxa255_turbo_freqs;
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*freq_table = pxa255_turbo_freq_table;
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} else {
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printk("CPU PXA: Unknown policy found. "
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"Using CPUFREQ_POLICY_PERFORMANCE\n");
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*pxa_freqs = pxa255_run_freqs;
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*freq_table = pxa255_run_freq_table;
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}
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}
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if (cpu_is_pxa27x()) {
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*pxa_freqs = pxa27x_freqs;
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*freq_table = pxa27x_freq_table;
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}
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}
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static void pxa27x_guess_max_freq(void)
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{
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if (!pxa27x_maxfreq) {
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pxa27x_maxfreq = 416000;
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printk(KERN_INFO "PXA CPU 27x max frequency not defined "
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"(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
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pxa27x_maxfreq);
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} else {
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pxa27x_maxfreq *= 1000;
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}
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}
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static u32 mdrefr_dri(unsigned int freq)
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{
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u32 dri = 0;
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if (cpu_is_pxa25x())
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dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
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if (cpu_is_pxa27x())
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dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
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return dri;
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}
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/* find a valid frequency point */
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static int pxa_verify_policy(struct cpufreq_policy *policy)
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{
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struct cpufreq_frequency_table *pxa_freqs_table;
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pxa_freqs_t *pxa_freqs;
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int ret;
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if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
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pxa_freqs_table = pxa255_run_freq_table;
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} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
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pxa_freqs_table = pxa255_turbo_freq_table;
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} else {
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printk("CPU PXA: Unknown policy found. "
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"Using CPUFREQ_POLICY_PERFORMANCE\n");
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pxa_freqs_table = pxa255_run_freq_table;
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}
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find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs);
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ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
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if (freq_debug)
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@ -128,6 +222,11 @@ static int pxa_verify_policy(struct cpufreq_policy *policy)
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return ret;
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}
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static unsigned int pxa_cpufreq_get(unsigned int cpu)
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{
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return get_clk_frequency_khz(0);
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}
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static int pxa_set_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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@ -137,22 +236,11 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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struct cpufreq_freqs freqs;
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unsigned int idx;
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unsigned long flags;
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unsigned int unused, preset_mdrefr, postset_mdrefr;
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void *ramstart = phys_to_virt(0xa0000000);
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unsigned int new_freq_cpu, new_freq_mem;
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unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
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/* Get the current policy */
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if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
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pxa_freq_settings = pxa255_run_freqs;
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pxa_freqs_table = pxa255_run_freq_table;
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} else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
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pxa_freq_settings = pxa255_turbo_freqs;
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pxa_freqs_table = pxa255_turbo_freq_table;
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} else {
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printk("CPU PXA: Unknown policy found. "
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"Using CPUFREQ_POLICY_PERFORMANCE\n");
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pxa_freq_settings = pxa255_run_freqs;
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pxa_freqs_table = pxa255_run_freq_table;
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}
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find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings);
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/* Lookup the next frequency */
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if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
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@ -160,16 +248,17 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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return -EINVAL;
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}
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new_freq_cpu = pxa_freq_settings[idx].khz;
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new_freq_mem = pxa_freq_settings[idx].membus;
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freqs.old = policy->cur;
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freqs.new = pxa_freq_settings[idx].khz;
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freqs.new = new_freq_cpu;
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freqs.cpu = policy->cpu;
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if (freq_debug)
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pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
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"(SDRAM %d Mhz)\n",
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freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
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(pxa_freq_settings[idx].membus / 2000) :
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(pxa_freq_settings[idx].membus / 1000));
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(new_freq_mem / 2000) : (new_freq_mem / 1000));
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/*
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* Tell everyone what we're about to do...
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@ -183,13 +272,12 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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* speeding up we need to set the larger DRI value after the change.
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*/
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preset_mdrefr = postset_mdrefr = MDREFR;
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if ((MDREFR & MDREFR_DRI_MASK) >
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MDREFR_DRI(pxa_freq_settings[idx].membus)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) |
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
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preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
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preset_mdrefr |= mdrefr_dri(new_freq_mem);
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}
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postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) |
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MDREFR_DRI(pxa_freq_settings[idx].membus);
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postset_mdrefr =
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(postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
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/* If we're dividing the memory clock by two for the SDRAM clock, this
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* must be set prior to the change. Clearing the divide must be done
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@ -204,25 +292,26 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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local_irq_save(flags);
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/* Set new the CCCR */
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/* Set new the CCCR and prepare CCLKCFG */
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CCCR = pxa_freq_settings[idx].cccr;
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cclkcfg = pxa_freq_settings[idx].cclkcfg;
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asm volatile(" \n\
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ldr r4, [%1] /* load MDREFR */ \n\
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b 2f \n\
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.align 5 \n\
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1: \n\
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str %4, [%1] /* preset the MDREFR */ \n\
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str %3, [%1] /* preset the MDREFR */ \n\
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mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
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str %5, [%1] /* postset the MDREFR */ \n\
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str %4, [%1] /* postset the MDREFR */ \n\
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\n\
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b 3f \n\
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2: b 1b \n\
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3: nop \n\
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"
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: "=&r" (unused)
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: "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r" (&MDREFR), "r" (cclkcfg),
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"r" (preset_mdrefr), "r" (postset_mdrefr)
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: "r4", "r5");
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local_irq_restore(flags);
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@ -236,39 +325,57 @@ static int pxa_set_target(struct cpufreq_policy *policy,
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return 0;
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}
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static unsigned int pxa_cpufreq_get(unsigned int cpu)
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{
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return get_clk_frequency_khz(0);
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}
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static int pxa_cpufreq_init(struct cpufreq_policy *policy)
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static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
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{
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int i;
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unsigned int freq;
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/* try to guess pxa27x cpu */
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if (cpu_is_pxa27x())
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pxa27x_guess_max_freq();
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/* set default policy and cpuinfo */
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policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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policy->policy = CPUFREQ_POLICY_PERFORMANCE;
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policy->cpuinfo.max_freq = PXA25x_MAX_FREQ;
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policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
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if (cpu_is_pxa25x())
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policy->policy = CPUFREQ_POLICY_PERFORMANCE;
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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policy->cur = get_clk_frequency_khz(0); /* current freq */
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policy->min = policy->max = policy->cur;
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/* Generate the run cpufreq_frequency_table struct */
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for (i = 0; i < NUM_RUN_FREQS; i++) {
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/* Generate pxa25x the run cpufreq_frequency_table struct */
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for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
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pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
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pxa255_run_freq_table[i].index = i;
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}
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pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
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/* Generate the turbo cpufreq_frequency_table struct */
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for (i = 0; i < NUM_TURBO_FREQS; i++) {
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/* Generate pxa25x the turbo cpufreq_frequency_table struct */
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for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
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pxa255_turbo_freq_table[i].frequency =
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pxa255_turbo_freqs[i].khz;
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pxa255_turbo_freq_table[i].index = i;
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}
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pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
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/* Generate the pxa27x cpufreq_frequency_table struct */
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for (i = 0; i < NUM_PXA27x_FREQS; i++) {
|
||||
freq = pxa27x_freqs[i].khz;
|
||||
if (freq > pxa27x_maxfreq)
|
||||
break;
|
||||
pxa27x_freq_table[i].frequency = freq;
|
||||
pxa27x_freq_table[i].index = i;
|
||||
}
|
||||
pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
|
||||
|
||||
/*
|
||||
* Set the policy's minimum and maximum frequencies from the tables
|
||||
* just constructed. This sets cpuinfo.mxx_freq, min and max.
|
||||
*/
|
||||
if (cpu_is_pxa25x())
|
||||
cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table);
|
||||
else if (cpu_is_pxa27x())
|
||||
cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
|
||||
|
||||
printk(KERN_INFO "PXA CPU frequency change support initialized\n");
|
||||
|
||||
return 0;
|
||||
@ -279,21 +386,20 @@ static struct cpufreq_driver pxa_cpufreq_driver = {
|
||||
.target = pxa_set_target,
|
||||
.init = pxa_cpufreq_init,
|
||||
.get = pxa_cpufreq_get,
|
||||
.name = "PXA25x",
|
||||
.name = "PXA2xx",
|
||||
};
|
||||
|
||||
static int __init pxa_cpu_init(void)
|
||||
{
|
||||
int ret = -ENODEV;
|
||||
if (cpu_is_pxa25x())
|
||||
if (cpu_is_pxa25x() || cpu_is_pxa27x())
|
||||
ret = cpufreq_register_driver(&pxa_cpufreq_driver);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void __exit pxa_cpu_exit(void)
|
||||
{
|
||||
if (cpu_is_pxa25x())
|
||||
cpufreq_unregister_driver(&pxa_cpufreq_driver);
|
||||
cpufreq_unregister_driver(&pxa_cpufreq_driver);
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user