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drm fixes for 5.3-rc8

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lima:
 - fix gem_wait ioctl
 
 core:
 - constify modes list
 
 i915:
 - DP MST high color depth regression
 - GPU hangs on vulkan compute workloads
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Merge tag 'drm-fixes-2019-09-13' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "From the maintainer summit, just some last minute fixes for final:

  lima:
   - fix gem_wait ioctl

  core:
   - constify modes list

  i915:
   - DP MST high color depth regression
   - GPU hangs on vulkan compute workloads"

* tag 'drm-fixes-2019-09-13' of git://anongit.freedesktop.org/drm/drm:
  drm/lima: fix lima_gem_wait() return value
  drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+
  drm/i915: Limit MST to <= 8bpc once again
  drm/modes: Make the whitelist more const
This commit is contained in:
Linus Torvalds 2019-09-14 11:54:57 -07:00
commit 592b8d8759
4 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/drm_modes.c
View File

@ -1677,7 +1677,7 @@ static int drm_mode_parse_cmdline_options(char *str, size_t len,
return 0;
}
static const char *drm_named_modes_whitelist[] = {
static const char * const drm_named_modes_whitelist[] = {
"NTSC",
"PAL",
};

10
drivers/gpu/drm/i915/display/intel_dp_mst.c
View File

@ -128,7 +128,15 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
limits.min_bpp = intel_dp_min_bpp(pipe_config);
limits.max_bpp = pipe_config->pipe_bpp;
/*
* FIXME: If all the streams can't fit into the link with
* their current pipe_bpp we should reduce pipe_bpp across
* the board until things start to fit. Until then we
* limit to <= 8bpc since that's what was hardcoded for all
* MST streams previously. This hack should be removed once
* we have the proper retry logic in place.
*/
limits.max_bpp = min(pipe_config->pipe_bpp, 24);
intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);

5
drivers/gpu/drm/i915/gt/intel_workarounds.c
View File

@ -308,11 +308,6 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
FLOW_CONTROL_ENABLE |
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
if (!IS_COFFEELAKE(i915))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,

2
drivers/gpu/drm/lima/lima_gem.c
View File

@ -342,7 +342,7 @@ int lima_gem_wait(struct drm_file *file, u32 handle, u32 op, s64 timeout_ns)
timeout = drm_timeout_abs_to_jiffies(timeout_ns);
ret = drm_gem_reservation_object_wait(file, handle, write, timeout);
if (ret == 0)
if (ret == -ETIME)
ret = timeout ? -ETIMEDOUT : -EBUSY;
return ret;