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Blackfin arch: IO Port functions to read/write unalligned memory

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Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Michael Hennerich 2008-05-17 16:38:52 +08:00 committed by Bryan Wu
parent 86ad79321c
commit 5906967638
4 changed files with 37 additions and 4 deletions
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2
arch/blackfin/kernel/bfin_ksyms.c
View File

@ -90,7 +90,9 @@ EXPORT_SYMBOL(__umodsi3);
EXPORT_SYMBOL(outsb);
EXPORT_SYMBOL(insb);
EXPORT_SYMBOL(outsw);
EXPORT_SYMBOL(outsw_8);
EXPORT_SYMBOL(insw);
EXPORT_SYMBOL(insw_8);
EXPORT_SYMBOL(outsl);
EXPORT_SYMBOL(insl);
EXPORT_SYMBOL(insl_16);

21
arch/blackfin/lib/ins.S
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@ -7,7 +7,7 @@
* Description: Implementation of ins{bwl} for BlackFin processors using zero overhead loops.
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
* Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
@ -63,6 +63,23 @@ ENTRY(_insw)
RTS;
ENDPROC(_insw)
ENTRY(_insw_8)
P0 = R0; /* P0 = port */
cli R3;
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
SSYNC;
LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
.Lword8_loop_s: R0 = W[P0];
B[P1++] = R0;
R0 = R0 >> 8;
B[P1++] = R0;
NOP;
.Lword8_loop_e: NOP;
sti R3;
RTS;
ENDPROC(_insw_8)
ENTRY(_insb)
P0 = R0; /* P0 = port */
cli R3;
@ -78,8 +95,6 @@ ENTRY(_insb)
RTS;
ENDPROC(_insb)
ENTRY(_insl_16)
P0 = R0; /* P0 = port */
cli R3;

16
arch/blackfin/lib/outs.S
View File

@ -7,7 +7,7 @@
* Description: Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
*
* Modified: Copyright (C) 2005 Bas Vermeulen, BuyWays BV <bas@buyways.nl>
* Copyright 2004-2006 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@ -63,3 +63,17 @@ ENTRY(_outsb)
.Lbyte_loop_e: B[P0] = R0;
RTS;
ENDPROC(_outsb)
ENTRY(_outsw_8)
P0 = R0; /* P0 = port */
P1 = R1; /* P1 = address */
P2 = R2; /* P2 = count */
LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
.Lword8_loop_s: R1 = B[P1++];
R0 = B[P1++];
R0 = R0 << 8;
R0 = R0 + R1;
.Lword8_loop_e: W[P0] = R0;
RTS;
ENDPROC(_outsw)

2
include/asm-blackfin/io.h
View File

@ -117,10 +117,12 @@ static inline unsigned int readl(const volatile void __iomem *addr)
extern void outsb(unsigned long port, const void *addr, unsigned long count);
extern void outsw(unsigned long port, const void *addr, unsigned long count);
extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
extern void outsl(unsigned long port, const void *addr, unsigned long count);
extern void insb(unsigned long port, void *addr, unsigned long count);
extern void insw(unsigned long port, void *addr, unsigned long count);
extern void insw_8(unsigned long port, void *addr, unsigned long count);
extern void insl(unsigned long port, void *addr, unsigned long count);
extern void insl_16(unsigned long port, void *addr, unsigned long count);