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OMAP3 SDRC: add support for 2 SDRAM chip selects
Some OMAP3 boards (Beagle Cx, Overo, RX51, Pandora) have 2 SDRAM parts connected to the SDRC. This patch adds the following: - add a new argument of type omap_sdrc_params struct* to omap2_init_common_hw and omap2_sdrc_init for the 2nd CS params - adapted the OMAP boards files to the new prototype of omap2_init_common_hw - add the SDRC 2nd CS registers offsets defines - adapt the sram sleep code to configure the SDRC for the 2nd CS Note: If the 2nd param to omap2_init_common_hw is NULL, then the parameters are not programmed into the SDRC CS1 registers Tested on 3430 SDP and Beagleboard rev C2 and B5, with suspend/resume and frequency changes (cpufreq). Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Jean Pihet
paul
parent
4be3bd7849
commit
58cda884ec
@ -141,7 +141,7 @@ static inline void board_smc91x_init(void)
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static void __init omap_2430sdp_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -169,7 +169,7 @@ static struct platform_device *sdp3430_devices[] __initdata = {
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static void __init omap_3430sdp_init_irq(void)
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{
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omap2_init_common_hw(hyb18m512160af6_sdrc_params);
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omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -59,7 +59,7 @@ static void __init gic_init_irq(void)
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static void __init omap_4430sdp_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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#ifdef CONFIG_OMAP_32K_TIMER
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omap2_gp_clockevent_set_gptimer(1);
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#endif
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@ -250,7 +250,7 @@ out:
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static void __init omap_apollon_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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apollon_init_smc91x();
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@ -33,7 +33,7 @@
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static void __init omap_generic_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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}
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@ -270,7 +270,7 @@ static void __init h4_init_flash(void)
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static void __init omap_h4_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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h4_init_flash();
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@ -270,7 +270,7 @@ static inline void __init ldp_init_smsc911x(void)
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static void __init omap_ldp_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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ldp_init_smsc911x();
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@ -282,7 +282,8 @@ static int __init omap3_beagle_i2c_init(void)
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static void __init omap3_beagle_init_irq(void)
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{
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
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mt46h32m32lf6_sdrc_params);
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omap_init_irq();
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#ifdef CONFIG_OMAP_32K_TIMER
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omap2_gp_clockevent_set_gptimer(12);
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@ -279,7 +279,7 @@ struct spi_board_info omap3evm_spi_board_info[] = {
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static void __init omap3_evm_init_irq(void)
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{
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
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omap_init_irq();
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omap_gpio_init();
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omap3evm_init_smc911x();
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@ -310,7 +310,8 @@ static int __init omap3pandora_i2c_init(void)
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static void __init omap3pandora_init_irq(void)
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{
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
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mt46h32m32lf6_sdrc_params);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -360,7 +360,8 @@ static int __init overo_i2c_init(void)
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static void __init overo_init_irq(void)
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{
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params);
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omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
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mt46h32m32lf6_sdrc_params);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -61,7 +61,7 @@ static struct omap_board_config_kernel rx51_config[] = {
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static void __init rx51_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -25,7 +25,7 @@
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static void __init omap_zoom2_init_irq(void)
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{
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omap2_init_common_hw(NULL);
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omap2_init_common_hw(NULL, NULL);
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omap_init_irq();
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omap_gpio_init();
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}
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@ -725,7 +725,9 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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u32 unlock_dll = 0;
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u32 c;
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unsigned long validrate, sdrcrate, mpurate;
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struct omap_sdrc_params *sp;
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struct omap_sdrc_params *sdrc_cs0;
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struct omap_sdrc_params *sdrc_cs1;
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int ret;
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if (!clk || !rate)
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return -EINVAL;
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@ -743,8 +745,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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else
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sdrcrate >>= ((clk->rate / rate) >> 1);
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sp = omap2_sdrc_get_params(sdrcrate);
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if (!sp)
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ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
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if (ret)
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return -EINVAL;
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if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
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@ -765,12 +767,29 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
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validrate);
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pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
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sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
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pr_debug("clock: SDRC CS0 timing params used:"
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" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
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if (sdrc_cs1)
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pr_debug("clock: SDRC CS1 timing params used: "
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" RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
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sp->actim_ctrlb, new_div, unlock_dll, c,
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sp->mr, rate > clk->rate);
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if (sdrc_cs1)
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clk->rate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
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sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
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else
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omap3_configure_core_dpll(
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new_div, unlock_dll, c, rate > clk->rate,
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sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
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sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
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0, 0, 0, 0);
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return 0;
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}
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@ -276,14 +276,15 @@ static int __init _omap2_init_reprogram_sdrc(void)
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return v;
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}
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void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
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void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
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struct omap_sdrc_params *sdrc_cs1)
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{
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omap2_mux_init();
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#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
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pwrdm_init(powerdomains_omap);
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clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
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omap2_clk_init();
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omap2_sdrc_init(sp);
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omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
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_omap2_init_reprogram_sdrc();
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#endif
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gpmc_init();
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@ -32,7 +32,7 @@
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#include <mach/sdrc.h>
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#include "sdrc.h"
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static struct omap_sdrc_params *sdrc_init_params;
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static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
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void __iomem *omap2_sdrc_base;
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void __iomem *omap2_sms_base;
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@ -45,33 +45,49 @@ void __iomem *omap2_sms_base;
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/**
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* omap2_sdrc_get_params - return SDRC register values for a given clock rate
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* @r: SDRC clock rate (in Hz)
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* @sdrc_cs0: chip select 0 ram timings **
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* @sdrc_cs1: chip select 1 ram timings **
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*
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* Return pre-calculated values for the SDRC_ACTIM_CTRLA,
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* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given
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* SDRC clock rate 'r'. These parameters control various timing
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* delays in the SDRAM controller that are expressed in terms of the
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* number of SDRC clock cycles to wait; hence the clock rate
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* dependency. Note that sdrc_init_params must be sorted rate
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* descending. Also assumes that both chip-selects use the same
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* timing parameters. Returns a struct omap_sdrc_params * upon
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* success, or NULL upon failure.
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* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
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* structs,for a given SDRC clock rate 'r'.
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* These parameters control various timing delays in the SDRAM controller
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* that are expressed in terms of the number of SDRC clock cycles to
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* wait; hence the clock rate dependency.
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*
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* Supports 2 different timing parameters for both chip selects.
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*
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* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
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* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
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* as sdrc_init_params_cs_0.
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*
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* Fills in the struct omap_sdrc_params * for each chip select.
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* Returns 0 upon success or -1 upon failure.
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*/
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struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r)
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int omap2_sdrc_get_params(unsigned long r,
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struct omap_sdrc_params **sdrc_cs0,
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struct omap_sdrc_params **sdrc_cs1)
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{
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struct omap_sdrc_params *sp;
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struct omap_sdrc_params *sp0, *sp1;
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if (!sdrc_init_params)
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return NULL;
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if (!sdrc_init_params_cs0)
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return -1;
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sp = sdrc_init_params;
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sp0 = sdrc_init_params_cs0;
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sp1 = sdrc_init_params_cs1;
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while (sp->rate && sp->rate != r)
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sp++;
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while (sp0->rate && sp0->rate != r) {
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sp0++;
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if (sdrc_init_params_cs1)
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sp1++;
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}
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if (!sp->rate)
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return NULL;
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if (!sp0->rate)
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return -1;
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return sp;
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*sdrc_cs0 = sp0;
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*sdrc_cs1 = sp1;
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return 0;
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}
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@ -83,13 +99,15 @@ void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
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/**
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* omap2_sdrc_init - initialize SMS, SDRC devices on boot
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* @sp: pointer to a null-terminated list of struct omap_sdrc_params
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* @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
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* Support for 2 chip selects timings
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*
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* Turn on smart idle modes for SDRAM scheduler and controller.
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* Program a known-good configuration for the SDRC to deal with buggy
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* bootloaders.
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*/
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void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
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struct omap_sdrc_params *sdrc_cs1)
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{
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u32 l;
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@ -103,7 +121,8 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
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l |= (0x2 << 3);
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sdrc_write_reg(l, SDRC_SYSCONFIG);
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sdrc_init_params = sp;
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sdrc_init_params_cs0 = sdrc_cs0;
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sdrc_init_params_cs1 = sdrc_cs1;
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/* XXX Enable SRFRONIDLEREQ here also? */
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l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
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@ -36,7 +36,7 @@
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.text
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/* r4 parameters */
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/* r1 parameters */
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#define SDRC_NO_UNLOCK_DLL 0x0
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#define SDRC_UNLOCK_DLL 0x1
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@ -71,40 +71,71 @@
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/*
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* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
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* r0 = new SDRC_RFR_CTRL register contents
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* r1 = new SDRC_ACTIM_CTRLA register contents
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* r2 = new SDRC_ACTIM_CTRLB register contents
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* r3 = new M2 divider setting (only 1 and 2 supported right now)
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* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = new SDRC_MR_0 register value
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* r7 = increasing SDRC rate? (1 = yes, 0 = no)
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*
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* Params passed in registers:
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* r0 = new M2 divider setting (only 1 and 2 supported right now)
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* r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
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* SDRC rates < 83MHz
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* r2 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r3 = increasing SDRC rate? (1 = yes, 0 = no)
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*
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* Params passed via the stack. The needed params will be copied in SRAM
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* before use by the code in SRAM (SDRAM is not accessible during SDRC
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* reconfiguration):
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* new SDRC_RFR_CTRL_0 register contents
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* new SDRC_ACTIM_CTRL_A_0 register contents
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* new SDRC_ACTIM_CTRL_B_0 register contents
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* new SDRC_MR_0 register value
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* new SDRC_RFR_CTRL_1 register contents
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* new SDRC_ACTIM_CTRL_A_1 register contents
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* new SDRC_ACTIM_CTRL_B_1 register contents
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* new SDRC_MR_1 register value
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*
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* If the param SDRC_RFR_CTRL_1 is 0, the parameters
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* are not programmed into the SDRC CS1 registers
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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ldr r7, [sp, #64] @ load extra args from the stack
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@ pull the extra args off the stack
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@ and store them in SRAM
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ldr r4, [sp, #52]
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str r4, omap_sdrc_rfr_ctrl_0_val
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ldr r4, [sp, #56]
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str r4, omap_sdrc_actim_ctrl_a_0_val
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ldr r4, [sp, #60]
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str r4, omap_sdrc_actim_ctrl_b_0_val
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ldr r4, [sp, #64]
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str r4, omap_sdrc_mr_0_val
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ldr r4, [sp, #68]
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str r4, omap_sdrc_rfr_ctrl_1_val
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cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
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beq skip_cs1_params @ do not use cs1 params
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ldr r4, [sp, #72]
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str r4, omap_sdrc_actim_ctrl_a_1_val
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ldr r4, [sp, #76]
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str r4, omap_sdrc_actim_ctrl_b_1_val
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ldr r4, [sp, #80]
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str r4, omap_sdrc_mr_1_val
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skip_cs1_params:
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dsb @ flush buffered writes to interconnect
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cmp r7, #1 @ if increasing SDRC clk rate,
|
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|
||||
cmp r3, #1 @ if increasing SDRC clk rate,
|
||||
bleq configure_sdrc @ program the SDRC regs early (for RFR)
|
||||
cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
|
||||
cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
|
||||
bleq unlock_dll
|
||||
blne lock_dll
|
||||
bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
|
||||
bl configure_core_dpll @ change the DPLL3 M2 divider
|
||||
bl enable_sdrc @ take SDRC out of idle
|
||||
cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
|
||||
cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
|
||||
bleq wait_dll_unlock
|
||||
blne wait_dll_lock
|
||||
cmp r7, #1 @ if increasing SDRC clk rate,
|
||||
cmp r3, #1 @ if increasing SDRC clk rate,
|
||||
beq return_to_sdram @ return to SDRAM code, otherwise,
|
||||
bl configure_sdrc @ reprogram SDRC regs now
|
||||
mov r12, r5
|
||||
mov r12, r2
|
||||
bl wait_clk_stable @ wait for SDRC to stabilize
|
||||
return_to_sdram:
|
||||
isb @ prevent speculative exec past here
|
||||
@ -149,7 +180,7 @@ configure_core_dpll:
|
||||
ldr r12, [r11]
|
||||
ldr r10, core_m2_mask_val @ modify m2 for core dpll
|
||||
and r12, r12, r10
|
||||
orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
|
||||
orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
|
||||
str r12, [r11]
|
||||
ldr r12, [r11] @ posted-write barrier for CM
|
||||
bx lr
|
||||
@ -187,15 +218,34 @@ wait_dll_unlock:
|
||||
bne wait_dll_unlock
|
||||
bx lr
|
||||
configure_sdrc:
|
||||
ldr r11, omap3_sdrc_rfr_ctrl
|
||||
str r0, [r11]
|
||||
ldr r11, omap3_sdrc_actim_ctrla
|
||||
str r1, [r11]
|
||||
ldr r11, omap3_sdrc_actim_ctrlb
|
||||
str r2, [r11]
|
||||
ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
|
||||
str r12, [r11] @ store
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_0
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_b_0_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_b_0
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_mr_0_val
|
||||
ldr r11, omap3_sdrc_mr_0
|
||||
str r6, [r11]
|
||||
ldr r6, [r11] @ posted-write barrier for SDRC
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_rfr_ctrl_1_val
|
||||
cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
|
||||
beq skip_cs1_prog @ do not program cs1 params
|
||||
ldr r11, omap3_sdrc_rfr_ctrl_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_a_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_a_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_actim_ctrl_b_1_val
|
||||
ldr r11, omap3_sdrc_actim_ctrl_b_1
|
||||
str r12, [r11]
|
||||
ldr r12, omap_sdrc_mr_1_val
|
||||
ldr r11, omap3_sdrc_mr_1
|
||||
str r12, [r11]
|
||||
skip_cs1_prog:
|
||||
ldr r12, [r11] @ posted-write barrier for SDRC
|
||||
bx lr
|
||||
|
||||
omap3_sdrc_power:
|
||||
@ -206,14 +256,40 @@ omap3_cm_idlest1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
|
||||
omap3_cm_iclken1_core:
|
||||
.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
|
||||
omap3_sdrc_rfr_ctrl:
|
||||
|
||||
omap3_sdrc_rfr_ctrl_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
|
||||
omap3_sdrc_actim_ctrla:
|
||||
omap3_sdrc_rfr_ctrl_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
|
||||
omap3_sdrc_actim_ctrl_a_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
|
||||
omap3_sdrc_actim_ctrlb:
|
||||
omap3_sdrc_actim_ctrl_a_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
|
||||
omap3_sdrc_actim_ctrl_b_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
|
||||
omap3_sdrc_actim_ctrl_b_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
|
||||
omap3_sdrc_mr_0:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
|
||||
omap3_sdrc_mr_1:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
|
||||
omap_sdrc_rfr_ctrl_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_rfr_ctrl_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_a_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_a_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_b_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_actim_ctrl_b_1_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_mr_0_val:
|
||||
.word 0xDEADBEEF
|
||||
omap_sdrc_mr_1_val:
|
||||
.word 0xDEADBEEF
|
||||
|
||||
omap3_sdrc_dlla_status:
|
||||
.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
|
||||
omap3_sdrc_dlla_ctrl:
|
||||
@ -223,3 +299,4 @@ core_m2_mask_val:
|
||||
|
||||
ENTRY(omap3_sram_configure_core_dpll_sz)
|
||||
.word . - omap3_sram_configure_core_dpll
|
||||
|
||||
|
||||
@ -228,7 +228,8 @@ extern void omap1_map_common_io(void);
|
||||
extern void omap1_init_common_hw(void);
|
||||
|
||||
extern void omap2_map_common_io(void);
|
||||
extern void omap2_init_common_hw(struct omap_sdrc_params *sp);
|
||||
extern void omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1);
|
||||
|
||||
#define __arch_ioremap(p,s,t) omap_ioremap(p,s,t)
|
||||
#define __arch_iounmap(v) omap_iounmap(v)
|
||||
|
||||
@ -30,6 +30,10 @@
|
||||
#define SDRC_ACTIM_CTRL_A_0 0x09c
|
||||
#define SDRC_ACTIM_CTRL_B_0 0x0a0
|
||||
#define SDRC_RFR_CTRL_0 0x0a4
|
||||
#define SDRC_MR_1 0x0B4
|
||||
#define SDRC_ACTIM_CTRL_A_1 0x0C4
|
||||
#define SDRC_ACTIM_CTRL_B_1 0x0C8
|
||||
#define SDRC_RFR_CTRL_1 0x0D4
|
||||
|
||||
/*
|
||||
* These values represent the number of memory clock cycles between
|
||||
@ -102,8 +106,11 @@ struct omap_sdrc_params {
|
||||
u32 mr;
|
||||
};
|
||||
|
||||
void __init omap2_sdrc_init(struct omap_sdrc_params *sp);
|
||||
struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r);
|
||||
void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
||||
struct omap_sdrc_params *sdrc_cs1);
|
||||
int omap2_sdrc_get_params(unsigned long r,
|
||||
struct omap_sdrc_params **sdrc_cs0,
|
||||
struct omap_sdrc_params **sdrc_cs1);
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP2
|
||||
|
||||
|
||||
@ -21,11 +21,12 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
||||
u32 mem_type);
|
||||
extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
|
||||
|
||||
extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2,
|
||||
u32 unlock_dll, u32 f, u32 sdrc_mr,
|
||||
u32 inc);
|
||||
extern u32 omap3_configure_core_dpll(
|
||||
u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
|
||||
|
||||
/* Do not use these */
|
||||
extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
|
||||
@ -59,12 +60,12 @@ extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
|
||||
u32 mem_type);
|
||||
extern unsigned long omap243x_sram_reprogram_sdrc_sz;
|
||||
|
||||
|
||||
extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2,
|
||||
u32 unlock_dll, u32 f, u32 sdrc_mr,
|
||||
u32 inc);
|
||||
extern u32 omap3_sram_configure_core_dpll(
|
||||
u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
|
||||
extern unsigned long omap3_sram_configure_core_dpll_sz;
|
||||
|
||||
#endif
|
||||
|
||||
@ -373,20 +373,26 @@ static inline int omap243x_sram_init(void)
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP3
|
||||
|
||||
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb,
|
||||
u32 m2, u32 unlock_dll,
|
||||
u32 f, u32 sdrc_mr, u32 inc);
|
||||
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
|
||||
u32 f, u32 sdrc_mr, u32 inc)
|
||||
static u32 (*_omap3_sram_configure_core_dpll)(
|
||||
u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
|
||||
|
||||
u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
|
||||
u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
|
||||
u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
|
||||
u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
|
||||
u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
|
||||
{
|
||||
BUG_ON(!_omap3_sram_configure_core_dpll);
|
||||
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
|
||||
sdrc_actim_ctrla,
|
||||
sdrc_actim_ctrlb, m2,
|
||||
unlock_dll, f, sdrc_mr, inc);
|
||||
return _omap3_sram_configure_core_dpll(
|
||||
m2, unlock_dll, f, inc,
|
||||
sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
|
||||
sdrc_actim_ctrl_b_0, sdrc_mr_0,
|
||||
sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
|
||||
sdrc_actim_ctrl_b_1, sdrc_mr_1);
|
||||
}
|
||||
|
||||
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user