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ARM: dts: rockchip: add rk3066 vop display nodes
This patch adds the core display subsystem and vop nodes to rk3066. Signed-off-by: Mark Yao <mark.yao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -44,6 +44,11 @@
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};
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};
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display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vop0_out>, <&vop1_out>;
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x10000>;
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@ -57,6 +62,48 @@
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};
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};
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vop0: vop@1010c000 {
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compatible = "rockchip,rk3066-vop";
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reg = <0x1010c000 0x19c>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC0>,
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<&cru DCLK_LCDC0>,
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<&cru HCLK_LCDC0>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3066_PD_VIO>;
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resets = <&cru SRST_LCDC0_AXI>,
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<&cru SRST_LCDC0_AHB>,
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<&cru SRST_LCDC0_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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vop0_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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vop1: vop@1010e000 {
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compatible = "rockchip,rk3066-vop";
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reg = <0x1010e000 0x19c>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_LCDC1>,
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<&cru DCLK_LCDC1>,
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<&cru HCLK_LCDC1>;
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clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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power-domains = <&power RK3066_PD_VIO>;
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resets = <&cru SRST_LCDC1_AXI>,
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<&cru SRST_LCDC1_AHB>,
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<&cru SRST_LCDC1_DCLK>;
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reset-names = "axi", "ahb", "dclk";
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status = "disabled";
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vop1_out: port {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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i2s0: i2s@10118000 {
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compatible = "rockchip,rk3066-i2s";
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reg = <0x10118000 0x2000>;
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