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NTB: Document HW errata

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Add a comment describing the necessary ordering of modifications to the
NTB Limit and Base registers.

Signed-off-by: Jon Mason <jon.mason@intel.com>
This commit is contained in:
Jon Mason 2013-11-01 15:08:19 -07:00
parent dcf81964e1
commit 58b889206e
1 changed files with 12 additions and 0 deletions
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12
drivers/ntb/ntb_hw.c
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@ -689,6 +689,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
*/
writeq(ndev->mw[1].bar_sz + 0x1000, ndev->reg_base +
SNB_PBAR4LMT_OFFSET);
/* HW errata on the Limit registers. They can only be
* written when the base register is 4GB aligned and
* < 32bit. This should already be the case based on the
* driver defaults, but write the Limit registers first
* just in case.
*/
} else {
ndev->limits.max_mw = SNB_MAX_MW;
@ -707,6 +713,12 @@ static int ntb_xeon_setup(struct ntb_device *ndev)
* something silly
*/
writeq(0, ndev->reg_base + SNB_PBAR4LMT_OFFSET);
/* HW errata on the Limit registers. They can only be
* written when the base register is 4GB aligned and
* < 32bit. This should already be the case based on the
* driver defaults, but write the Limit registers first
* just in case.
*/
}
/* The Xeon errata workaround requires setting SBAR Base