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Staging: et131x: Clean up MII control
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Alan Cox
Greg Kroah-Hartman
parent
4ea30f84c5
commit
57aed3b438
@ -1407,97 +1407,46 @@ typedef struct _RXMAC_t { /* Location: */
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/*
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* structure for MII Management Command reg in mac address map.
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* located at address 0x5024
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* bit 1: scan cycle
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* bit 0: read cycle
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*/
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typedef union _MII_MGMT_CMD_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reserved:30; /* bits 2-31 */
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u32 scan_cycle:1; /* bit 1 */
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u32 read_cycle:1; /* bit 0 */
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#else
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u32 read_cycle:1; /* bit 0 */
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u32 scan_cycle:1; /* bit 1 */
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u32 reserved:30; /* bits 2-31 */
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#endif
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} bits;
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} MII_MGMT_CMD_t, *PMII_MGMT_CMD_t;
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/*
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* structure for MII Management Address reg in mac address map.
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* located at address 0x5028
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* 31-13: reserved
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* 12-8: phy addr
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* 7-5: reserved
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* 4-0: register
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*/
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typedef union _MII_MGMT_ADDR_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reserved2:19; /* bit 13-31 */
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u32 phy_addr:5; /* bits 8-12 */
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u32 reserved1:3; /* bits 5-7 */
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u32 reg_addr:5; /* bits 0-4 */
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#else
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u32 reg_addr:5; /* bits 0-4 */
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u32 reserved1:3; /* bits 5-7 */
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u32 phy_addr:5; /* bits 8-12 */
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u32 reserved2:19; /* bit 13-31 */
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#endif
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} bits;
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} MII_MGMT_ADDR_t, *PMII_MGMT_ADDR_t;
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#define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
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/*
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* structure for MII Management Control reg in mac address map.
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* located at address 0x502C
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* 31-16: reserved
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* 15-0: phy control
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*/
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typedef union _MII_MGMT_CTRL_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reserved:16; /* bits 16-31 */
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u32 phy_ctrl:16; /* bits 0-15 */
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#else
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u32 phy_ctrl:16; /* bits 0-15 */
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u32 reserved:16; /* bits 16-31 */
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#endif
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} bits;
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} MII_MGMT_CTRL_t, *PMII_MGMT_CTRL_t;
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/*
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* structure for MII Management Status reg in mac address map.
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* located at address 0x5030
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* 31-16: reserved
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* 15-0: phy control
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*/
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typedef union _MII_MGMT_STAT_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reserved:16; /* bits 16-31 */
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u32 phy_stat:16; /* bits 0-15 */
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#else
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u32 phy_stat:16; /* bits 0-15 */
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u32 reserved:16; /* bits 16-31 */
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#endif
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} bits;
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} MII_MGMT_STAT_t, *PMII_MGMT_STAT_t;
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/*
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* structure for MII Management Indicators reg in mac address map.
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* located at address 0x5034
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* 31-3: reserved
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* 2: not valid
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* 1: scanning
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* 0: busy
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*/
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typedef union _MII_MGMT_INDICATOR_t {
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u32 value;
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struct {
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#ifdef _BIT_FIELDS_HTOL
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u32 reserved:29; /* bits 3-31 */
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u32 not_valid:1; /* bit 2 */
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u32 scanning:1; /* bit 1 */
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u32 busy:1; /* bit 0 */
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#else
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u32 busy:1; /* bit 0 */
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u32 scanning:1; /* bit 1 */
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u32 not_valid:1; /* bit 2 */
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u32 reserved:29; /* bits 3-31 */
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#endif
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} bits;
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} MII_MGMT_INDICATOR_t, *PMII_MGMT_INDICATOR_t;
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#define MGMT_BUSY 0x00000001 /* busy */
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#define MGMT_WAIT 0x00000005 /* busy | not valid */
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/*
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* structure for Interface Control reg in mac address map.
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@ -1634,11 +1583,11 @@ typedef struct _MAC_t { /* Location: */
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u32 rsv2; /* 0x5018 */
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u32 mac_test; /* 0x501C */
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u32 mii_mgmt_cfg; /* 0x5020 */
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MII_MGMT_CMD_t mii_mgmt_cmd; /* 0x5024 */
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MII_MGMT_ADDR_t mii_mgmt_addr; /* 0x5028 */
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MII_MGMT_CTRL_t mii_mgmt_ctrl; /* 0x502C */
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MII_MGMT_STAT_t mii_mgmt_stat; /* 0x5030 */
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MII_MGMT_INDICATOR_t mii_mgmt_indicator; /* 0x5034 */
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u32 mii_mgmt_cmd; /* 0x5024 */
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u32 mii_mgmt_addr; /* 0x5028 */
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u32 mii_mgmt_ctrl; /* 0x502C */
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u32 mii_mgmt_stat; /* 0x5030 */
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u32 mii_mgmt_indicator; /* 0x5034 */
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MAC_IF_CTRL_t if_ctrl; /* 0x5038 */
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MAC_IF_STAT_t if_stat; /* 0x503C */
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MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
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@ -115,69 +115,55 @@ int PhyMiRead(struct et131x_adapter *adapter, uint8_t xcvrAddr,
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struct _MAC_t __iomem *mac = &adapter->regs->mac;
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int status = 0;
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uint32_t delay;
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MII_MGMT_ADDR_t miiAddr;
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MII_MGMT_CMD_t miiCmd;
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MII_MGMT_INDICATOR_t miiIndicator;
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u32 miiAddr;
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u32 miiCmd;
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u32 miiIndicator;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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miiAddr.value = readl(&mac->mii_mgmt_addr.value);
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miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
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miiAddr = readl(&mac->mii_mgmt_addr);
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miiCmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd.value);
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to read from on the correct PHY */
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{
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MII_MGMT_ADDR_t mii_mgmt_addr = { 0 };
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mii_mgmt_addr.bits.phy_addr = xcvrAddr;
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mii_mgmt_addr.bits.reg_addr = xcvrReg;
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writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
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}
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writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
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/* Kick the read cycle off */
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delay = 0;
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writel(0x1, &mac->mii_mgmt_cmd.value);
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writel(0x1, &mac->mii_mgmt_cmd);
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do {
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udelay(50);
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delay++;
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miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
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} while ((miiIndicator.bits.not_valid || miiIndicator.bits.busy) &&
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delay < 50);
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miiIndicator = readl(&mac->mii_mgmt_indicator);
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} while ((miiIndicator & MGMT_WAIT) && delay < 50);
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/* If we hit the max delay, we could not read the register */
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if (delay >= 50) {
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if (delay == 50) {
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dev_warn(&adapter->pdev->dev,
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"xcvrReg 0x%08x could not be read\n", xcvrReg);
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dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
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miiIndicator.value);
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miiIndicator);
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status = -EIO;
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}
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/* If we hit here we were able to read the register and we need to
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* return the value to the caller
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*/
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/* TODO: make this stuff a simple readw()?! */
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{
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MII_MGMT_STAT_t mii_mgmt_stat;
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mii_mgmt_stat.value = readl(&mac->mii_mgmt_stat.value);
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*value = (uint16_t) mii_mgmt_stat.bits.phy_stat;
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}
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* return the value to the caller */
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*value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
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/* Stop the read operation */
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writel(0, &mac->mii_mgmt_cmd.value);
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writel(0, &mac->mii_mgmt_cmd);
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/* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(miiAddr.value, &mac->mii_mgmt_addr.value);
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writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
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writel(miiAddr, &mac->mii_mgmt_addr);
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writel(miiCmd, &mac->mii_mgmt_cmd);
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return status;
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}
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@ -196,37 +182,31 @@ int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
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int status = 0;
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uint8_t xcvrAddr = adapter->Stats.xcvr_addr;
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uint32_t delay;
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MII_MGMT_ADDR_t miiAddr;
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MII_MGMT_CMD_t miiCmd;
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MII_MGMT_INDICATOR_t miiIndicator;
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u32 miiAddr;
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u32 miiCmd;
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u32 miiIndicator;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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miiAddr.value = readl(&mac->mii_mgmt_addr.value);
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miiCmd.value = readl(&mac->mii_mgmt_cmd.value);
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miiAddr = readl(&mac->mii_mgmt_addr);
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miiCmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd.value);
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to write to on the correct PHY */
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{
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MII_MGMT_ADDR_t mii_mgmt_addr;
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mii_mgmt_addr.bits.phy_addr = xcvrAddr;
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mii_mgmt_addr.bits.reg_addr = xcvrReg;
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writel(mii_mgmt_addr.value, &mac->mii_mgmt_addr.value);
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}
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writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
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/* Add the value to write to the registers to the mac */
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writel(value, &mac->mii_mgmt_ctrl.value);
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writel(value, &mac->mii_mgmt_ctrl);
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delay = 0;
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do {
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udelay(50);
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delay++;
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miiIndicator.value = readl(&mac->mii_mgmt_indicator.value);
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} while (miiIndicator.bits.busy && delay < 100);
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miiIndicator = readl(&mac->mii_mgmt_indicator);
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} while ((miiIndicator & MGMT_BUSY) && delay < 100);
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/* If we hit the max delay, we could not write the register */
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if (delay == 100) {
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@ -235,23 +215,22 @@ int MiWrite(struct et131x_adapter *adapter, uint8_t xcvrReg, uint16_t value)
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dev_warn(&adapter->pdev->dev,
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"xcvrReg 0x%08x could not be written", xcvrReg);
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dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
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miiIndicator.value);
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miiIndicator);
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dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
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readl(&mac->mii_mgmt_cmd.value));
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readl(&mac->mii_mgmt_cmd));
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MiRead(adapter, xcvrReg, &TempValue);
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status = -EIO;
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}
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/* Stop the write operation */
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writel(0, &mac->mii_mgmt_cmd.value);
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writel(0, &mac->mii_mgmt_cmd);
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/* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(miiAddr.value, &mac->mii_mgmt_addr.value);
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writel(miiCmd.value, &mac->mii_mgmt_cmd.value);
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writel(miiAddr, &mac->mii_mgmt_addr);
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writel(miiCmd, &mac->mii_mgmt_cmd);
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return status;
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}
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