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thermal: exynos: Add support for many TRIMINFO_CTRL registers
This patch support many TRIMINFO_CTRL registers if specific Exynos SoC has one more TRIMINFO_CTRL registers. Also this patch uses proper 'RELOAD' shift/mask bit operation to set RELOAD feature instead of static value. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Zhang Rui <rui.zhang@intel.com> Cc: Eduardo Valentin <edubezval@gmail.com> Cc: Amit Daniel Kachhap <amit.daniel@samsung.com> Reviewed-by: Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by: Eduardo Valentin <edubezval@gmail.com>
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@ -27,6 +27,7 @@
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#define SENSOR_NAME_LEN 16
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#define MAX_TRIP_COUNT 8
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#define MAX_COOLING_DEVICE 4
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#define MAX_TRIMINFO_CTRL_REG 2
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#define ACTIVE_INTERVAL 500
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#define IDLE_INTERVAL 10000
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@ -127,7 +127,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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struct exynos_tmu_data *data = platform_get_drvdata(pdev);
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struct exynos_tmu_platform_data *pdata = data->pdata;
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const struct exynos_tmu_registers *reg = pdata->registers;
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unsigned int status, trim_info = 0, con;
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unsigned int status, trim_info = 0, con, ctrl;
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unsigned int rising_threshold = 0, falling_threshold = 0;
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int ret = 0, threshold_code, i;
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@ -144,8 +144,17 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
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}
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}
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if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
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__raw_writel(1, data->base + reg->triminfo_ctrl);
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if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) {
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for (i = 0; i < reg->triminfo_ctrl_count; i++) {
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if (pdata->triminfo_reload[i]) {
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ctrl = readl(data->base +
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reg->triminfo_ctrl[i]);
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ctrl |= pdata->triminfo_reload[i];
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writel(ctrl, data->base +
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reg->triminfo_ctrl[i]);
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}
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}
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}
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/* Save trimming info in order to perform calibration */
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if (data->soc == SOC_ARCH_EXYNOS5440) {
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@ -78,6 +78,7 @@ enum soc_type {
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* slightly across different exynos SOC's.
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* @triminfo_data: register containing 2 pont trimming data
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* @triminfo_ctrl: trim info controller register.
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* @triminfo_ctrl_count: the number of trim info controller register.
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* @tmu_ctrl: TMU main controller register.
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* @test_mux_addr_shift: shift bits of test mux address.
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* @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
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@ -112,8 +113,8 @@ enum soc_type {
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struct exynos_tmu_registers {
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u32 triminfo_data;
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u32 triminfo_ctrl;
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u32 triminfo_ctrl1;
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u32 triminfo_ctrl[MAX_TRIMINFO_CTRL_REG];
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u32 triminfo_ctrl_count;
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u32 tmu_ctrl;
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u32 test_mux_addr_shift;
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@ -200,6 +201,7 @@ struct exynos_tmu_registers {
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* @second_point_trim: temp value of the second point trimming
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* @default_temp_offset: default temperature offset in case of no trimming
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* @test_mux; information if SoC supports test MUX
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* @triminfo_reload: reload value to read TRIMINFO register
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* @cal_type: calibration type for temperature
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* @freq_clip_table: Table representing frequency reduction percentage.
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* @freq_tab_count: Count of the above table as frequency reduction may
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@ -230,6 +232,7 @@ struct exynos_tmu_platform_data {
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u8 second_point_trim;
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u8 default_temp_offset;
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u8 test_mux;
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u8 triminfo_reload[MAX_TRIMINFO_CTRL_REG];
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enum calibration_type cal_type;
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enum soc_type type;
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@ -169,7 +169,8 @@ struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_ctrl[0] = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_ctrl_count = 1,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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@ -231,6 +232,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.temp_level = 95, \
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}, \
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.freq_tab_count = 2, \
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.triminfo_reload[0] = EXYNOS_TRIMINFO_RELOAD_ENABLE, \
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.registers = &exynos4412_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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@ -51,6 +51,7 @@
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#define EXYNOS_THD_TEMP_FALL 0x54
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#define EXYNOS_EMUL_CON 0x80
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#define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
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#define EXYNOS_TRIMINFO_25_SHIFT 0
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#define EXYNOS_TRIMINFO_85_SHIFT 8
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#define EXYNOS_TMU_RISE_INT_MASK 0x111
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