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[ARM] 3226/1: IXP4xx runtime expansion bus window size configuration

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Patch from Deepak Saxena

The expansion bus on the IXP46x NPU can be configured for either 32MiB or
16MiB windows and changing the configuration causes the base address for
each chip select for each region to change. Because of this, we cannot
hardcode the physical base as we currently do. This patch checks the
expansion bus configuration registers at runtime to determine the
appropriate window size. Note that this requires that the bootloader
already configured the device sizes appropriately, but I feel that is
valid assumption to make as the bootloader must configure and access
the flash window, the output display (LCD, LEDs, etc) window, and
other expansion bus devices.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Deepak Saxena 2006-01-05 20:59:29 +00:00 committed by Russell King
parent 2b9ac7c15c
commit 54e269ead6
11 changed files with 52 additions and 45 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/mach-ixp4xx/common.c
View File

@ -332,11 +332,27 @@ static struct platform_device *ixp46x_devices[] __initdata = {
&ixp46x_i2c_controller
};
unsigned long ixp4xx_exp_bus_size;
void __init ixp4xx_sys_init(void)
{
ixp4xx_exp_bus_size = SZ_16M;
if (cpu_is_ixp46x()) {
int region;
platform_add_devices(ixp46x_devices,
ARRAY_SIZE(ixp46x_devices));
for (region = 0; region < 7; region++) {
if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
ixp4xx_exp_bus_size = SZ_32M;
break;
}
}
}
printk("IXP4xx: Using %uMiB expansion bus window size\n",
ixp4xx_exp_bus_size >> 20);
}

10
arch/arm/mach-ixp4xx/coyote-setup.c
View File

@ -14,6 +14,7 @@
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/slab.h>
#include <asm/types.h>
#include <asm/setup.h>
@ -30,8 +31,6 @@ static struct flash_platform_data coyote_flash_data = {
};
static struct resource coyote_flash_resource = {
.start = COYOTE_FLASH_BASE,
.end = COYOTE_FLASH_BASE + COYOTE_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
};
@ -81,6 +80,11 @@ static struct platform_device *coyote_devices[] __initdata = {
static void __init coyote_init(void)
{
ixp4xx_sys_init();
coyote_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
coyote_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
@ -91,8 +95,6 @@ static void __init coyote_init(void)
coyote_uart_data[0].irq = IRQ_IXP4XX_UART1;
}
ixp4xx_sys_init();
platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
}

15
arch/arm/mach-ixp4xx/gtwx5715-setup.c
View File

@ -27,6 +27,7 @@
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/slab.h>
#include <asm/types.h>
#include <asm/setup.h>
@ -106,11 +107,9 @@ static struct flash_platform_data gtwx5715_flash_data = {
.width = 2,
};
static struct resource gtwx5715_flash_resource = {
.start = GTWX5715_FLASH_BASE,
.end = GTWX5715_FLASH_BASE + GTWX5715_FLASH_SIZE - 1,
static struct gtw5715_flash_resource = {
.flags = IORESOURCE_MEM,
};
}
static struct platform_device gtwx5715_flash = {
.name = "IXP4XX-Flash",
@ -129,6 +128,14 @@ static struct platform_device *gtwx5715_devices[] __initdata = {
static void __init gtwx5715_init(void)
{
ixp4xx_sys_init();
if (!flash_resource)
printk(KERN_ERR "Could not allocate flash resource\n");
gtwx5715_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
gtwx5715_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1;
platform_add_devices(gtwx5715_devices, ARRAY_SIZE(gtwx5715_devices));
}

13
arch/arm/mach-ixp4xx/ixdp425-setup.c
View File

@ -14,6 +14,7 @@
#include <linux/serial.h>
#include <linux/tty.h>
#include <linux/serial_8250.h>
#include <linux/slab.h>
#include <asm/types.h>
#include <asm/setup.h>
@ -30,8 +31,6 @@ static struct flash_platform_data ixdp425_flash_data = {
};
static struct resource ixdp425_flash_resource = {
.start = IXDP425_FLASH_BASE,
.end = IXDP425_FLASH_BASE + IXDP425_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
};
@ -108,17 +107,13 @@ static struct platform_device *ixdp425_devices[] __initdata = {
&ixdp425_uart
};
static void __init ixdp425_init(void)
{
ixp4xx_sys_init();
/*
* IXP465 has 32MB window
*/
if (machine_is_ixdp465()) {
ixdp425_flash_resource.end += IXDP425_FLASH_SIZE;
}
ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
ixdp425_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
}

6
arch/arm/mach-ixp4xx/nas100d-setup.c
View File

@ -26,8 +26,6 @@ static struct flash_platform_data nas100d_flash_data = {
};
static struct resource nas100d_flash_resource = {
.start = NAS100D_FLASH_BASE,
.end = NAS100D_FLASH_BASE + NAS100D_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
@ -115,6 +113,10 @@ static void __init nas100d_init(void)
{
ixp4xx_sys_init();
nas100d_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
nas100d_flash_resource.end =
IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
pm_power_off = nas100d_power_off;
platform_add_devices(nas100d_devices, ARRAY_SIZE(nas100d_devices));

5
include/asm-arm/arch-ixp4xx/coyote.h
View File

@ -16,9 +16,6 @@
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define COYOTE_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define COYOTE_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE * 2
/* PCI controller GPIO to IRQ pin mappings */
#define COYOTE_PCI_SLOT0_PIN 6
#define COYOTE_PCI_SLOT1_PIN 11
@ -26,7 +23,7 @@
#define COYOTE_PCI_SLOT0_DEVID 14
#define COYOTE_PCI_SLOT1_DEVID 15
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_CS3_BASE_PHYS
#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
#define COYOTE_IDE_REGION_SIZE 0x1000

4
include/asm-arm/arch-ixp4xx/gtwx5715.h
View File

@ -57,10 +57,6 @@
#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
#define GTWX5715_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define GTWX5715_FLASH_SIZE (0x00800000)
/* PCI controller GPIO to IRQ pin mappings
INTA INTB

3
include/asm-arm/arch-ixp4xx/ixdp425.h
View File

@ -16,9 +16,6 @@
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define IXDP425_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define IXDP425_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
#define IXDP425_SDA_PIN 7
#define IXDP425_SCL_PIN 6

3
include/asm-arm/arch-ixp4xx/nas100d.h
View File

@ -19,9 +19,6 @@
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define NAS100D_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define NAS100D_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
#define NAS100D_SDA_PIN 6
#define NAS100D_SCL_PIN 5

3
include/asm-arm/arch-ixp4xx/nslu2.h
View File

@ -18,9 +18,6 @@
#error "Do not include this directly, instead #include <asm/hardware.h>"
#endif
#define NSLU2_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
#define NSLU2_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
#define NSLU2_SDA_PIN 7
#define NSLU2_SCL_PIN 6

19
include/asm-arm/arch-ixp4xx/platform.h
View File

@ -26,16 +26,17 @@
*/
#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
#define IXP4XX_EXP_BUS_CSX_REGION_SIZE (0x01000000)
/*
* The expansion bus on the IXP4xx can be configured for either 16 or
* 32MB windows and the CS offset for each region changes based on the
* current configuration. This means that we cannot simply hardcode
* each offset. ixp4xx_sys_init() looks at the expansion bus configuration
* as setup by the bootloader to determine our window size.
*/
extern unsigned long ixp4xx_exp_bus_size;
#define IXP4XX_EXP_BUS_CS0_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x00000000)
#define IXP4XX_EXP_BUS_CS1_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x01000000)
#define IXP4XX_EXP_BUS_CS2_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x02000000)
#define IXP4XX_EXP_BUS_CS3_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x03000000)
#define IXP4XX_EXP_BUS_CS4_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x04000000)
#define IXP4XX_EXP_BUS_CS5_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x05000000)
#define IXP4XX_EXP_BUS_CS6_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x06000000)
#define IXP4XX_EXP_BUS_CS7_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x07000000)
#define IXP4XX_EXP_BUS_BASE(region)\
(IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size))
#define IXP4XX_FLASH_WRITABLE (0x2)
#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)