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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

Browse Source 
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (60 commits)
  Blackfin arch: make sure we include the fix for SPORT hysteresis when reprogramming clocks
  Blackfin arch: Fix bogus str_ident check in gpio code
  Blackfin arch: AD7879 Touchscreen driver
  Blackfin arch: introducing bfin_addr_dcachable
  Blackfin arch: fix a typo in comments
  Blackfin arch: Remove useless head file
  Blackfin arch: make sure L2 start and length are always defined (fixes building on BF542)
  Blackfin arch: use the Blackfin on-chip ROM to do software reset when possible
  Blackfin arch: update anomaly headers to match the latest sheet
  Blackfin arch: bfin_reset() is an internal reboot function ... everyone should go through machine_restart()
  Blackfin arch: print out error/warning if you are running on the incorrect CPU type
  Blackfin arch: remove non-bf54x ifdef logic since this file is only compiled on bf54x parts
  Blackfin arch: update board defconfigs
  Blackfin arch: Add optional verbose debug
  Blackfin arch: emulate a TTY over the EMUDAT/JTAG interface
  Blackfin arch: have is_user_addr_valid() check for overflows (like when address is -1)
  Blackfin arch: ptrace - fix off-by-one check on end of memory regions
  Blackfin arch: Enable framebuffer support for the BF526-EZkit TFT LCD display
  Blackfin arch: flash memory map and dm9000 resources updating
  Blackfin arch: early prink code still use uart core console functions to parse and set configure option string
  ...
This commit is contained in:
Linus Torvalds 2008-10-13 10:08:43 -07:00
commit 54cebc68c8
66 changed files with 4505 additions and 1021 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

155
Documentation/blackfin/kgdb.txt
View File

@ -1,155 +0,0 @@
A Simple Guide to Configure KGDB
Sonic Zhang <sonic.zhang@analog.com>
Aug. 24th 2006
This KGDB patch enables the kernel developer to do source level debugging on
the kernel for the Blackfin architecture. The debugging works over either the
ethernet interface or one of the uarts. Both software breakpoints and
hardware breakpoints are supported in this version.
http://docs.blackfin.uclinux.org/doku.php?id=kgdb
2 known issues:
1. This bug:
http://blackfin.uclinux.org/tracker/index.php?func=detail&aid=544&group_id=18&atid=145
The GDB client for Blackfin uClinux causes incorrect values of local
variables to be displayed when the user breaks the running of kernel in GDB.
2. Because of a hardware bug in Blackfin 533 v1.0.3:
05000067 - Watchpoints (Hardware Breakpoints) are not supported
Hardware breakpoints cannot be set properly.
Debug over Ethernet:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over (Ethernet)". Add "kgdboe=@target-IP/,@host-IP/" to
the option "Compiled-in Kernel Boot Parameter" under "Kernel hacking".
4. Connect minicom to the serial port and boot the kernel image.
5. Configure the IP "/> ifconfig eth0 target-IP"
6. Start GDB client "bfin-elf-gdb vmlinux".
7. Connect to the target "(gdb) target remote udp:target-IP:6443".
8. Set software breakpoint "(gdb) break sys_open".
9. Continue "(gdb) c".
10. Run ls in the target console "/> ls".
11. Breakpoint hits. "Breakpoint 1: sys_open(..."
12. Display local variables and function paramters.
(*) This operation gives wrong results, see known issue 1.
13. Single stepping "(gdb) si".
14. Remove breakpoint 1. "(gdb) del 1"
15. Set hardware breakpoint "(gdb) hbreak sys_open".
16. Continue "(gdb) c".
17. Run ls in the target console "/> ls".
18. Hardware breakpoint hits. "Breakpoint 1: sys_open(...".
(*) This hardware breakpoint will not be hit, see known issue 2.
19. Continue "(gdb) c".
20. Interrupt the target in GDB "Ctrl+C".
21. Detach from the target "(gdb) detach".
22. Exit GDB "(gdb) quit".
Debug over the UART:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over (UART)". Set "KGDB: UART port number" to be
a different one from the console. Don't forget to change the mode of
blackfin serial driver to PIO. Otherwise kgdb works incorrectly on UART.
4. If you want connect to kgdb when the kernel boots, enable
"KGDB: Wait for gdb connection early"
5. Compile kernel.
6. Connect minicom to the serial port of the console and boot the kernel image.
7. Start GDB client "bfin-elf-gdb vmlinux".
8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
9. Connect to the target on the second serial port "(gdb) target remote /dev/ttyS1".
10. Set software breakpoint "(gdb) break sys_open".
11. Continue "(gdb) c".
12. Run ls in the target console "/> ls".
13. A breakpoint is hit. "Breakpoint 1: sys_open(..."
14. All other operations are the same as that in KGDB over Ethernet.
Debug over the same UART as console:
1. Compile and install the cross platform version of gdb for blackfin, which
can be found at $(BINROOT)/bfin-elf-gdb.
2. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
"Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
With this selected, option "Full Symbolic/Source Debugging support" and
"Compile the kernel with frame pointers" are also selected.
3. Select option "KGDB: connect over UART". Set "KGDB: UART port number" to console.
Don't forget to change the mode of blackfin serial driver to PIO.
Otherwise kgdb works incorrectly on UART.
4. If you want connect to kgdb when the kernel boots, enable
"KGDB: Wait for gdb connection early"
5. Connect minicom to the serial port and boot the kernel image.
6. (Optional) Ask target to wait for gdb connection by entering Ctrl+A. In minicom, you should enter Ctrl+A+A.
7. Start GDB client "bfin-elf-gdb vmlinux".
8. Set the baud rate in GDB "(gdb) set remotebaud 57600".
9. Connect to the target "(gdb) target remote /dev/ttyS0".
10. Set software breakpoint "(gdb) break sys_open".
11. Continue "(gdb) c". Then enter Ctrl+C twice to stop GDB connection.
12. Run ls in the target console "/> ls". Dummy string can be seen on the console.
13. Then connect the gdb to target again. "(gdb) target remote /dev/ttyS0".
Now you will find a breakpoint is hit. "Breakpoint 1: sys_open(..."
14. All other operations are the same as that in KGDB over Ethernet. The only
difference is that after continue command in GDB, please stop GDB
connection by 2 "Ctrl+C"s and connect again after breakpoints are hit or
Ctrl+A is entered.

75
arch/blackfin/Kconfig
View File

@ -162,16 +162,28 @@ config BF549
config BF561
bool "BF561"
help
Not Supported Yet - Work in progress - BF561 Processor Support.
BF561 Processor Support.
endchoice
config BF_REV_MIN
int
default 0 if (BF52x || BF54x)
default 2 if (BF537 || BF536 || BF534)
default 3 if (BF561 ||BF533 || BF532 || BF531)
config BF_REV_MAX
int
default 2 if (BF52x || BF54x)
default 3 if (BF537 || BF536 || BF534)
default 5 if (BF561)
default 6 if (BF533 || BF532 || BF531)
choice
prompt "Silicon Rev"
default BF_REV_0_1 if BF527
default BF_REV_0_2 if BF537
default BF_REV_0_3 if BF533
default BF_REV_0_0 if BF549
default BF_REV_0_1 if (BF52x || BF54x)
default BF_REV_0_2 if (BF534 || BF536 || BF537)
default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
config BF_REV_0_0
bool "0.0"
@ -183,7 +195,7 @@ config BF_REV_0_1
config BF_REV_0_2
bool "0.2"
depends on (BF537 || BF536 || BF534)
depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
config BF_REV_0_3
bool "0.3"
@ -197,6 +209,10 @@ config BF_REV_0_5
bool "0.5"
depends on (BF561 || BF533 || BF532 || BF531)
config BF_REV_0_6
bool "0.6"
depends on (BF533 || BF532 || BF531)
config BF_REV_ANY
bool "any"
@ -249,7 +265,7 @@ config MEM_MT48LC8M32B2B5_7
config MEM_MT48LC32M16A2TG_75
bool
depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP)
depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
default y
source "arch/blackfin/mach-bf527/Kconfig"
@ -286,13 +302,20 @@ config BOOT_LOAD
memory region is used to capture NULL pointer references as well
as some core kernel functions.
config ROM_BASE
hex "Kernel ROM Base"
default "0x20040000"
range 0x20000000 0x20400000 if !(BF54x || BF561)
range 0x20000000 0x30000000 if (BF54x || BF561)
help
comment "Clock/PLL Setup"
config CLKIN_HZ
int "Frequency of the crystal on the board in Hz"
default "11059200" if BFIN533_STAMP
default "27000000" if BFIN533_EZKIT
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP)
default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
default "30000000" if BFIN561_EZKIT
default "24576000" if PNAV10
default "10000000" if BFIN532_IP0X
@ -332,7 +355,7 @@ config VCO_MULT
default "22" if BFIN533_BLUETECHNIX_CM
default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
default "20" if BFIN561_EZKIT
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP)
default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
@ -368,14 +391,6 @@ config SCLK_DIV
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
config MAX_MEM_SIZE
int "Max SDRAM Memory Size in MBytes"
depends on !MPU
default 512
help
This is the max memory size that the kernel will create CPLB
tables for. Your system will not be able to handle any more.
choice
prompt "DDR SDRAM Chip Type"
depends on BFIN_KERNEL_CLOCK
@ -389,6 +404,14 @@ config MEM_MT46V32M16_5B
bool "MT46V32M16_5B"
endchoice
config MAX_MEM_SIZE
int "Max SDRAM Memory Size in MBytes"
depends on !MPU
default 512
help
This is the max memory size that the kernel will create CPLB
tables for. Your system will not be able to handle any more.
#
# Max & Min Speeds for various Chips
#
@ -455,8 +478,6 @@ config CYCLES_CLOCKSOURCE
source kernel/time/Kconfig
comment "Memory Setup"
comment "Misc"
choice
@ -622,6 +643,15 @@ config CPLB_SWITCH_TAB_L1
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
config APP_STACK_L1
bool "Support locating application stack in L1 Scratch Memory"
default y
help
If enabled the application stack can be located in L1
scratch memory (less latency).
Currently only works with FLAT binaries.
comment "Speed Optimizations"
config BFIN_INS_LOWOVERHEAD
bool "ins[bwl] low overhead, higher interrupt latency"
@ -755,6 +785,13 @@ config BFIN_WT
endchoice
config BFIN_L2_CACHEABLE
bool "Cache L2 SRAM"
depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
default n
help
Select to make L2 SRAM cacheable in L1 data and instruction cache.
config MPU
bool "Enable the memory protection unit (EXPERIMENTAL)"
default n

55
arch/blackfin/Kconfig.debug
View File

@ -2,6 +2,22 @@ menu "Kernel hacking"
source "lib/Kconfig.debug"
config HAVE_ARCH_KGDB
def_bool y
config DEBUG_VERBOSE
bool "Verbose fault messages"
default y
select PRINTK
help
When a program crashes due to an exception, or the kernel detects
an internal error, the kernel can print a not so brief message
explaining what the problem was. This debugging information is
useful to developers and kernel hackers when tracking down problems,
but mostly meaningless to other people. This is always helpful for
debugging but serves no purpose on a production system.
Most people should say N here.
config DEBUG_MMRS
bool "Generate Blackfin MMR tree"
select DEBUG_FS
@ -22,6 +38,44 @@ config DEBUG_HWERR
hardware error interrupts and need to know where they are coming
from.
config DEBUG_DOUBLEFAULT
bool "Debug Double Faults"
default n
help
If an exception is caused while executing code within the exception
handler, the NMI handler, the reset vector, or in emulator mode,
a double fault occurs. On the Blackfin, this is a unrecoverable
event. You have two options:
- RESET exactly when double fault occurs. The excepting
instruction address is stored in RETX, where the next kernel
boot will print it out.
- Print debug message. This is much more error prone, although
easier to handle. It is error prone since:
- The excepting instruction is not committed.
- All writebacks from the instruction are prevented.
- The generated exception is not taken.
- The EXCAUSE field is updated with an unrecoverable event
The only way to check this is to see if EXCAUSE contains the
unrecoverable event value at every exception return. By selecting
this option, you are skipping over the faulting instruction, and
hoping things stay together enough to print out a debug message.
This does add a little kernel code, but is the only method to debug
double faults - if unsure say "Y"
choice
prompt "Double Fault Failure Method"
default DEBUG_DOUBLEFAULT_PRINT
depends on DEBUG_DOUBLEFAULT
config DEBUG_DOUBLEFAULT_PRINT
bool "Print"
config DEBUG_DOUBLEFAULT_RESET
bool "Reset"
endchoice
config DEBUG_ICACHE_CHECK
bool "Check Instruction cache coherency"
depends on DEBUG_KERNEL
@ -143,6 +197,7 @@ config DEBUG_BFIN_NO_KERN_HWTRACE
config EARLY_PRINTK
bool "Early printk"
default n
select SERIAL_CORE_CONSOLE
help
This option enables special console drivers which allow the kernel
to print messages very early in the bootup process.

1
arch/blackfin/Makefile
View File

@ -67,6 +67,7 @@ rev-$(CONFIG_BF_REV_0_2) := 0.2
rev-$(CONFIG_BF_REV_0_3) := 0.3
rev-$(CONFIG_BF_REV_0_4) := 0.4
rev-$(CONFIG_BF_REV_0_5) := 0.5
rev-$(CONFIG_BF_REV_0_6) := 0.6
rev-$(CONFIG_BF_REV_NONE) := none
rev-$(CONFIG_BF_REV_ANY) := any

1427
arch/blackfin/configs/BF526-EZBRD_defconfig Normal file
View File

File diff suppressed because it is too large Load Diff

36
arch/blackfin/configs/H8606_defconfig
View File

@ -1,6 +1,6 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.22.12
# Linux kernel version: 2.6.22.14
#
# CONFIG_MMU is not set
# CONFIG_FPU is not set
@ -192,7 +192,7 @@ CONFIG_CLKIN_HZ=25000000
# CONFIG_BFIN_KERNEL_CLOCK is not set
CONFIG_MAX_VCO_HZ=400000000
CONFIG_MIN_VCO_HZ=50000000
CONFIG_MAX_SCLK_HZ=133000000
CONFIG_MAX_SCLK_HZ=133333333
CONFIG_MIN_SCLK_HZ=27000000
#
@ -516,7 +516,7 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
#
# CONFIG_MTD_DATAFLASH is not set
CONFIG_MTD_M25P80=y
CONFIG_M25PXX_USE_FAST_READ=y
# CONFIG_M25PXX_USE_FAST_READ is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
@ -635,25 +635,25 @@ CONFIG_INPUT=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
CONFIG_INPUT_EVDEV=m
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_UINPUT is not set
# CONFIG_BF53X_PFBUTTONS is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
@ -681,7 +681,15 @@ CONFIG_BFIN_TIMER_LATENCY=y
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
CONFIG_SERIAL_8250=y
# CONFIG_SERIAL_8250_CONSOLE is not set
CONFIG_SERIAL_8250_NR_UARTS=4
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
# CONFIG_SERIAL_8250_MANY_PORTS is not set
CONFIG_SERIAL_8250_SHARE_IRQ=y
# CONFIG_SERIAL_8250_DETECT_IRQ is not set
# CONFIG_SERIAL_8250_RSA is not set
#
# Non-8250 serial port support

5
arch/blackfin/include/asm/bfin-global.h
View File

@ -63,7 +63,6 @@ extern void bfin_dcache_init(void);
extern void init_exception_vectors(void);
extern void program_IAR(void);
extern void bfin_reset(void);
extern asmlinkage void lower_to_irq14(void);
extern asmlinkage void bfin_return_from_exception(void);
extern asmlinkage void evt14_softirq(void);
@ -92,6 +91,8 @@ extern int sram_free(const void*);
extern void *sram_alloc_with_lsl(size_t, unsigned long);
extern int sram_free_with_lsl(const void*);
extern void *isram_memcpy(void *dest, const void *src, size_t n);
extern const char bfin_board_name[];
extern unsigned long bfin_sic_iwr[];
@ -104,7 +105,7 @@ extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
_stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
_ebss_l2[], _l2_lma_start[];
/* only used when CONFIG_MTD_UCLINUX */
/* only used when MTD_UCLINUX */
extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
#ifdef CONFIG_BFIN_ICACHE_LOCK

85
arch/blackfin/include/asm/bfrom.h Normal file
View File

@ -0,0 +1,85 @@
/* Blackfin on-chip ROM API
*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFROM_H__
#define __BFROM_H__
#include <linux/types.h>
/* Possible syscontrol action flags */
#define SYSCTRL_READ 0x00000000 /* read registers */
#define SYSCTRL_WRITE 0x00000001 /* write registers */
#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */
#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */
#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */
#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */
#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */
#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */
#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */
#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */
#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */
#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */
#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */
typedef struct ADI_SYSCTRL_VALUES {
uint16_t uwVrCtl;
uint16_t uwPllCtl;
uint16_t uwPllDiv;
uint16_t uwPllLockCnt;
uint16_t uwPllStat;
} ADI_SYSCTRL_VALUES;
static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)0xEF000038;
/* We need a dedicated function since we need to screw with the stack pointer
* when resetting. The on-chip ROM will save/restore registers on the stack
* when doing a system reset, so the stack cannot be outside of the chip.
*/
__attribute__((__noreturn__))
static inline void bfrom_SoftReset(void *new_stack)
{
while (1)
__asm__ __volatile__(
"sp = %[stack];"
"jump (%[bfrom_syscontrol]);"
: : [bfrom_syscontrol] "p"(bfrom_SysControl),
"q0"(SYSCTRL_SOFTRESET),
"q1"(0),
"q2"(NULL),
[stack] "p"(new_stack)
);
}
/* OTP Functions */
static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)0xEF000018;
static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001A;
static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)0xEF00001C;
/* otp command: defines for "command" */
#define OTP_INIT 0x00000001
#define OTP_CLOSE 0x00000002
/* otp read/write: defines for "flags" */
#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */
#define OTP_UPPER_HALF 0x00000001
#define OTP_NO_ECC 0x00000010 /* do not use ECC */
#define OTP_LOCK 0x00000020 /* sets page protection bit for page */
#define OTP_CHECK_FOR_PREV_WRITE 0x00000080
/* Return values for all functions */
#define OTP_SUCCESS 0x00000000
#define OTP_MASTER_ERROR 0x001
#define OTP_WRITE_ERROR 0x003
#define OTP_READ_ERROR 0x005
#define OTP_ACC_VIO_ERROR 0x009
#define OTP_DATA_MULT_ERROR 0x011
#define OTP_ECC_MULT_ERROR 0x021
#define OTP_PREV_WR_ERROR 0x041
#define OTP_DATA_SB_WARN 0x100
#define OTP_ECC_SB_WARN 0x200
#endif

2
arch/blackfin/include/asm/cacheflush.h
View File

@ -30,8 +30,6 @@
#ifndef _BLACKFIN_CACHEFLUSH_H
#define _BLACKFIN_CACHEFLUSH_H
#include <asm/cplb.h>
extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
extern void blackfin_icache_flush_range(unsigned int, unsigned int);
extern void blackfin_dcache_flush_range(unsigned int, unsigned int);

8
arch/blackfin/include/asm/cplb.h
View File

@ -55,7 +55,13 @@
#endif
#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
#define L2_MEMORY (CPLB_COMMON)
#ifdef CONFIG_BFIN_L2_CACHEABLE
#define L2_IMEMORY (SDRAM_IGENERIC)
#define L2_DMEMORY (SDRAM_DGENERIC)
#else
#define L2_IMEMORY (CPLB_COMMON)
#define L2_DMEMORY (CPLB_COMMON)
#endif
#define SDRAM_DNON_CHBL (CPLB_COMMON)
#define SDRAM_EBIU (CPLB_COMMON)
#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)

16
arch/blackfin/include/asm/cplbinit.h
View File

@ -90,6 +90,20 @@ extern u_long dpdt_swapcount_table[];
extern unsigned long reserved_mem_dcache_on;
extern unsigned long reserved_mem_icache_on;
extern void generate_cpl_tables(void);
extern void generate_cplb_tables(void);
static inline int bfin_addr_dcachable(unsigned long addr)
{
#ifdef CONFIG_BFIN_DCACHE
if (addr < (_ramend - DMA_UNCACHED_REGION))
return 1;
#endif
if (reserved_mem_dcache_on &&
addr >= _ramend && addr < physical_mem_end)
return 1;
return 0;
}
#endif

6
arch/blackfin/include/asm/cpumask.h
View File

@ -1,6 +0,0 @@
#ifndef _ASM_BLACKFIN_CPUMASK_H
#define _ASM_BLACKFIN_CPUMASK_H
#include <asm-generic/cpumask.h>
#endif /* _ASM_BLACKFIN_CPUMASK_H */

11
arch/blackfin/include/asm/dma-mapping.h
View File

@ -80,4 +80,15 @@ extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction direction);
static inline void dma_sync_single_for_cpu(struct device *dev,
dma_addr_t handle, size_t size,
enum dma_data_direction dir)
{
}
static inline void dma_sync_single_for_device(struct device *dev,
dma_addr_t handle, size_t size,
enum dma_data_direction dir)
{
}
#endif /* _BLACKFIN_DMA_MAPPING_H */

21
arch/blackfin/include/asm/kgdb.h
View File

@ -124,9 +124,16 @@ enum regnames {
/* Number of bytes of registers. */
#define NUMREGBYTES BFIN_NUM_REGS*4
#define BREAKPOINT() asm(" EXCPT 2;");
#define BREAK_INSTR_SIZE 2
#define HW_BREAKPOINT_NUM 6
static inline void arch_kgdb_breakpoint(void)
{
asm(" EXCPT 2;");
}
#define BREAK_INSTR_SIZE 2
#define CACHE_FLUSH_IS_SAFE 1
#define HW_INST_WATCHPOINT_NUM 6
#define HW_WATCHPOINT_NUM 8
#define TYPE_INST_WATCHPOINT 0
#define TYPE_DATA_WATCHPOINT 1
/* Instruction watchpoint address control register bits mask */
#define WPPWR 0x1
@ -163,10 +170,11 @@ enum regnames {
#define WPDAEN1 0x8
#define WPDCNTEN0 0x10
#define WPDCNTEN1 0x20
#define WPDSRC0 0xc0
#define WPDACC0 0x300
#define WPDACC0_OFFSET 8
#define WPDSRC1 0xc00
#define WPDACC1 0x3000
#define WPDACC1_OFFSET 12
/* Watchpoint status register bits mask */
#define STATIA0 0x1
@ -178,7 +186,4 @@ enum regnames {
#define STATDA0 0x40
#define STATDA1 0x80
extern void kgdb_print(const char *fmt, ...);
extern void init_kgdb_uart(void);
#endif

79
arch/blackfin/include/asm/mmu_context.h
View File

@ -45,49 +45,12 @@ extern unsigned long l1_stack_len;
extern int l1sram_free(const void*);
extern void *l1sram_alloc_max(void*);
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
/* Called when creating a new context during fork() or execve(). */
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifdef CONFIG_MPU
unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
mm->context.page_rwx_mask = (unsigned long *)p;
memset(mm->context.page_rwx_mask, 0,
page_mask_nelts * 3 * sizeof(long));
#endif
return 0;
}
static inline void free_l1stack(void)
{
nr_l1stack_tasks--;
if (nr_l1stack_tasks == 0)
l1sram_free(l1_stack_base);
}
static inline void destroy_context(struct mm_struct *mm)
{
struct sram_list_struct *tmp;
if (current_l1_stack_save == mm->context.l1_stack_save)
current_l1_stack_save = NULL;
if (mm->context.l1_stack_save)
free_l1stack();
while ((tmp = mm->context.sram_list)) {
mm->context.sram_list = tmp->next;
sram_free(tmp->addr);
kfree(tmp);
}
#ifdef CONFIG_MPU
if (current_rwx_mask == mm->context.page_rwx_mask)
current_rwx_mask = NULL;
free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
#endif
}
static inline unsigned long
alloc_l1stack(unsigned long length, unsigned long *stack_base)
@ -134,6 +97,7 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
}
#endif
#ifdef CONFIG_APP_STACK_L1
/* L1 stack switching. */
if (!next_mm->context.l1_stack_save)
return;
@ -144,6 +108,7 @@ static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_m
}
current_l1_stack_save = next_mm->context.l1_stack_save;
memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
#endif
}
#ifdef CONFIG_MPU
@ -180,4 +145,44 @@ static inline void update_protections(struct mm_struct *mm)
}
#endif
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
/* Called when creating a new context during fork() or execve(). */
static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifdef CONFIG_MPU
unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
mm->context.page_rwx_mask = (unsigned long *)p;
memset(mm->context.page_rwx_mask, 0,
page_mask_nelts * 3 * sizeof(long));
#endif
return 0;
}
static inline void destroy_context(struct mm_struct *mm)
{
struct sram_list_struct *tmp;
#ifdef CONFIG_APP_STACK_L1
if (current_l1_stack_save == mm->context.l1_stack_save)
current_l1_stack_save = 0;
if (mm->context.l1_stack_save)
free_l1stack();
#endif
while ((tmp = mm->context.sram_list)) {
mm->context.sram_list = tmp->next;
sram_free(tmp->addr);
kfree(tmp);
}
#ifdef CONFIG_MPU
if (current_rwx_mask == mm->context.page_rwx_mask)
current_rwx_mask = NULL;
free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
#endif
}
#endif

6
arch/blackfin/include/asm/processor.h
View File

@ -134,6 +134,12 @@ static inline uint32_t __pure bfin_revid(void)
return revid;
}
static inline uint16_t __pure bfin_cpuid(void)
{
return (bfin_read_CHIPID() & CHIPID_FAMILY) >> 12;
}
static inline uint32_t __pure bfin_compiled_revid(void)
{
#if defined(CONFIG_BF_REV_0_0)

2
arch/blackfin/include/asm/ptrace.h
View File

@ -158,6 +158,8 @@ extern void show_regs(struct pt_regs *);
#define PT_SEQSTAT 8
#define PT_IPEND 4
#define PT_ORIG_R0 208
#define PT_ORIG_P0 212
#define PT_SYSCFG 216
#define PT_TEXT_ADDR 220
#define PT_TEXT_END_ADDR 224

5
arch/blackfin/include/asm/traps.h
View File

@ -59,6 +59,9 @@
level " or a 16-bit register is accessed with a 32-bit instruction.\n"
#define HWC_x3(level) \
"External Memory Addressing Error\n"
#define EXC_0x04(level) \
"Unimplmented exception occured\n" \
level " - Maybe you forgot to install a custom exception handler?\n"
#define HWC_x12(level) \
"Performance Monitor Overflow\n"
#define HWC_x18(level) \
@ -84,7 +87,7 @@
level " a particular processor implementation.\n"
#define EXC_0x22(level) \
"Illegal instruction combination\n" \
level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
level " - See section for multi-issue rules in the Blackfin\n" \
level " Processor Instruction Set Reference.\n"
#define EXC_0x23(level) \
"Data access CPLB protection violation\n" \

1
arch/blackfin/kernel/asm-offsets.c
View File

@ -60,6 +60,7 @@ int main(void)
DEFINE(KERNEL_STACK_SIZE, THREAD_SIZE);
/* offsets into the pt_regs */
DEFINE(PT_ORIG_R0, offsetof(struct pt_regs, orig_r0));
DEFINE(PT_ORIG_P0, offsetof(struct pt_regs, orig_p0));
DEFINE(PT_ORIG_PC, offsetof(struct pt_regs, orig_pc));
DEFINE(PT_R0, offsetof(struct pt_regs, r0));

9
arch/blackfin/kernel/bfin_gpio.c
View File

@ -231,14 +231,14 @@ inline int check_gpio(unsigned gpio)
}
#endif
void gpio_error(unsigned gpio)
static void gpio_error(unsigned gpio)
{
printk(KERN_ERR "bfin-gpio: GPIO %d wasn't requested!\n", gpio);
}
static void set_label(unsigned short ident, const char *label)
{
if (label && str_ident) {
if (label) {
strncpy(str_ident[ident].name, label,
RESOURCE_LABEL_SIZE);
str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
@ -247,9 +247,6 @@ static void set_label(unsigned short ident, const char *label)
static char *get_label(unsigned short ident)
{
if (!str_ident)
return "UNKNOWN";
return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
}
@ -260,7 +257,7 @@ static int cmp_label(unsigned short ident, const char *label)
printk(KERN_ERR "Please provide none-null label\n");
}
if (label && str_ident)
if (label)
return strncmp(str_ident[ident].name,
label, strlen(label));
else

12
arch/blackfin/kernel/cplb-mpu/cplbinit.c
View File

@ -36,7 +36,7 @@ struct cplb_entry dcplb_tbl[MAX_CPLBS];
int first_switched_icplb, first_switched_dcplb;
int first_mask_dcplb;
void __init generate_cpl_tables(void)
void __init generate_cplb_tables(void)
{
int i_d, i_i;
unsigned long addr;
@ -83,8 +83,18 @@ void __init generate_cpl_tables(void)
dcplb_tbl[i_d].addr = L1_DATA_A_START;
dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
#endif
#if L1_CODE_LENGTH > 0
icplb_tbl[i_i].addr = L1_CODE_START;
icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
#endif
/* Cover L2 memory */
#if L2_LENGTH > 0
dcplb_tbl[i_d].addr = L2_START;
dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
icplb_tbl[i_i].addr = L2_START;
icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
#endif
first_mask_dcplb = i_d;
first_switched_dcplb = i_d + (1 << page_mask_order);

14
arch/blackfin/kernel/cplb-mpu/cplbmgr.c
View File

@ -322,9 +322,11 @@ int cplb_hdr(int seqstat, struct pt_regs *regs)
void flush_switched_cplbs(void)
{
int i;
unsigned long flags;
nr_cplb_flush++;
local_irq_save(flags);
disable_icplb();
for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
icplb_tbl[i].data = 0;
@ -338,6 +340,8 @@ void flush_switched_cplbs(void)
bfin_write32(DCPLB_DATA0 + i * 4, 0);
}
enable_dcplb();
local_irq_restore(flags);
}
void set_mask_dcplbs(unsigned long *masks)
@ -345,10 +349,15 @@ void set_mask_dcplbs(unsigned long *masks)
int i;
unsigned long addr = (unsigned long)masks;
unsigned long d_data;
current_rwx_mask = masks;
unsigned long flags;
if (!masks)
if (!masks) {
current_rwx_mask = masks;
return;
}
local_irq_save(flags);
current_rwx_mask = masks;
d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
#ifdef CONFIG_BFIN_DCACHE
@ -367,4 +376,5 @@ void set_mask_dcplbs(unsigned long *masks)
addr += PAGE_SIZE;
}
enable_dcplb();
local_irq_restore(flags);
}

6
arch/blackfin/kernel/cplb-nompu/cplbinit.c
View File

@ -168,8 +168,8 @@ static struct cplb_desc cplb_data[] = {
.end = L2_START + L2_LENGTH,
.psize = SIZE_1M,
.attr = SWITCH_T | I_CPLB | D_CPLB,
.i_conf = L2_MEMORY,
.d_conf = L2_MEMORY,
.i_conf = L2_IMEMORY,
.d_conf = L2_DMEMORY,
.valid = (L2_LENGTH > 0),
.name = "L2 Memory",
},
@ -308,7 +308,7 @@ __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
}
}
void __init generate_cpl_tables(void)
void __init generate_cplb_tables(void)
{
u16 i, j, process;

12
arch/blackfin/kernel/early_printk.c
View File

@ -35,6 +35,9 @@
extern struct console *bfin_earlyserial_init(unsigned int port,
unsigned int cflag);
#endif
#ifdef CONFIG_BFIN_JTAG_COMM
extern struct console *bfin_jc_early_init(void);
#endif
static struct console *early_console;
@ -142,6 +145,15 @@ int __init setup_early_printk(char *buf)
early_console = earlyserial_init(buf);
}
#endif
#ifdef CONFIG_BFIN_JTAG_COMM
/* Check for Blackfin JTAG */
if (!strncmp(buf, "jtag", 4)) {
buf += 4;
early_console = bfin_jc_early_init();
}
#endif
#ifdef CONFIG_FB
/* TODO: add framebuffer console support */
#endif

721
arch/blackfin/kernel/kgdb.c
View File

@ -1,32 +1,9 @@
/*
* File: arch/blackfin/kernel/kgdb.c
* Based on:
* Author: Sonic Zhang
* arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
*
* Created:
* Description:
* Copyright 2005-2008 Analog Devices Inc.
*
* Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
*
* Modified:
* Copyright 2005-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* Licensed under the GPL-2 or later.
*/
#include <linux/string.h>
@ -39,24 +16,29 @@
#include <linux/kgdb.h>
#include <linux/console.h>
#include <linux/init.h>
#include <linux/debugger.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <linux/uaccess.h>
#include <asm/system.h>
#include <asm/traps.h>
#include <asm/blackfin.h>
#include <asm/dma.h>
/* Put the error code here just in case the user cares. */
int gdb_bf533errcode;
int gdb_bfin_errcode;
/* Likewise, the vector number here (since GDB only gets the signal
number through the usual means, and that's not very specific). */
int gdb_bf533vector = -1;
int gdb_bfin_vector = -1;
#if KGDB_MAX_NO_CPUS != 8
#error change the definition of slavecpulocks
#endif
void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
#ifdef CONFIG_BFIN_WDT
# error "Please unselect blackfin watchdog driver before build KGDB."
#endif
void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{
gdb_regs[BFIN_R0] = regs->r0;
gdb_regs[BFIN_R1] = regs->r1;
@ -133,7 +115,7 @@ void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
}
void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs)
void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
{
regs->r0 = gdb_regs[BFIN_R0];
regs->r1 = gdb_regs[BFIN_R1];
@ -199,171 +181,208 @@ struct hw_breakpoint {
unsigned int dataacc:2;
unsigned short count;
unsigned int addr;
} breakinfo[HW_BREAKPOINT_NUM];
} breakinfo[HW_WATCHPOINT_NUM];
int kgdb_arch_init(void)
{
debugger_step = 0;
kgdb_remove_all_hw_break();
return 0;
}
int kgdb_set_hw_break(unsigned long addr)
int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
{
int breakno;
for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
if (!breakinfo[breakno].occupied) {
int bfin_type;
int dataacc = 0;
switch (type) {
case BP_HARDWARE_BREAKPOINT:
bfin_type = TYPE_INST_WATCHPOINT;
break;
case BP_WRITE_WATCHPOINT:
dataacc = 1;
bfin_type = TYPE_DATA_WATCHPOINT;
break;
case BP_READ_WATCHPOINT:
dataacc = 2;
bfin_type = TYPE_DATA_WATCHPOINT;
break;
case BP_ACCESS_WATCHPOINT:
dataacc = 3;
bfin_type = TYPE_DATA_WATCHPOINT;
break;
default:
return -ENOSPC;
}
/* Becasue hardware data watchpoint impelemented in current
* Blackfin can not trigger an exception event as the hardware
* instrction watchpoint does, we ignaore all data watch point here.
* They can be turned on easily after future blackfin design
* supports this feature.
*/
for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
if (bfin_type == breakinfo[breakno].type
&& !breakinfo[breakno].occupied) {
breakinfo[breakno].occupied = 1;
breakinfo[breakno].enabled = 1;
breakinfo[breakno].type = 1;
breakinfo[breakno].addr = addr;
breakinfo[breakno].dataacc = dataacc;
breakinfo[breakno].count = 0;
return 0;
}
return -ENOSPC;
}
int kgdb_remove_hw_break(unsigned long addr)
int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
{
int breakno;
for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
if (breakinfo[breakno].addr == addr)
memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint));
int bfin_type;
switch (type) {
case BP_HARDWARE_BREAKPOINT:
bfin_type = TYPE_INST_WATCHPOINT;
break;
case BP_WRITE_WATCHPOINT:
case BP_READ_WATCHPOINT:
case BP_ACCESS_WATCHPOINT:
bfin_type = TYPE_DATA_WATCHPOINT;
break;
default:
return 0;
}
for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
if (bfin_type == breakinfo[breakno].type
&& breakinfo[breakno].occupied
&& breakinfo[breakno].addr == addr) {
breakinfo[breakno].occupied = 0;
breakinfo[breakno].enabled = 0;
}
return 0;
}
void kgdb_remove_all_hw_break(void)
{
memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8);
}
/*
void kgdb_show_info(void)
{
printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n",
bfin_read_WPIA0(), bfin_read_WPIACNT0(),
bfin_read_WPIACTL(), bfin_read_WPSTAT());
}
*/
void kgdb_correct_hw_break(void)
void bfin_remove_all_hw_break(void)
{
int breakno;
int correctit;
uint32_t wpdactl = bfin_read_WPDACTL();
correctit = 0;
for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) {
if (breakinfo[breakno].type == 1) {
memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
for (; breakno < HW_WATCHPOINT_NUM; breakno++)
breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
}
void bfin_correct_hw_break(void)
{
int breakno;
unsigned int wpiactl = 0;
unsigned int wpdactl = 0;
int enable_wp = 0;
for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
if (breakinfo[breakno].enabled) {
enable_wp = 1;
switch (breakno) {
case 0:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) {
correctit = 1;
wpdactl &= ~(WPIREN01|EMUSW0);
wpdactl |= WPIAEN0|WPICNTEN0;
bfin_write_WPIA0(breakinfo[breakno].addr);
bfin_write_WPIACNT0(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) {
correctit = 1;
wpdactl &= ~WPIAEN0;
}
wpiactl |= WPIAEN0|WPICNTEN0;
bfin_write_WPIA0(breakinfo[breakno].addr);
bfin_write_WPIACNT0(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 1:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) {
correctit = 1;
wpdactl &= ~(WPIREN01|EMUSW1);
wpdactl |= WPIAEN1|WPICNTEN1;
bfin_write_WPIA1(breakinfo[breakno].addr);
bfin_write_WPIACNT1(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) {
correctit = 1;
wpdactl &= ~WPIAEN1;
}
wpiactl |= WPIAEN1|WPICNTEN1;
bfin_write_WPIA1(breakinfo[breakno].addr);
bfin_write_WPIACNT1(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 2:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) {
correctit = 1;
wpdactl &= ~(WPIREN23|EMUSW2);
wpdactl |= WPIAEN2|WPICNTEN2;
bfin_write_WPIA2(breakinfo[breakno].addr);
bfin_write_WPIACNT2(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) {
correctit = 1;
wpdactl &= ~WPIAEN2;
}
wpiactl |= WPIAEN2|WPICNTEN2;
bfin_write_WPIA2(breakinfo[breakno].addr);
bfin_write_WPIACNT2(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 3:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) {
correctit = 1;
wpdactl &= ~(WPIREN23|EMUSW3);
wpdactl |= WPIAEN3|WPICNTEN3;
bfin_write_WPIA3(breakinfo[breakno].addr);
bfin_write_WPIACNT3(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) {
correctit = 1;
wpdactl &= ~WPIAEN3;
}
wpiactl |= WPIAEN3|WPICNTEN3;
bfin_write_WPIA3(breakinfo[breakno].addr);
bfin_write_WPIACNT3(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 4:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) {
correctit = 1;
wpdactl &= ~(WPIREN45|EMUSW4);
wpdactl |= WPIAEN4|WPICNTEN4;
bfin_write_WPIA4(breakinfo[breakno].addr);
bfin_write_WPIACNT4(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) {
correctit = 1;
wpdactl &= ~WPIAEN4;
}
wpiactl |= WPIAEN4|WPICNTEN4;
bfin_write_WPIA4(breakinfo[breakno].addr);
bfin_write_WPIACNT4(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 5:
if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) {
correctit = 1;
wpdactl &= ~(WPIREN45|EMUSW5);
wpdactl |= WPIAEN5|WPICNTEN5;
bfin_write_WPIA5(breakinfo[breakno].addr);
bfin_write_WPIACNT5(breakinfo[breakno].skip);
} else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) {
correctit = 1;
wpdactl &= ~WPIAEN5;
}
wpiactl |= WPIAEN5|WPICNTEN5;
bfin_write_WPIA5(breakinfo[breakno].addr);
bfin_write_WPIACNT5(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 6:
wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
wpdactl |= breakinfo[breakno].dataacc
<< WPDACC0_OFFSET;
bfin_write_WPDA0(breakinfo[breakno].addr);
bfin_write_WPDACNT0(breakinfo[breakno].count
+ breakinfo->skip);
break;
case 7:
wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
wpdactl |= breakinfo[breakno].dataacc
<< WPDACC1_OFFSET;
bfin_write_WPDA1(breakinfo[breakno].addr);
bfin_write_WPDACNT1(breakinfo[breakno].count
+ breakinfo->skip);
break;
}
}
}
if (correctit) {
wpdactl &= ~WPAND;
wpdactl |= WPPWR;
/*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/
/* Should enable WPPWR bit first before set any other
* WPIACTL and WPDACTL bits */
if (enable_wp) {
bfin_write_WPIACTL(WPPWR);
CSYNC();
bfin_write_WPIACTL(wpiactl|WPPWR);
bfin_write_WPDACTL(wpdactl);
CSYNC();
/*kgdb_show_info();*/
}
}
void kgdb_disable_hw_debug(struct pt_regs *regs)
{
/* Disable hardware debugging while we are in kgdb */
bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1);
bfin_write_WPIACTL(0);
bfin_write_WPDACTL(0);
CSYNC();
}
void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code)
#ifdef CONFIG_SMP
void kgdb_passive_cpu_callback(void *info)
{
/* Master processor is completely in the debugger */
gdb_bf533vector = eVector;
gdb_bf533errcode = err_code;
kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
}
int kgdb_arch_handle_exception(int exceptionVector, int signo,
void kgdb_roundup_cpus(unsigned long flags)
{
smp_call_function(kgdb_passive_cpu_callback, NULL, 0, 0);
}
void kgdb_roundup_cpu(int cpu, unsigned long flags)
{
smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0, 0);
}
#endif
void kgdb_post_primary_code(struct pt_regs *regs, int eVector, int err_code)
{
/* Master processor is completely in the debugger */
gdb_bfin_vector = eVector;
gdb_bfin_errcode = err_code;
}
int kgdb_arch_handle_exception(int vector, int signo,
int err_code, char *remcom_in_buffer,
char *remcom_out_buffer,
struct pt_regs *linux_regs)
struct pt_regs *regs)
{
long addr;
long breakno;
@ -385,44 +404,40 @@ int kgdb_arch_handle_exception(int exceptionVector, int signo,
/* try to read optional parameter, pc unchanged if no parm */
ptr = &remcom_in_buffer[1];
if (kgdb_hex2long(&ptr, &addr)) {
linux_regs->retx = addr;
regs->retx = addr;
}
newPC = linux_regs->retx;
newPC = regs->retx;
/* clear the trace bit */
linux_regs->syscfg &= 0xfffffffe;
regs->syscfg &= 0xfffffffe;
/* set the trace bit if we're stepping */
if (remcom_in_buffer[0] == 's') {
linux_regs->syscfg |= 0x1;
debugger_step = linux_regs->ipend;
debugger_step >>= 6;
for (i = 10; i > 0; i--, debugger_step >>= 1)
if (debugger_step & 1)
regs->syscfg |= 0x1;
kgdb_single_step = regs->ipend;
kgdb_single_step >>= 6;
for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
if (kgdb_single_step & 1)
break;
/* i indicate event priority of current stopped instruction
* user space instruction is 0, IVG15 is 1, IVTMR is 10.
* debugger_step > 0 means in single step mode
* kgdb_single_step > 0 means in single step mode
*/
debugger_step = i + 1;
} else {
debugger_step = 0;
kgdb_single_step = i + 1;
}
wp_status = bfin_read_WPSTAT();
CSYNC();
if (exceptionVector == VEC_WATCH) {
for (breakno = 0; breakno < 6; ++breakno) {
if (vector == VEC_WATCH) {
wp_status = bfin_read_WPSTAT();
for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++) {
if (wp_status & (1 << breakno)) {
breakinfo->skip = 1;
break;
}
}
bfin_write_WPSTAT(0);
}
kgdb_correct_hw_break();
bfin_write_WPSTAT(0);
bfin_correct_hw_break();
return 0;
} /* switch */
@ -431,5 +446,385 @@ int kgdb_arch_handle_exception(int exceptionVector, int signo,
struct kgdb_arch arch_kgdb_ops = {
.gdb_bpt_instr = {0xa1},
#ifdef CONFIG_SMP
.flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
#else
.flags = KGDB_HW_BREAKPOINT,
#endif
.set_hw_breakpoint = bfin_set_hw_break,
.remove_hw_breakpoint = bfin_remove_hw_break,
.remove_all_hw_break = bfin_remove_all_hw_break,
.correct_hw_break = bfin_correct_hw_break,
};
static int hex(char ch)
{
if ((ch >= 'a') && (ch <= 'f'))
return ch - 'a' + 10;
if ((ch >= '0') && (ch <= '9'))
return ch - '0';
if ((ch >= 'A') && (ch <= 'F'))
return ch - 'A' + 10;
return -1;
}
static int validate_memory_access_address(unsigned long addr, int size)
{
int cpu = raw_smp_processor_id();
if (size < 0)
return EFAULT;
if (addr >= 0x1000 && (addr + size) <= physical_mem_end)
return 0;
if (addr >= SYSMMR_BASE)
return 0;
if (addr >= ASYNC_BANK0_BASE
&& addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
return 0;
if (cpu == 0) {
if (addr >= L1_SCRATCH_START
&& (addr + size <= L1_SCRATCH_START + L1_SCRATCH_LENGTH))
return 0;
#if L1_CODE_LENGTH != 0
if (addr >= L1_CODE_START
&& (addr + size <= L1_CODE_START + L1_CODE_LENGTH))
return 0;
#endif
#if L1_DATA_A_LENGTH != 0
if (addr >= L1_DATA_A_START
&& (addr + size <= L1_DATA_A_START + L1_DATA_A_LENGTH))
return 0;
#endif
#if L1_DATA_B_LENGTH != 0
if (addr >= L1_DATA_B_START
&& (addr + size <= L1_DATA_B_START + L1_DATA_B_LENGTH))
return 0;
#endif
#ifdef CONFIG_SMP
} else if (cpu == 1) {
if (addr >= COREB_L1_SCRATCH_START
&& (addr + size <= COREB_L1_SCRATCH_START
+ L1_SCRATCH_LENGTH))
return 0;
# if L1_CODE_LENGTH != 0
if (addr >= COREB_L1_CODE_START
&& (addr + size <= COREB_L1_CODE_START + L1_CODE_LENGTH))
return 0;
# endif
# if L1_DATA_A_LENGTH != 0
if (addr >= COREB_L1_DATA_A_START
&& (addr + size <= COREB_L1_DATA_A_START + L1_DATA_A_LENGTH))
return 0;
# endif
# if L1_DATA_B_LENGTH != 0
if (addr >= COREB_L1_DATA_B_START
&& (addr + size <= COREB_L1_DATA_B_START + L1_DATA_B_LENGTH))
return 0;
# endif
#endif
}
#if L2_LENGTH != 0
if (addr >= L2_START
&& addr + size <= L2_START + L2_LENGTH)
return 0;
#endif
return EFAULT;
}
/*
* Convert the memory pointed to by mem into hex, placing result in buf.
* Return a pointer to the last char put in buf (null). May return an error.
*/
int kgdb_mem2hex(char *mem, char *buf, int count)
{
char *tmp;
int err = 0;
unsigned char *pch;
unsigned short mmr16;
unsigned long mmr32;
int cpu = raw_smp_processor_id();
if (validate_memory_access_address((unsigned long)mem, count))
return EFAULT;
/*
* We use the upper half of buf as an intermediate buffer for the
* raw memory copy. Hex conversion will work against this one.
*/
tmp = buf + count;
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
switch (count) {
case 2:
if ((unsigned int)mem % 2 == 0) {
mmr16 = *(unsigned short *)mem;
pch = (unsigned char *)&mmr16;
*tmp++ = *pch++;
*tmp++ = *pch++;
tmp -= 2;
} else
err = EFAULT;
break;
case 4:
if ((unsigned int)mem % 4 == 0) {
mmr32 = *(unsigned long *)mem;
pch = (unsigned char *)&mmr32;
*tmp++ = *pch++;
*tmp++ = *pch++;
*tmp++ = *pch++;
*tmp++ = *pch++;
tmp -= 4;
} else
err = EFAULT;
break;
default:
err = EFAULT;
}
} else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
(unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
#ifdef CONFIG_SMP
|| cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
(unsigned int)(mem + count) <=
COREB_L1_CODE_START + L1_CODE_LENGTH
#endif
) {
/* access L1 instruction SRAM*/
if (dma_memcpy(tmp, mem, count) == NULL)
err = EFAULT;
} else
err = probe_kernel_read(tmp, mem, count);
if (!err) {
while (count > 0) {
buf = pack_hex_byte(buf, *tmp);
tmp++;
count--;
}
*buf = 0;
}
return err;
}
/*
* Copy the binary array pointed to by buf into mem. Fix $, #, and
* 0x7d escaped with 0x7d. Return a pointer to the character after
* the last byte written.
*/
int kgdb_ebin2mem(char *buf, char *mem, int count)
{
char *tmp_old;
char *tmp_new;
unsigned short *mmr16;
unsigned long *mmr32;
int err = 0;
int size = 0;
int cpu = raw_smp_processor_id();
tmp_old = tmp_new = buf;
while (count-- > 0) {
if (*tmp_old == 0x7d)
*tmp_new = *(++tmp_old) ^ 0x20;
else
*tmp_new = *tmp_old;
tmp_new++;
tmp_old++;
size++;
}
if (validate_memory_access_address((unsigned long)mem, size))
return EFAULT;
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
switch (size) {
case 2:
if ((unsigned int)mem % 2 == 0) {
mmr16 = (unsigned short *)buf;
*(unsigned short *)mem = *mmr16;
} else
return EFAULT;
break;
case 4:
if ((unsigned int)mem % 4 == 0) {
mmr32 = (unsigned long *)buf;
*(unsigned long *)mem = *mmr32;
} else
return EFAULT;
break;
default:
return EFAULT;
}
} else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
(unsigned int)(mem + count) < L1_CODE_START + L1_CODE_LENGTH
#ifdef CONFIG_SMP
|| cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
(unsigned int)(mem + count) <=
COREB_L1_CODE_START + L1_CODE_LENGTH
#endif
) {
/* access L1 instruction SRAM */
if (dma_memcpy(mem, buf, size) == NULL)
err = EFAULT;
} else
err = probe_kernel_write(mem, buf, size);
return err;
}
/*
* Convert the hex array pointed to by buf into binary to be placed in mem.
* Return a pointer to the character AFTER the last byte written.
* May return an error.
*/
int kgdb_hex2mem(char *buf, char *mem, int count)
{
char *tmp_raw;
char *tmp_hex;
unsigned short *mmr16;
unsigned long *mmr32;
int cpu = raw_smp_processor_id();
if (validate_memory_access_address((unsigned long)mem, count))
return EFAULT;
/*
* We use the upper half of buf as an intermediate buffer for the
* raw memory that is converted from hex.
*/
tmp_raw = buf + count * 2;
tmp_hex = tmp_raw - 1;
while (tmp_hex >= buf) {
tmp_raw--;
*tmp_raw = hex(*tmp_hex--);
*tmp_raw |= hex(*tmp_hex--) << 4;
}
if ((unsigned int)mem >= SYSMMR_BASE) { /*access MMR registers*/
switch (count) {
case 2:
if ((unsigned int)mem % 2 == 0) {
mmr16 = (unsigned short *)tmp_raw;
*(unsigned short *)mem = *mmr16;
} else
return EFAULT;
break;
case 4:
if ((unsigned int)mem % 4 == 0) {
mmr32 = (unsigned long *)tmp_raw;
*(unsigned long *)mem = *mmr32;
} else
return EFAULT;
break;
default:
return EFAULT;
}
} else if (cpu == 0 && (unsigned int)mem >= L1_CODE_START &&
(unsigned int)(mem + count) <= L1_CODE_START + L1_CODE_LENGTH
#ifdef CONFIG_SMP
|| cpu == 1 && (unsigned int)mem >= COREB_L1_CODE_START &&
(unsigned int)(mem + count) <=
COREB_L1_CODE_START + L1_CODE_LENGTH
#endif
) {
/* access L1 instruction SRAM */
if (dma_memcpy(mem, tmp_raw, count) == NULL)
return EFAULT;
} else
return probe_kernel_write(mem, tmp_raw, count);
return 0;
}
int kgdb_validate_break_address(unsigned long addr)
{
int cpu = raw_smp_processor_id();
if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
return 0;
if (addr >= ASYNC_BANK0_BASE
&& addr + BREAK_INSTR_SIZE <= ASYNC_BANK3_BASE + ASYNC_BANK3_BASE)
return 0;
#if L1_CODE_LENGTH != 0
if (cpu == 0 && addr >= L1_CODE_START
&& addr + BREAK_INSTR_SIZE <= L1_CODE_START + L1_CODE_LENGTH)
return 0;
# ifdef CONFIG_SMP
else if (cpu == 1 && addr >= COREB_L1_CODE_START
&& addr + BREAK_INSTR_SIZE <= COREB_L1_CODE_START + L1_CODE_LENGTH)
return 0;
# endif
#endif
#if L2_LENGTH != 0
if (addr >= L2_START
&& addr + BREAK_INSTR_SIZE <= L2_START + L2_LENGTH)
return 0;
#endif
return EFAULT;
}
int kgdb_arch_set_breakpoint(unsigned long addr, char *saved_instr)
{
int err;
int cpu = raw_smp_processor_id();
if ((cpu == 0 && (unsigned int)addr >= L1_CODE_START
&& (unsigned int)(addr + BREAK_INSTR_SIZE)
< L1_CODE_START + L1_CODE_LENGTH)
#ifdef CONFIG_SMP
|| (cpu == 1 && (unsigned int)addr >= COREB_L1_CODE_START
&& (unsigned int)(addr + BREAK_INSTR_SIZE)
< COREB_L1_CODE_START + L1_CODE_LENGTH)
#endif
) {
/* access L1 instruction SRAM */
if (dma_memcpy(saved_instr, (void *)addr, BREAK_INSTR_SIZE)
== NULL)
return -EFAULT;
if (dma_memcpy((void *)addr, arch_kgdb_ops.gdb_bpt_instr,
BREAK_INSTR_SIZE) == NULL)
return -EFAULT;
return 0;
} else {
err = probe_kernel_read(saved_instr, (char *)addr,
BREAK_INSTR_SIZE);
if (err)
return err;
return probe_kernel_write((char *)addr,
arch_kgdb_ops.gdb_bpt_instr, BREAK_INSTR_SIZE);
}
}
int kgdb_arch_remove_breakpoint(unsigned long addr, char *bundle)
{
if ((unsigned int)addr >= L1_CODE_START &&
(unsigned int)(addr + BREAK_INSTR_SIZE) <
L1_CODE_START + L1_CODE_LENGTH) {
/* access L1 instruction SRAM */
if (dma_memcpy((void *)addr, bundle, BREAK_INSTR_SIZE) == NULL)
return -EFAULT;
return 0;
} else
return probe_kernel_write((char *)addr,
(char *)bundle, BREAK_INSTR_SIZE);
}
int kgdb_arch_init(void)
{
kgdb_single_step = 0;
bfin_remove_all_hw_break();
return 0;
}
void kgdb_arch_exit(void)
{
}

215
arch/blackfin/kernel/ptrace.c
View File

@ -46,7 +46,6 @@
#include <asm/dma.h>
#include <asm/fixed_code.h>
#define MAX_SHARED_LIBS 3
#define TEXT_OFFSET 0
/*
* does not yet catch signals sent when the child dies.
@ -161,21 +160,32 @@ static inline int is_user_addr_valid(struct task_struct *child,
struct vm_list_struct *vml;
struct sram_list_struct *sraml;
/* overflow */
if (start + len < start)
return -EIO;
for (vml = child->mm->context.vmlist; vml; vml = vml->next)
if (start >= vml->vma->vm_start && start + len <= vml->vma->vm_end)
if (start >= vml->vma->vm_start && start + len < vml->vma->vm_end)
return 0;
for (sraml = child->mm->context.sram_list; sraml; sraml = sraml->next)
if (start >= (unsigned long)sraml->addr
&& start + len <= (unsigned long)sraml->addr + sraml->length)
&& start + len < (unsigned long)sraml->addr + sraml->length)
return 0;
if (start >= FIXED_CODE_START && start + len <= FIXED_CODE_END)
if (start >= FIXED_CODE_START && start + len < FIXED_CODE_END)
return 0;
return -EIO;
}
void ptrace_enable(struct task_struct *child)
{
unsigned long tmp;
tmp = get_reg(child, PT_SYSCFG) | (TRACE_BITS);
put_reg(child, PT_SYSCFG, tmp);
}
/*
* Called by kernel/ptrace.c when detaching..
*
@ -192,14 +202,12 @@ void ptrace_disable(struct task_struct *child)
long arch_ptrace(struct task_struct *child, long request, long addr, long data)
{
int ret;
int add = 0;
unsigned long __user *datap = (unsigned long __user *)data;
switch (request) {
/* when I and D space are separate, these will need to be fixed. */
case PTRACE_PEEKDATA:
pr_debug("ptrace: PEEKDATA\n");
add = MAX_SHARED_LIBS * 4; /* space between text and data */
/* fall through */
case PTRACE_PEEKTEXT: /* read word at location addr. */
{
@ -207,40 +215,35 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
int copied;
ret = -EIO;
pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + add %d %ld\n", addr, add,
sizeof(data));
if (is_user_addr_valid(child, addr + add, sizeof(tmp)) < 0)
pr_debug("ptrace: PEEKTEXT at addr 0x%08lx + %ld\n", addr, sizeof(data));
if (is_user_addr_valid(child, addr, sizeof(tmp)) < 0)
break;
pr_debug("ptrace: user address is valid\n");
#if L1_CODE_LENGTH != 0
if (addr + add >= L1_CODE_START
&& addr + add + sizeof(tmp) <= L1_CODE_START + L1_CODE_LENGTH) {
safe_dma_memcpy (&tmp, (const void *)(addr + add), sizeof(tmp));
if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START
&& addr + sizeof(tmp) <= L1_CODE_START + L1_CODE_LENGTH) {
safe_dma_memcpy (&tmp, (const void *)(addr), sizeof(tmp));
copied = sizeof(tmp);
} else
#endif
#if L1_DATA_A_LENGTH != 0
if (addr + add >= L1_DATA_A_START
&& addr + add + sizeof(tmp) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
} else if (L1_DATA_A_LENGTH != 0 && addr >= L1_DATA_A_START
&& addr + sizeof(tmp) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
memcpy(&tmp, (const void *)(addr), sizeof(tmp));
copied = sizeof(tmp);
} else
#endif
#if L1_DATA_B_LENGTH != 0
if (addr + add >= L1_DATA_B_START
&& addr + add + sizeof(tmp) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
} else if (L1_DATA_B_LENGTH != 0 && addr >= L1_DATA_B_START
&& addr + sizeof(tmp) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
memcpy(&tmp, (const void *)(addr), sizeof(tmp));
copied = sizeof(tmp);
} else
#endif
if (addr + add >= FIXED_CODE_START
&& addr + add + sizeof(tmp) <= FIXED_CODE_END) {
memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
} else if (addr >= FIXED_CODE_START
&& addr + sizeof(tmp) <= FIXED_CODE_END) {
memcpy(&tmp, (const void *)(addr), sizeof(tmp));
copied = sizeof(tmp);
} else
copied = access_process_vm(child, addr + add, &tmp,
copied = access_process_vm(child, addr, &tmp,
sizeof(tmp), 0);
pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
if (copied != sizeof(tmp))
break;
@ -284,47 +287,43 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
/* when I and D space are separate, this will have to be fixed. */
case PTRACE_POKEDATA:
printk(KERN_NOTICE "ptrace: PTRACE_PEEKDATA\n");
pr_debug("ptrace: PTRACE_PEEKDATA\n");
/* fall through */
case PTRACE_POKETEXT: /* write the word at location addr. */
{
int copied;
ret = -EIO;
pr_debug("ptrace: POKETEXT at addr 0x%08lx + add %d %ld bytes %lx\n",
addr, add, sizeof(data), data);
if (is_user_addr_valid(child, addr + add, sizeof(data)) < 0)
pr_debug("ptrace: POKETEXT at addr 0x%08lx + %ld bytes %lx\n",
addr, sizeof(data), data);
if (is_user_addr_valid(child, addr, sizeof(data)) < 0)
break;
pr_debug("ptrace: user address is valid\n");
#if L1_CODE_LENGTH != 0
if (addr + add >= L1_CODE_START
&& addr + add + sizeof(data) <= L1_CODE_START + L1_CODE_LENGTH) {
safe_dma_memcpy ((void *)(addr + add), &data, sizeof(data));
if (L1_CODE_LENGTH != 0 && addr >= L1_CODE_START
&& addr + sizeof(data) <= L1_CODE_START + L1_CODE_LENGTH) {
safe_dma_memcpy ((void *)(addr), &data, sizeof(data));
copied = sizeof(data);
} else
#endif
#if L1_DATA_A_LENGTH != 0
if (addr + add >= L1_DATA_A_START
&& addr + add + sizeof(data) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
memcpy((void *)(addr + add), &data, sizeof(data));
} else if (L1_DATA_A_LENGTH != 0 && addr >= L1_DATA_A_START
&& addr + sizeof(data) <= L1_DATA_A_START + L1_DATA_A_LENGTH) {
memcpy((void *)(addr), &data, sizeof(data));
copied = sizeof(data);
} else
#endif
#if L1_DATA_B_LENGTH != 0
if (addr + add >= L1_DATA_B_START
&& addr + add + sizeof(data) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
memcpy((void *)(addr + add), &data, sizeof(data));
} else if (L1_DATA_B_LENGTH != 0 && addr >= L1_DATA_B_START
&& addr + sizeof(data) <= L1_DATA_B_START + L1_DATA_B_LENGTH) {
memcpy((void *)(addr), &data, sizeof(data));
copied = sizeof(data);
} else
#endif
if (addr + add >= FIXED_CODE_START
&& addr + add + sizeof(data) <= FIXED_CODE_END) {
memcpy((void *)(addr + add), &data, sizeof(data));
} else if (addr >= FIXED_CODE_START
&& addr + sizeof(data) <= FIXED_CODE_END) {
memcpy((void *)(addr), &data, sizeof(data));
copied = sizeof(data);
} else
copied = access_process_vm(child, addr + add, &data,
copied = access_process_vm(child, addr, &data,
sizeof(data), 1);
pr_debug("ptrace: copied size %d\n", copied);
if (copied != sizeof(data))
break;
@ -351,29 +350,22 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
break;
case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
case PTRACE_CONT:
{ /* restart after signal. */
long tmp;
case PTRACE_CONT: /* restart after signal. */
pr_debug("ptrace: syscall/cont\n");
pr_debug("ptrace_cont\n");
ret = -EIO;
if (!valid_signal(data))
break;
if (request == PTRACE_SYSCALL)
set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
else
clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
child->exit_code = data;
/* make sure the single step bit is not set. */
tmp = get_reg(child, PT_SYSCFG) & ~(TRACE_BITS);
put_reg(child, PT_SYSCFG, tmp);
pr_debug("before wake_up_process\n");
wake_up_process(child);
ret = 0;
ret = -EIO;
if (!valid_signal(data))
break;
}
if (request == PTRACE_SYSCALL)
set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
else
clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
child->exit_code = data;
ptrace_disable(child);
pr_debug("ptrace: before wake_up_process\n");
wake_up_process(child);
ret = 0;
break;
/*
* make the child exit. Best I can do is send it a sigkill.
@ -381,55 +373,37 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
* exit.
*/
case PTRACE_KILL:
{
long tmp;
ret = 0;
if (child->exit_state == EXIT_ZOMBIE) /* already dead */
break;
child->exit_code = SIGKILL;
/* make sure the single step bit is not set. */
tmp = get_reg(child, PT_SYSCFG) & ~(TRACE_BITS);
put_reg(child, PT_SYSCFG, tmp);
wake_up_process(child);
ret = 0;
if (child->exit_state == EXIT_ZOMBIE) /* already dead */
break;
}
child->exit_code = SIGKILL;
ptrace_disable(child);
wake_up_process(child);
break;
case PTRACE_SINGLESTEP:
{ /* set the trap flag. */
long tmp;
pr_debug("single step\n");
ret = -EIO;
if (!valid_signal(data))
break;
clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
tmp = get_reg(child, PT_SYSCFG) | (TRACE_BITS);
put_reg(child, PT_SYSCFG, tmp);
child->exit_code = data;
/* give it a chance to run. */
wake_up_process(child);
ret = 0;
case PTRACE_SINGLESTEP: /* set the trap flag. */
pr_debug("ptrace: single step\n");
ret = -EIO;
if (!valid_signal(data))
break;
}
clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
ptrace_enable(child);
child->exit_code = data;
wake_up_process(child);
ret = 0;
break;
case PTRACE_GETREGS:
{
/* Get all gp regs from the child. */
ret = ptrace_getregs(child, datap);
break;
}
/* Get all gp regs from the child. */
ret = ptrace_getregs(child, datap);
break;
case PTRACE_SETREGS:
{
printk(KERN_NOTICE
"ptrace: SETREGS: **** NOT IMPLEMENTED ***\n");
/* Set all gp regs in the child. */
ret = 0;
break;
}
printk(KERN_WARNING "ptrace: SETREGS: **** NOT IMPLEMENTED ***\n");
/* Set all gp regs in the child. */
ret = 0;
break;
default:
ret = ptrace_request(child, request, addr, data);
break;
@ -440,7 +414,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
asmlinkage void syscall_trace(void)
{
if (!test_thread_flag(TIF_SYSCALL_TRACE))
return;

18
arch/blackfin/kernel/reboot.c
View File

@ -10,6 +10,7 @@
#include <asm/bfin-global.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <asm/bfrom.h>
/* A system soft reset makes external memory unusable so force
* this function into L1. We use the compiler ssync here rather
@ -20,7 +21,7 @@
* the core reset.
*/
__attribute__((l1_text))
void bfin_reset(void)
static void bfin_reset(void)
{
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
@ -34,15 +35,15 @@ void bfin_reset(void)
bfin_write_SWRST(0x7);
/* Due to the way reset is handled in the hardware, we need
* to delay for 7 SCLKS. The only reliable way to do this is
* to calculate the CCLK/SCLK ratio and multiply 7. For now,
* to delay for 10 SCLKS. The only reliable way to do this is
* to calculate the CCLK/SCLK ratio and multiply 10. For now,
* we'll assume worse case which is a 1:15 ratio.
*/
asm(
"LSETUP (1f, 1f) LC0 = %0\n"
"1: nop;"
:
: "a" (15 * 7)
: "a" (15 * 10)
: "LC0", "LB0", "LT0"
);
@ -74,7 +75,14 @@ void machine_restart(char *cmd)
{
native_machine_restart(cmd);
local_irq_disable();
bfin_reset();
if (ANOMALY_05000353 || ANOMALY_05000386)
bfin_reset();
else
/* the bootrom checks to see how it was reset and will
* automatically perform a software reset for us when
* it starts executing boot
*/
asm("raise 1;");
}
__attribute__((weak))

97
arch/blackfin/kernel/setup.c
View File

@ -42,6 +42,7 @@ EXPORT_SYMBOL(memory_start);
EXPORT_SYMBOL(memory_end);
EXPORT_SYMBOL(physical_mem_end);
EXPORT_SYMBOL(_ramend);
EXPORT_SYMBOL(reserved_mem_dcache_on);
#ifdef CONFIG_MTD_UCLINUX
unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
@ -52,7 +53,8 @@ EXPORT_SYMBOL(mtd_size);
#endif
char __initdata command_line[COMMAND_LINE_SIZE];
unsigned int __initdata *__retx;
void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
*init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
/* boot memmap, for parsing "memmap=" */
#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
@ -77,10 +79,10 @@ static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
void __init bf53x_cache_init(void)
void __init bfin_cache_init(void)
{
#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
generate_cpl_tables();
generate_cplb_tables();
#endif
#ifdef CONFIG_BFIN_ICACHE
@ -100,7 +102,7 @@ void __init bf53x_cache_init(void)
#endif
}
void __init bf53x_relocate_l1_mem(void)
void __init bfin_relocate_l1_mem(void)
{
unsigned long l1_code_length;
unsigned long l1_data_a_length;
@ -410,7 +412,7 @@ static __init void parse_cmdline_early(char *cmdline_p)
* [_rambase, _ramstart]: kernel image
* [memory_start, memory_end]: dynamic memory managed by kernel
* [memory_end, _ramend]: reserved memory
* [meory_mtd_start(memory_end),
* [memory_mtd_start(memory_end),
* memory_mtd_start + mtd_size]: rootfs (if any)
* [_ramend - DMA_UNCACHED_REGION,
* _ramend]: uncached DMA region
@ -782,16 +784,25 @@ void __init setup_arch(char **cmdline_p)
_bfin_swrst = bfin_read_SWRST();
/* If we double fault, reset the system - otherwise we hang forever */
bfin_write_SWRST(DOUBLE_FAULT);
#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
#endif
if (_bfin_swrst & RESET_DOUBLE)
/*
* don't decode the address, since you don't know if this
* kernel's symbol map is the same as the crashing kernel
*/
printk(KERN_INFO "Recovering from Double Fault event at %pF\n", __retx);
else if (_bfin_swrst & RESET_WDOG)
if (_bfin_swrst & RESET_DOUBLE) {
printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
#ifdef CONFIG_DEBUG_DOUBLEFAULT
/* We assume the crashing kernel, and the current symbol table match */
printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
(int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
#endif
printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
init_retx);
} else if (_bfin_swrst & RESET_WDOG)
printk(KERN_INFO "Recovering from Watchdog event\n");
else if (_bfin_swrst & RESET_SOFTWARE)
printk(KERN_NOTICE "Reset caused by Software reset\n");
@ -803,17 +814,24 @@ void __init setup_arch(char **cmdline_p)
printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
else
printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
if (bfin_revid() != bfin_compiled_revid()) {
if (bfin_compiled_revid() == -1)
printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
bfin_revid());
else if (bfin_compiled_revid() != 0xffff)
printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
bfin_compiled_revid(), bfin_revid());
if (unlikely(CPUID != bfin_cpuid()))
printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
CPU, bfin_cpuid(), bfin_revid());
else {
if (bfin_revid() != bfin_compiled_revid()) {
if (bfin_compiled_revid() == -1)
printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
bfin_revid());
else if (bfin_compiled_revid() != 0xffff)
printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
bfin_compiled_revid(), bfin_revid());
}
if (bfin_revid() <= CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
CPU, bfin_revid());
}
if (bfin_revid() < SUPPORTED_REVID)
printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
CPU, bfin_revid());
printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
@ -850,7 +868,7 @@ void __init setup_arch(char **cmdline_p)
!= SAFE_USER_INSTRUCTION - FIXED_CODE_START);
init_exception_vectors();
bf53x_cache_init();
bfin_cache_init();
}
static int __init topology_init(void)
@ -986,13 +1004,18 @@ static int show_cpuinfo(struct seq_file *m, void *v)
}
seq_printf(m, "processor\t: %d\n"
"vendor_id\t: %s\n"
"cpu family\t: 0x%x\n"
"model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
"vendor_id\t: %s\n",
*(unsigned int *)v,
vendor);
if (CPUID == bfin_cpuid())
seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
else
seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
CPUID, bfin_cpuid());
seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
"stepping\t: %d\n",
0,
vendor,
(bfin_read_CHIPID() & CHIPID_FAMILY),
cpu, cclk/1000000, sclk/1000000,
#ifdef CONFIG_MPU
"mpu on",
@ -1038,7 +1061,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
if ((bfin_read_DMEM_CONTROL() & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
dcache_size = 0;
if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) == (IMC | ENICPLB))
if ((bfin_read_IMEM_CONTROL() & (IMC | ENICPLB)) != (IMC | ENICPLB))
icache_size = 0;
seq_printf(m, "cache size\t: %d KB(L1 icache) "
@ -1127,12 +1150,18 @@ static int show_cpuinfo(struct seq_file *m, void *v)
static void *c_start(struct seq_file *m, loff_t *pos)
{
return *pos < NR_CPUS ? ((void *)0x12345678) : NULL;
if (*pos == 0)
*pos = first_cpu(cpu_online_map);
if (*pos >= num_online_cpus())
return NULL;
return pos;
}
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
++*pos;
*pos = next_cpu(*pos, cpu_online_map);
return c_start(m, pos);
}

371
arch/blackfin/kernel/traps.c
View File

@ -34,20 +34,19 @@
#include <linux/fs.h>
#include <asm/traps.h>
#include <asm/cacheflush.h>
#include <asm/cplb.h>
#include <asm/blackfin.h>
#include <asm/irq_handler.h>
#include <linux/irq.h>
#include <asm/trace.h>
#include <asm/fixed_code.h>
#include <asm/dma.h>
#ifdef CONFIG_KGDB
# include <linux/debugger.h>
# include <linux/kgdb.h>
# define CHK_DEBUGGER_TRAP() \
do { \
CHK_DEBUGGER(trapnr, sig, info.si_code, fp, ); \
kgdb_handle_exception(trapnr, sig, info.si_code, fp); \
} while (0)
# define CHK_DEBUGGER_TRAP_MAYBE() \
do { \
@ -59,6 +58,15 @@
# define CHK_DEBUGGER_TRAP_MAYBE() do { } while (0)
#endif
#ifdef CONFIG_VERBOSE_DEBUG
#define verbose_printk(fmt, arg...) \
printk(fmt, ##arg)
#else
#define verbose_printk(fmt, arg...) \
({ if (0) printk(fmt, ##arg); 0; })
#endif
/* Initiate the event table handler */
void __init trap_init(void)
{
@ -67,10 +75,19 @@ void __init trap_init(void)
CSYNC();
}
unsigned long saved_icplb_fault_addr, saved_dcplb_fault_addr;
/*
* Used to save the RETX, SEQSTAT, I/D CPLB FAULT ADDR
* values across the transition from exception to IRQ5.
* We put these in L1, so they are going to be in a valid
* location during exception context
*/
__attribute__((l1_data))
unsigned long saved_retx, saved_seqstat,
saved_icplb_fault_addr, saved_dcplb_fault_addr;
static void decode_address(char *buf, unsigned long address)
{
#ifdef CONFIG_DEBUG_VERBOSE
struct vm_list_struct *vml;
struct task_struct *p;
struct mm_struct *mm;
@ -178,16 +195,39 @@ static void decode_address(char *buf, unsigned long address)
done:
write_unlock_irqrestore(&tasklist_lock, flags);
#else
sprintf(buf, " ");
#endif
}
asmlinkage void double_fault_c(struct pt_regs *fp)
{
console_verbose();
oops_in_progress = 1;
#ifdef CONFIG_DEBUG_VERBOSE
printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n");
dump_bfin_process(fp);
dump_bfin_mem(fp);
show_regs(fp);
#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
char buf[150];
decode_address(buf, saved_retx);
printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
(int)saved_seqstat & SEQSTAT_EXCAUSE, buf);
decode_address(buf, saved_dcplb_fault_addr);
printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
decode_address(buf, saved_icplb_fault_addr);
printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
decode_address(buf, fp->retx);
printk(KERN_NOTICE "The instruction at %s caused a double exception\n",
buf);
} else
#endif
{
dump_bfin_process(fp);
dump_bfin_mem(fp);
show_regs(fp);
}
#endif
panic("Double Fault - unrecoverable event\n");
}
@ -259,34 +299,42 @@ asmlinkage void trap_c(struct pt_regs *fp)
return;
else
break;
#ifdef CONFIG_KGDB
case VEC_EXCPT02 : /* gdb connection */
info.si_code = TRAP_ILLTRAP;
sig = SIGTRAP;
CHK_DEBUGGER_TRAP();
return;
#else
/* 0x02 - User Defined, Caught by default */
#endif
/* 0x03 - User Defined, userspace stack overflow */
case VEC_EXCPT03:
info.si_code = SEGV_STACKFLOW;
sig = SIGSEGV;
printk(KERN_NOTICE EXC_0x03(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x03(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x02 - KGDB initial connection and break signal trap */
case VEC_EXCPT02:
#ifdef CONFIG_KGDB
info.si_code = TRAP_ILLTRAP;
sig = SIGTRAP;
CHK_DEBUGGER_TRAP();
return;
#endif
/* 0x04 - User Defined */
/* 0x05 - User Defined */
/* 0x06 - User Defined */
/* 0x07 - User Defined */
/* 0x08 - User Defined */
/* 0x09 - User Defined */
/* 0x0A - User Defined */
/* 0x0B - User Defined */
/* 0x0C - User Defined */
/* 0x0D - User Defined */
/* 0x0E - User Defined */
/* 0x0F - User Defined */
/* If we got here, it is most likely that someone was trying to use a
* custom exception handler, and it is not actually installed properly
*/
case VEC_EXCPT04 ... VEC_EXCPT15:
info.si_code = ILL_ILLPARAOP;
sig = SIGILL;
verbose_printk(KERN_NOTICE EXC_0x04(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x04 - User Defined, Caught by default */
/* 0x05 - User Defined, Caught by default */
/* 0x06 - User Defined, Caught by default */
/* 0x07 - User Defined, Caught by default */
/* 0x08 - User Defined, Caught by default */
/* 0x09 - User Defined, Caught by default */
/* 0x0A - User Defined, Caught by default */
/* 0x0B - User Defined, Caught by default */
/* 0x0C - User Defined, Caught by default */
/* 0x0D - User Defined, Caught by default */
/* 0x0E - User Defined, Caught by default */
/* 0x0F - User Defined, Caught by default */
/* 0x10 HW Single step, handled here */
case VEC_STEP:
info.si_code = TRAP_STEP;
@ -301,8 +349,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_OVFLOW:
info.si_code = TRAP_TRACEFLOW;
sig = SIGTRAP;
printk(KERN_NOTICE EXC_0x11(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x11(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x12 - Reserved, Caught by default */
/* 0x13 - Reserved, Caught by default */
@ -323,44 +371,43 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_UNDEF_I:
info.si_code = ILL_ILLOPC;
sig = SIGILL;
printk(KERN_NOTICE EXC_0x21(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x21(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x22 - Illegal Instruction Combination, handled here */
case VEC_ILGAL_I:
info.si_code = ILL_ILLPARAOP;
sig = SIGILL;
printk(KERN_NOTICE EXC_0x22(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x22(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x23 - Data CPLB protection violation, handled here */
case VEC_CPLB_VL:
info.si_code = ILL_CPLB_VI;
sig = SIGBUS;
printk(KERN_NOTICE EXC_0x23(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x23(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x24 - Data access misaligned, handled here */
case VEC_MISALI_D:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
printk(KERN_NOTICE EXC_0x24(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x24(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x25 - Unrecoverable Event, handled here */
case VEC_UNCOV:
info.si_code = ILL_ILLEXCPT;
sig = SIGILL;
printk(KERN_NOTICE EXC_0x25(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x25(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x26 - Data CPLB Miss, normal case is handled in _cplb_hdr,
error case is handled here */
case VEC_CPLB_M:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
printk(KERN_NOTICE EXC_0x26(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x26(KERN_NOTICE));
break;
/* 0x27 - Data CPLB Multiple Hits - Linux Trap Zero, handled here */
case VEC_CPLB_MHIT:
@ -368,11 +415,11 @@ asmlinkage void trap_c(struct pt_regs *fp)
sig = SIGSEGV;
#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
if (saved_dcplb_fault_addr < FIXED_CODE_START)
printk(KERN_NOTICE "NULL pointer access\n");
verbose_printk(KERN_NOTICE "NULL pointer access\n");
else
#endif
printk(KERN_NOTICE EXC_0x27(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x27(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x28 - Emulation Watchpoint, handled here */
case VEC_WATCH:
@ -390,8 +437,8 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_ISTRU_VL: /* ADSP-BF535 only (MH) */
info.si_code = BUS_OPFETCH;
sig = SIGBUS;
printk(KERN_NOTICE "BF535: VEC_ISTRU_VL\n");
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE "BF535: VEC_ISTRU_VL\n");
CHK_DEBUGGER_TRAP_MAYBE();
break;
#else
/* 0x29 - Reserved, Caught by default */
@ -400,22 +447,21 @@ asmlinkage void trap_c(struct pt_regs *fp)
case VEC_MISALI_I:
info.si_code = BUS_ADRALN;
sig = SIGBUS;
printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x2A(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x2B - Instruction CPLB protection violation, handled here */
case VEC_CPLB_I_VL:
info.si_code = ILL_CPLB_VI;
sig = SIGBUS;
printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x2B(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x2C - Instruction CPLB miss, handled in _cplb_hdr */
case VEC_CPLB_I_M:
info.si_code = ILL_CPLB_MISS;
sig = SIGBUS;
printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x2C(KERN_NOTICE));
break;
/* 0x2D - Instruction CPLB Multiple Hits, handled here */
case VEC_CPLB_I_MHIT:
@ -423,18 +469,18 @@ asmlinkage void trap_c(struct pt_regs *fp)
sig = SIGSEGV;
#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
if (saved_icplb_fault_addr < FIXED_CODE_START)
printk(KERN_NOTICE "Jump to NULL address\n");
verbose_printk(KERN_NOTICE "Jump to NULL address\n");
else
#endif
printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x2D(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x2E - Illegal use of Supervisor Resource, handled here */
case VEC_ILL_RES:
info.si_code = ILL_PRVOPC;
sig = SIGILL;
printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE));
CHK_DEBUGGER_TRAP();
verbose_printk(KERN_NOTICE EXC_0x2E(KERN_NOTICE));
CHK_DEBUGGER_TRAP_MAYBE();
break;
/* 0x2F - Reserved, Caught by default */
/* 0x30 - Reserved, Caught by default */
@ -461,17 +507,17 @@ asmlinkage void trap_c(struct pt_regs *fp)
case (SEQSTAT_HWERRCAUSE_SYSTEM_MMR):
info.si_code = BUS_ADRALN;
sig = SIGBUS;
printk(KERN_NOTICE HWC_x2(KERN_NOTICE));
verbose_printk(KERN_NOTICE HWC_x2(KERN_NOTICE));
break;
/* External Memory Addressing Error */
case (SEQSTAT_HWERRCAUSE_EXTERN_ADDR):
info.si_code = BUS_ADRERR;
sig = SIGBUS;
printk(KERN_NOTICE HWC_x3(KERN_NOTICE));
verbose_printk(KERN_NOTICE HWC_x3(KERN_NOTICE));
break;
/* Performance Monitor Overflow */
case (SEQSTAT_HWERRCAUSE_PERF_FLOW):
printk(KERN_NOTICE HWC_x12(KERN_NOTICE));
verbose_printk(KERN_NOTICE HWC_x12(KERN_NOTICE));
break;
/* RAISE 5 instruction */
case (SEQSTAT_HWERRCAUSE_RAISE_5):
@ -481,21 +527,25 @@ asmlinkage void trap_c(struct pt_regs *fp)
printk(KERN_NOTICE HWC_default(KERN_NOTICE));
break;
}
CHK_DEBUGGER_TRAP();
CHK_DEBUGGER_TRAP_MAYBE();
break;
/*
* We should be handling all known exception types above,
* if we get here we hit a reserved one, so panic
*/
default:
info.si_code = TRAP_ILLTRAP;
sig = SIGTRAP;
printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
oops_in_progress = 1;
info.si_code = ILL_ILLPARAOP;
sig = SIGILL;
verbose_printk(KERN_EMERG "Caught Unhandled Exception, code = %08lx\n",
(fp->seqstat & SEQSTAT_EXCAUSE));
CHK_DEBUGGER_TRAP();
CHK_DEBUGGER_TRAP_MAYBE();
break;
}
BUG_ON(sig == 0);
if (sig != SIGTRAP) {
unsigned long *stack;
dump_bfin_process(fp);
dump_bfin_mem(fp);
show_regs(fp);
@ -503,7 +553,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
/* Print out the trace buffer if it makes sense */
#ifndef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
if (trapnr == VEC_CPLB_I_M || trapnr == VEC_CPLB_M)
printk(KERN_NOTICE "No trace since you do not have "
verbose_printk(KERN_NOTICE "No trace since you do not have "
"CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE enabled\n"
KERN_NOTICE "\n");
else
@ -512,20 +562,22 @@ asmlinkage void trap_c(struct pt_regs *fp)
if (oops_in_progress) {
/* Dump the current kernel stack */
printk(KERN_NOTICE "\n" KERN_NOTICE "Kernel Stack\n");
verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "Kernel Stack\n");
show_stack(current, NULL);
print_modules();
#ifndef CONFIG_ACCESS_CHECK
printk(KERN_EMERG "Please turn on "
verbose_printk(KERN_EMERG "Please turn on "
"CONFIG_ACCESS_CHECK\n");
#endif
panic("Kernel exception");
} else {
#ifdef CONFIG_VERBOSE_DEBUG
unsigned long *stack;
/* Dump the user space stack */
stack = (unsigned long *)rdusp();
printk(KERN_NOTICE "Userspace Stack\n");
verbose_printk(KERN_NOTICE "Userspace Stack\n");
show_stack(NULL, stack);
#endif
}
}
@ -546,7 +598,7 @@ asmlinkage void trap_c(struct pt_regs *fp)
* Similar to get_user, do some address checking, then dereference
* Return true on sucess, false on bad address
*/
bool get_instruction(unsigned short *val, unsigned short *address)
static bool get_instruction(unsigned short *val, unsigned short *address)
{
unsigned long addr;
@ -592,7 +644,7 @@ bool get_instruction(unsigned short *val, unsigned short *address)
#if L1_CODE_LENGTH != 0
if (addr >= L1_CODE_START && (addr + 2) <= (L1_CODE_START + L1_CODE_LENGTH)) {
dma_memcpy(val, address, 2);
isram_memcpy(val, address, 2);
return true;
}
#endif
@ -607,45 +659,48 @@ bool get_instruction(unsigned short *val, unsigned short *address)
* These are the normal instructions which cause change of flow, which
* would be at the source of the trace buffer
*/
void decode_instruction(unsigned short *address)
#ifdef CONFIG_DEBUG_VERBOSE
static void decode_instruction(unsigned short *address)
{
unsigned short opcode;
if (get_instruction(&opcode, address)) {
if (opcode == 0x0010)
printk("RTS");
verbose_printk("RTS");
else if (opcode == 0x0011)
printk("RTI");
verbose_printk("RTI");
else if (opcode == 0x0012)
printk("RTX");
verbose_printk("RTX");
else if (opcode >= 0x0050 && opcode <= 0x0057)
printk("JUMP (P%i)", opcode & 7);
verbose_printk("JUMP (P%i)", opcode & 7);
else if (opcode >= 0x0060 && opcode <= 0x0067)
printk("CALL (P%i)", opcode & 7);
verbose_printk("CALL (P%i)", opcode & 7);
else if (opcode >= 0x0070 && opcode <= 0x0077)
printk("CALL (PC+P%i)", opcode & 7);
verbose_printk("CALL (PC+P%i)", opcode & 7);
else if (opcode >= 0x0080 && opcode <= 0x0087)
printk("JUMP (PC+P%i)", opcode & 7);
verbose_printk("JUMP (PC+P%i)", opcode & 7);
else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF))
printk("IF !CC JUMP");
verbose_printk("IF !CC JUMP");
else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff))
printk("IF CC JUMP");
verbose_printk("IF CC JUMP");
else if (opcode >= 0x2000 && opcode <= 0x2fff)
printk("JUMP.S");
verbose_printk("JUMP.S");
else if (opcode >= 0xe080 && opcode <= 0xe0ff)
printk("LSETUP");
verbose_printk("LSETUP");
else if (opcode >= 0xe200 && opcode <= 0xe2ff)
printk("JUMP.L");
verbose_printk("JUMP.L");
else if (opcode >= 0xe300 && opcode <= 0xe3ff)
printk("CALL pcrel");
verbose_printk("CALL pcrel");
else
printk("0x%04x", opcode);
verbose_printk("0x%04x", opcode);
}
}
#endif
void dump_bfin_trace_buffer(void)
{
#ifdef CONFIG_DEBUG_VERBOSE
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
int tflags, i = 0;
char buf[150];
@ -701,6 +756,7 @@ void dump_bfin_trace_buffer(void)
trace_buffer_restore(tflags);
#endif
#endif
}
EXPORT_SYMBOL(dump_bfin_trace_buffer);
@ -708,7 +764,7 @@ EXPORT_SYMBOL(dump_bfin_trace_buffer);
* Checks to see if the address pointed to is either a
* 16-bit CALL instruction, or a 32-bit CALL instruction
*/
bool is_bfin_call(unsigned short *addr)
static bool is_bfin_call(unsigned short *addr)
{
unsigned short opcode = 0, *ins_addr;
ins_addr = (unsigned short *)addr;
@ -730,8 +786,10 @@ bool is_bfin_call(unsigned short *addr)
return false;
}
void show_stack(struct task_struct *task, unsigned long *stack)
{
#ifdef CONFIG_PRINTK
unsigned int *addr, *endstack, *fp = 0, *frame;
unsigned short *ins_addr;
char buf[150];
@ -756,8 +814,10 @@ void show_stack(struct task_struct *task, unsigned long *stack)
} else
endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
printk(KERN_NOTICE "Stack info:\n");
decode_address(buf, (unsigned int)stack);
printk(KERN_NOTICE "Stack info:\n" KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
addr = (unsigned int *)((unsigned int)stack & ~0x3F);
/* First thing is to look for a frame pointer */
@ -848,7 +908,7 @@ void show_stack(struct task_struct *task, unsigned long *stack)
if (!j)
printk("\n");
}
#endif
}
void dump_stack(void)
@ -866,38 +926,39 @@ EXPORT_SYMBOL(dump_stack);
void dump_bfin_process(struct pt_regs *fp)
{
#ifdef CONFIG_DEBUG_VERBOSE
/* We should be able to look at fp->ipend, but we don't push it on the
* stack all the time, so do this until we fix that */
unsigned int context = bfin_read_IPEND();
if (oops_in_progress)
printk(KERN_EMERG "Kernel OOPS in progress\n");
verbose_printk(KERN_EMERG "Kernel OOPS in progress\n");
if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
printk(KERN_NOTICE "HW Error context\n");
verbose_printk(KERN_NOTICE "HW Error context\n");
else if (context & 0x0020)
printk(KERN_NOTICE "Deferred Exception context\n");
verbose_printk(KERN_NOTICE "Deferred Exception context\n");
else if (context & 0x3FC0)
printk(KERN_NOTICE "Interrupt context\n");
verbose_printk(KERN_NOTICE "Interrupt context\n");
else if (context & 0x4000)
printk(KERN_NOTICE "Deferred Interrupt context\n");
verbose_printk(KERN_NOTICE "Deferred Interrupt context\n");
else if (context & 0x8000)
printk(KERN_NOTICE "Kernel process context\n");
verbose_printk(KERN_NOTICE "Kernel process context\n");
/* Because we are crashing, and pointers could be bad, we check things
* pretty closely before we use them
*/
if ((unsigned long)current >= FIXED_CODE_START &&
!((unsigned long)current & 0x3) && current->pid) {
printk(KERN_NOTICE "CURRENT PROCESS:\n");
verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
if (current->comm >= (char *)FIXED_CODE_START)
printk(KERN_NOTICE "COMM=%s PID=%d\n",
verbose_printk(KERN_NOTICE "COMM=%s PID=%d\n",
current->comm, current->pid);
else
printk(KERN_NOTICE "COMM= invalid\n");
verbose_printk(KERN_NOTICE "COMM= invalid\n");
if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START)
printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
verbose_printk(KERN_NOTICE "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
KERN_NOTICE " BSS = 0x%p-0x%p USER-STACK = 0x%p\n"
KERN_NOTICE "\n",
(void *)current->mm->start_code,
@ -908,38 +969,40 @@ void dump_bfin_process(struct pt_regs *fp)
(void *)current->mm->brk,
(void *)current->mm->start_stack);
else
printk(KERN_NOTICE "invalid mm\n");
verbose_printk(KERN_NOTICE "invalid mm\n");
} else
printk(KERN_NOTICE "\n" KERN_NOTICE
verbose_printk(KERN_NOTICE "\n" KERN_NOTICE
"No Valid process in current context\n");
#endif
}
void dump_bfin_mem(struct pt_regs *fp)
{
#ifdef CONFIG_DEBUG_VERBOSE
unsigned short *addr, *erraddr, val = 0, err = 0;
char sti = 0, buf[6];
erraddr = (void *)fp->pc;
printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
verbose_printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
addr++) {
if (!((unsigned long)addr & 0xF))
printk("\n" KERN_NOTICE "0x%p: ", addr);
verbose_printk("\n" KERN_NOTICE "0x%p: ", addr);
if (get_instruction(&val, addr)) {
if (!get_instruction(&val, addr)) {
val = 0;
sprintf(buf, "????");
} else
sprintf(buf, "%04x", val);
if (addr == erraddr) {
printk("[%s]", buf);
verbose_printk("[%s]", buf);
err = val;
} else
printk(" %s ", buf);
verbose_printk(" %s ", buf);
/* Do any previous instructions turn on interrupts? */
if (addr <= erraddr && /* in the past */
@ -948,14 +1011,14 @@ void dump_bfin_mem(struct pt_regs *fp)
sti = 1;
}
printk("\n");
verbose_printk("\n");
/* Hardware error interrupts can be deferred */
if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
oops_in_progress)){
printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
verbose_printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
#ifndef CONFIG_DEBUG_HWERR
printk(KERN_NOTICE "The remaining message may be meaningless\n"
verbose_printk(KERN_NOTICE "The remaining message may be meaningless\n"
KERN_NOTICE "You should enable CONFIG_DEBUG_HWERR to get a"
" better idea where it came from\n");
#else
@ -969,34 +1032,47 @@ void dump_bfin_mem(struct pt_regs *fp)
/* And the last RETI points to the current userspace context */
if ((fp + 1)->pc >= current->mm->start_code &&
(fp + 1)->pc <= current->mm->end_code) {
printk(KERN_NOTICE "It might be better to look around here : \n");
printk(KERN_NOTICE "-------------------------------------------\n");
verbose_printk(KERN_NOTICE "It might be better to look around here : \n");
verbose_printk(KERN_NOTICE "-------------------------------------------\n");
show_regs(fp + 1);
printk(KERN_NOTICE "-------------------------------------------\n");
verbose_printk(KERN_NOTICE "-------------------------------------------\n");
}
}
#endif
}
#endif
}
void show_regs(struct pt_regs *fp)
{
#ifdef CONFIG_DEBUG_VERBOSE
char buf [150];
struct irqaction *action;
unsigned int i;
unsigned long flags;
printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "SEQUENCER STATUS:\t\t%s\n", print_tainted());
verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx SYSCFG: %04lx\n",
(long)fp->seqstat, fp->ipend, fp->syscfg);
printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
(fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
(fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
#ifdef EBIU_ERRMST
/* If the error was from the EBIU, print it out */
if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
verbose_printk(KERN_NOTICE " EBIU Error Reason : 0x%04x\n",
bfin_read_EBIU_ERRMST());
verbose_printk(KERN_NOTICE " EBIU Error Address : 0x%08x\n",
bfin_read_EBIU_ERRADD());
}
#endif
}
verbose_printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
fp->seqstat & SEQSTAT_EXCAUSE);
for (i = 6; i <= 15 ; i++) {
if (fp->ipend & (1 << i)) {
decode_address(buf, bfin_read32(EVT0 + 4*i));
printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
verbose_printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
}
}
@ -1009,64 +1085,65 @@ void show_regs(struct pt_regs *fp)
goto unlock;
decode_address(buf, (unsigned int)action->handler);
printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
verbose_printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
for (action = action->next; action; action = action->next) {
decode_address(buf, (unsigned int)action->handler);
printk(", %s", buf);
verbose_printk(", %s", buf);
}
printk("\n");
verbose_printk("\n");
unlock:
spin_unlock_irqrestore(&irq_desc[i].lock, flags);
}
}
decode_address(buf, fp->rete);
printk(KERN_NOTICE " RETE: %s\n", buf);
verbose_printk(KERN_NOTICE " RETE: %s\n", buf);
decode_address(buf, fp->retn);
printk(KERN_NOTICE " RETN: %s\n", buf);
verbose_printk(KERN_NOTICE " RETN: %s\n", buf);
decode_address(buf, fp->retx);
printk(KERN_NOTICE " RETX: %s\n", buf);
verbose_printk(KERN_NOTICE " RETX: %s\n", buf);
decode_address(buf, fp->rets);
printk(KERN_NOTICE " RETS: %s\n", buf);
verbose_printk(KERN_NOTICE " RETS: %s\n", buf);
decode_address(buf, fp->pc);
printk(KERN_NOTICE " PC : %s\n", buf);
verbose_printk(KERN_NOTICE " PC : %s\n", buf);
if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
(((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
decode_address(buf, saved_dcplb_fault_addr);
printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
decode_address(buf, saved_icplb_fault_addr);
printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf);
verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf);
}
printk(KERN_NOTICE "\n" KERN_NOTICE "PROCESSOR STATE:\n");
printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
verbose_printk(KERN_NOTICE "\n" KERN_NOTICE "PROCESSOR STATE:\n");
verbose_printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
fp->r0, fp->r1, fp->r2, fp->r3);
printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
verbose_printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
fp->r4, fp->r5, fp->r6, fp->r7);
printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
verbose_printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
fp->p0, fp->p1, fp->p2, fp->p3);
printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
verbose_printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
fp->p4, fp->p5, fp->fp, (long)fp);
printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n",
verbose_printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n",
fp->lb0, fp->lt0, fp->lc0);
printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n",
verbose_printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n",
fp->lb1, fp->lt1, fp->lc1);
printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
verbose_printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
fp->b0, fp->l0, fp->m0, fp->i0);
printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
verbose_printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
fp->b1, fp->l1, fp->m1, fp->i1);
printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
verbose_printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
fp->b2, fp->l2, fp->m2, fp->i2);
printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
verbose_printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
fp->b3, fp->l3, fp->m3, fp->i3);
printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
verbose_printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
fp->a0w, fp->a0x, fp->a1w, fp->a1x);
printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n",
verbose_printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n",
rdusp(), fp->astat);
printk(KERN_NOTICE "\n");
verbose_printk(KERN_NOTICE "\n");
#endif
}
#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1

5
arch/blackfin/mach-bf527/boards/Kconfig
View File

@ -14,4 +14,9 @@ config BFIN527_BLUETECHNIX_CM
help
CM-BF527 support for EVAL- and DEV-Board.
config BFIN526_EZBRD
bool "BF526-EZBRD"
help
BF526-EZBRD/EZKIT Lite board support.
endchoice

1
arch/blackfin/mach-bf527/boards/Makefile
View File

@ -4,3 +4,4 @@
obj-$(CONFIG_BFIN527_EZKIT) += ezkit.o
obj-$(CONFIG_BFIN527_BLUETECHNIX_CM) += cm_bf527.o
obj-$(CONFIG_BFIN526_EZBRD) += ezbrd.o

17
arch/blackfin/mach-bf527/boards/cm_bf527.c
View File

@ -43,10 +43,7 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/sl811.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
#endif
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
@ -130,6 +127,16 @@ static struct resource musb_resources[] = {
},
};
static struct musb_hdrc_config musb_config = {
.multipoint = 0,
.dyn_fifo = 0,
.soft_con = 1,
.dma = 1,
.num_eps = 7,
.dma_channels = 7,
.gpio_vrsel = GPIO_PF11,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG)
.mode = MUSB_OTG,
@ -138,7 +145,7 @@ static struct musb_hdrc_platform_data musb_plat = {
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL,
#endif
.multipoint = 0,
.config = &musb_config,
};
static u64 musb_dmamask = ~(u32)0;
@ -201,7 +208,7 @@ static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.offset = 0,
.size = 4 * SIZE_1M,
.size = 4 * 1024 * 1024,
},
{
.name = "file system(nand)",

734
arch/blackfin/mach-bf527/boards/ezbrd.c Normal file
View File

@ -0,0 +1,734 @@
/*
* File: arch/blackfin/mach-bf527/boards/ezbrd.c
* Based on: arch/blackfin/mach-bf537/boards/stamp.c
* Author: Aidan Williams <aidan@nicta.com.au>
*
* Created:
* Description:
*
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/musb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
#include <asm/nand.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <linux/spi/ad7877.h>
/*
* Name the Board for the /proc/cpuinfo
*/
const char bfin_board_name[] = "BF526-EZBRD";
/*
* Driver needs to know address, irq and flag pin.
*/
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
static struct resource musb_resources[] = {
[0] = {
.start = 0xffc03800,
.end = 0xffc03cff,
.flags = IORESOURCE_MEM,
},
[1] = { /* general IRQ */
.start = IRQ_USB_INT0,
.end = IRQ_USB_INT0,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
[2] = { /* DMA IRQ */
.start = IRQ_USB_DMA,
.end = IRQ_USB_DMA,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
},
};
static struct musb_hdrc_config musb_config = {
.multipoint = 0,
.dyn_fifo = 0,
.soft_con = 1,
.dma = 1,
.num_eps = 7,
.dma_channels = 7,
.gpio_vrsel = GPIO_PG13,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG)
.mode = MUSB_OTG,
#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
.mode = MUSB_HOST,
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL,
#endif
.config = &musb_config,
};
static u64 musb_dmamask = ~(u32)0;
static struct platform_device musb_device = {
.name = "musb_hdrc",
.id = 0,
.dev = {
.dma_mask = &musb_dmamask,
.coherent_dma_mask = 0xffffffff,
.platform_data = &musb_plat,
},
.num_resources = ARRAY_SIZE(musb_resources),
.resource = musb_resources,
};
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
static struct mtd_partition ezbrd_partitions[] = {
{
.name = "bootloader(nor)",
.size = 0x40000,
.offset = 0,
}, {
.name = "linux kernel(nor)",
.size = 0x1C0000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
static struct physmap_flash_data ezbrd_flash_data = {
.width = 2,
.parts = ezbrd_partitions,
.nr_parts = ARRAY_SIZE(ezbrd_partitions),
};
static struct resource ezbrd_flash_resource = {
.start = 0x20000000,
.end = 0x203fffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device ezbrd_flash_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &ezbrd_flash_data,
},
.num_resources = 1,
.resource = &ezbrd_flash_resource,
};
#endif
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.offset = 0,
.size = 4 * 1024 * 1024,
},
{
.name = "file system(nand)",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
},
};
static struct bf5xx_nand_platform bf5xx_nand_platform = {
.page_size = NFC_PG_SIZE_256,
.data_width = NFC_NWIDTH_8,
.partitions = partition_info,
.nr_partitions = ARRAY_SIZE(partition_info),
.rd_dly = 3,
.wr_dly = 3,
};
static struct resource bf5xx_nand_resources[] = {
{
.start = NFC_CTL,
.end = NFC_DATA_RD + 2,
.flags = IORESOURCE_MEM,
},
{
.start = CH_NFC,
.end = CH_NFC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bf5xx_nand_device = {
.name = "bf5xx-nand",
.id = 0,
.num_resources = ARRAY_SIZE(bf5xx_nand_resources),
.resource = bf5xx_nand_resources,
.dev = {
.platform_data = &bf5xx_nand_platform,
},
};
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
.id = -1,
};
#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
static struct platform_device bfin_mac_device = {
.name = "bfin_mac",
};
#endif
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
{
.name = "bootloader(spi)",
.size = 0x00040000,
.offset = 0,
.mask_flags = MTD_CAP_ROM
}, {
.name = "linux kernel(spi)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND,
}
};
static struct flash_platform_data bfin_spi_flash_data = {
.name = "m25p80",
.parts = bfin_spi_flash_partitions,
.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
.type = "m25p16",
};
/* SPI flash chip (m25p64) */
static struct bfin5xx_spi_chip spi_flash_chip_info = {
.enable_dma = 0, /* use dma transfer with this chip*/
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
/* SPI ADC chip */
static struct bfin5xx_spi_chip spi_adc_chip_info = {
.enable_dma = 1, /* use dma transfer with this chip*/
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
static struct bfin5xx_spi_chip spi_mmc_chip_info = {
.enable_dma = 1,
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_PBX)
static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
.ctl_reg = 0x4, /* send zero */
.enable_dma = 0,
.bits_per_word = 8,
.cs_change_per_word = 1,
};
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
};
static const struct ad7877_platform_data bfin_ad7877_ts_info = {
.model = 7877,
.vref_delay_usecs = 50, /* internal, no capacitor */
.x_plate_ohms = 419,
.y_plate_ohms = 486,
.pressure_max = 1000,
.pressure_min = 0,
.stopacq_polarity = 1,
.first_conversion_delay = 3,
.acquisition_time = 1,
.averaging = 1,
.pen_down_acc_interval = 1,
};
#endif
#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
&& defined(CONFIG_SND_SOC_WM8731_SPI)
static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
{
/* the modalias must be the same as spi device driver name */
.modalias = "m25p80", /* Name of spi_driver for this device */
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
.platform_data = &bfin_spi_flash_data,
.controller_data = &spi_flash_chip_info,
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_SPI_ADC_BF533) \
|| defined(CONFIG_SPI_ADC_BF533_MODULE)
{
.modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
.max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0, /* Framework bus number */
.chip_select = 1, /* Framework chip select. */
.platform_data = NULL, /* No spi_driver specific config */
.controller_data = &spi_adc_chip_info,
},
#endif
#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
{
.modalias = "spi_mmc_dummy",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 0,
.platform_data = NULL,
.controller_data = &spi_mmc_chip_info,
.mode = SPI_MODE_3,
},
{
.modalias = "spi_mmc",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = CONFIG_SPI_MMC_CS_CHAN,
.platform_data = NULL,
.controller_data = &spi_mmc_chip_info,
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_PBX)
{
.modalias = "fxs-spi",
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 8 - CONFIG_J11_JUMPER,
.controller_data = &spi_si3xxx_chip_info,
.mode = SPI_MODE_3,
},
{
.modalias = "fxo-spi",
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 8 - CONFIG_J19_JUMPER,
.controller_data = &spi_si3xxx_chip_info,
.mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
{
.modalias = "ad7877",
.platform_data = &bfin_ad7877_ts_info,
.irq = IRQ_PF8,
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 2,
.controller_data = &spi_ad7877_chip_info,
},
#endif
#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
&& defined(CONFIG_SND_SOC_WM8731_SPI)
{
.modalias = "wm8731",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 5,
.controller_data = &spi_wm8731_chip_info,
.mode = SPI_MODE_0,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
{
.modalias = "bfin-lq035q1-spi",
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &lq035q1_spi_chip_info,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
};
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
/* SPI controller data */
static struct bfin5xx_spi_master bfin_spi0_info = {
.num_chipselect = 8,
.enable_dma = 1, /* master has the ability to do dma transfer */
.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
};
/* SPI (0) */
static struct resource bfin_spi0_resource[] = {
[0] = {
.start = SPI0_REGBASE,
.end = SPI0_REGBASE + 0xFF,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CH_SPI,
.end = CH_SPI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_spi0_device = {
.name = "bfin-spi",
.id = 0, /* Bus number */
.num_resources = ARRAY_SIZE(bfin_spi0_resource),
.resource = bfin_spi0_resource,
.dev = {
.platform_data = &bfin_spi0_info, /* Passed to driver */
},
};
#endif /* spi master and devices */
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_SERIAL_BFIN_UART1
{
.start = 0xFFC02000,
.end = 0xFFC020FF,
.flags = IORESOURCE_MEM,
},
#endif
};
static struct platform_device bfin_uart_device = {
.name = "bfin-uart",
.id = 1,
.num_resources = ARRAY_SIZE(bfin_uart_resources),
.resource = bfin_uart_resources,
};
#endif
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
static struct resource bfin_sir_resources[] = {
#ifdef CONFIG_BFIN_SIR0
{
.start = 0xFFC00400,
.end = 0xFFC004FF,
.flags = IORESOURCE_MEM,
},
#endif
#ifdef CONFIG_BFIN_SIR1
{
.start = 0xFFC02000,
.end = 0xFFC020FF,
.flags = IORESOURCE_MEM,
},
#endif
};
static struct platform_device bfin_sir_device = {
.name = "bfin_sir",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_sir_resources),
.resource = bfin_sir_resources,
};
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
static struct resource bfin_twi0_resource[] = {
[0] = {
.start = TWI0_REGBASE,
.end = TWI0_REGBASE,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_TWI,
.end = IRQ_TWI,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device i2c_bfin_twi_device = {
.name = "i2c-bfin-twi",
.id = 0,
.num_resources = ARRAY_SIZE(bfin_twi0_resource),
.resource = bfin_twi0_resource,
};
#endif
#ifdef CONFIG_I2C_BOARDINFO
static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
#if defined(CONFIG_TWI_LCD) || defined(CONFIG_TWI_LCD_MODULE)
{
I2C_BOARD_INFO("pcf8574_lcd", 0x22),
},
#endif
#if defined(CONFIG_TWI_KEYPAD) || defined(CONFIG_TWI_KEYPAD_MODULE)
{
I2C_BOARD_INFO("pcf8574_keypad", 0x27),
.irq = IRQ_PF8,
},
#endif
};
#endif
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
static struct platform_device bfin_sport0_uart_device = {
.name = "bfin-sport-uart",
.id = 0,
};
static struct platform_device bfin_sport1_uart_device = {
.name = "bfin-sport-uart",
.id = 1,
};
#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
#include <linux/input.h>
#include <linux/gpio_keys.h>
static struct gpio_keys_button bfin_gpio_keys_table[] = {
{BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
{BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
};
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
.buttons = bfin_gpio_keys_table,
.nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
};
static struct platform_device bfin_device_gpiokeys = {
.name = "gpio-keys",
.dev = {
.platform_data = &bfin_gpio_keys_data,
},
};
#endif
static struct resource bfin_gpios_resources = {
.start = 0,
.end = MAX_BLACKFIN_GPIOS - 1,
.flags = IORESOURCE_IRQ,
};
static struct platform_device bfin_gpios_device = {
.name = "simple-gpio",
.id = -1,
.num_resources = 1,
.resource = &bfin_gpios_resources,
};
static const unsigned int cclk_vlev_datasheet[] =
{
VRPAIR(VLEV_100, 400000000),
VRPAIR(VLEV_105, 426000000),
VRPAIR(VLEV_110, 500000000),
VRPAIR(VLEV_115, 533000000),
VRPAIR(VLEV_120, 600000000),
};
static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
.tuple_tab = cclk_vlev_datasheet,
.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
.vr_settling_time = 25 /* us */,
};
static struct platform_device bfin_dpmc = {
.name = "bfin dpmc",
.dev = {
.platform_data = &bfin_dmpc_vreg_data,
},
};
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
#include <asm/bfin-lq035q1.h>
static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
.mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
.use_bl = 1,
.gpio_bl = GPIO_PG12,
};
static struct resource bfin_lq035q1_resources[] = {
{
.start = IRQ_PPI_ERROR,
.end = IRQ_PPI_ERROR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_lq035q1_device = {
.name = "bfin-lq035q1",
.id = -1,
.num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
.resource = bfin_lq035q1_resources,
.dev = {
.platform_data = &bfin_lq035q1_data,
},
};
#endif
static struct platform_device *stamp_devices[] __initdata = {
&bfin_dpmc,
#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
&bf5xx_nand_device,
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
&rtc_device,
#endif
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
&musb_device,
#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
&bfin_mac_device,
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device,
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
&bfin_uart_device,
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
&bfin_lq035q1_device,
#endif
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
&bfin_sir_device,
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi_device,
#endif
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
&bfin_sport0_uart_device,
&bfin_sport1_uart_device,
#endif
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
&bfin_device_gpiokeys,
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&ezbrd_flash_device,
#endif
&bfin_gpios_device,
};
static int __init stamp_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __func__);
#ifdef CONFIG_I2C_BOARDINFO
i2c_register_board_info(0, bfin_i2c_board_info,
ARRAY_SIZE(bfin_i2c_board_info));
#endif
platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
return 0;
}
arch_initcall(stamp_init);
void native_machine_restart(char *cmd)
{
/* workaround reboot hang when booting from SPI */
if ((bfin_read_SYSCR() & 0x7) == 0x3)
bfin_gpio_reset_spi0_ssel1();
}
void bfin_get_ether_addr(char *addr)
{
/* the MAC is stored in OTP memory page 0xDF */
u32 ret;
u64 otp_mac;
u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
ret = otp_read(0xDF, 0x00, &otp_mac);
if (!(ret & 0x1)) {
char *otp_mac_p = (char *)&otp_mac;
for (ret = 0; ret < 6; ++ret)
addr[ret] = otp_mac_p[5 - ret];
}
}
EXPORT_SYMBOL(bfin_get_ether_addr);

53
arch/blackfin/mach-bf527/boards/ezkit.c
View File

@ -42,10 +42,7 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/sl811.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
#endif
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
#include <asm/reboot.h>
@ -129,6 +126,16 @@ static struct resource musb_resources[] = {
},
};
static struct musb_hdrc_config musb_config = {
.multipoint = 0,
.dyn_fifo = 0,
.soft_con = 1,
.dma = 1,
.num_eps = 7,
.dma_channels = 7,
.gpio_vrsel = GPIO_PG13,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG)
.mode = MUSB_OTG,
@ -137,7 +144,7 @@ static struct musb_hdrc_platform_data musb_plat = {
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL,
#endif
.multipoint = 0,
.config = &musb_config,
};
static u64 musb_dmamask = ~(u32)0;
@ -218,7 +225,7 @@ static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.offset = 0,
.size = 4 * SIZE_1M,
.size = 4 * 1024 * 1024,
},
{
.name = "file system(nand)",
@ -846,6 +853,38 @@ static struct platform_device bfin_device_gpiokeys = {
};
#endif
#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
#include <linux/input.h>
#include <asm/bfin_rotary.h>
static struct bfin_rotary_platform_data bfin_rotary_data = {
/*.rotary_up_key = KEY_UP,*/
/*.rotary_down_key = KEY_DOWN,*/
.rotary_rel_code = REL_WHEEL,
.rotary_button_key = KEY_ENTER,
.debounce = 10, /* 0..17 */
.mode = ROT_QUAD_ENC | ROT_DEBE,
};
static struct resource bfin_rotary_resources[] = {
{
.start = IRQ_CNT,
.end = IRQ_CNT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_rotary_device = {
.name = "bfin-rotary",
.id = -1,
.num_resources = ARRAY_SIZE(bfin_rotary_resources),
.resource = bfin_rotary_resources,
.dev = {
.platform_data = &bfin_rotary_data,
},
};
#endif
static struct resource bfin_gpios_resources = {
.start = 0,
.end = MAX_BLACKFIN_GPIOS - 1,
@ -962,6 +1001,10 @@ static struct platform_device *stamp_devices[] __initdata = {
&bfin_device_gpiokeys,
#endif
#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
&bfin_rotary_device,
#endif
#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
&ezkit_flash_device,
#endif

3
arch/blackfin/mach-bf527/head.S
View File

@ -87,6 +87,9 @@ ENTRY(_start_dma_code)
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */

160
arch/blackfin/mach-bf527/include/mach/anomaly.h
View File

@ -7,12 +7,24 @@
*/
/* This file shoule be up to date with:
* - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
* - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
* - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
# define ANOMALY_BF526 1
#else
# define ANOMALY_BF526 0
#endif
#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
# define ANOMALY_BF527 1
#else
# define ANOMALY_BF527 0
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
@ -23,68 +35,124 @@
#define ANOMALY_05000245 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* New Feature: EMAC TX DMA Word Alignment */
#define ANOMALY_05000285 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
#define ANOMALY_05000312 (ANOMALY_BF527)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (1)
#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
#define ANOMALY_05000337 (1)
#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
#define ANOMALY_05000341 (1)
#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
#define ANOMALY_05000342 (1)
#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* USB Calibration Value Is Not Initialized */
#define ANOMALY_05000346 (1)
#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* USB Calibration Value to use */
#define ANOMALY_05000346_value 0xE510
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (1)
#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Security Features Are Not Functional */
#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
#define ANOMALY_05000353 (ANOMALY_BF526)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (1)
#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* New Feature: Higher Default CCLK Rate */
#define ANOMALY_05000368 (1)
/* Incorrect Default CSEL Value in PLL_DIV */
#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Authentication Fails To Initiate */
#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Data Read From L3 Memory by USB DMA May be Corrupted */
#define ANOMALY_05000380 (1)
/* USB Full-speed Mode not Fully Tested */
#define ANOMALY_05000381 (1)
/* New Feature: Boot from OTP Memory */
#define ANOMALY_05000385 (1)
/* New Feature: bfrom_SysControl() Routine */
#define ANOMALY_05000386 (1)
/* New Feature: Programmable Preboot Settings */
#define ANOMALY_05000387 (1)
#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* 8-Bit NAND Flash Boot Mode Not Functional */
#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
/* Host Must Not Read Back During Host DMA Boot */
#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Boot from OTP Memory Not Functional */
#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* bfrom_SysControl() Firmware Routine Not Functional */
#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Programmable Preboot Settings Not Functional */
#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* CRC32 Checksum Support Not Functional */
#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
/* Reset Vector Must Not Be in SDRAM Memory Space */
#define ANOMALY_05000389 (1)
/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
#define ANOMALY_05000392 (1)
/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
#define ANOMALY_05000393 (1)
/* New Feature: Log Buffer Functionality */
#define ANOMALY_05000394 (1)
/* New Feature: Hook Routine Functionality */
#define ANOMALY_05000395 (1)
/* New Feature: Header Indirect Bit */
#define ANOMALY_05000396 (1)
/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
#define ANOMALY_05000397 (1)
/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
#define ANOMALY_05000398 (1)
/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
#define ANOMALY_05000399 (1)
#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Log Buffer Not Functional */
#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Hook Routine Not Functional */
#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Header Indirect Bit Not Functional */
#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
#define ANOMALY_05000401 (1)
#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Disallows Certain User Interrupts */
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Lockbox firmware leaves MDMA0 channel enabled */
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
/* Incorrect Default Internal Voltage Regulator Setting */
#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
/* DEB2_URGENT Bit Not Functional */
#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
#define ANOMALY_05000421 (1)
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
/* Internal Voltage Regulator Not Trimmed */
#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
#define ANOMALY_05000426 (1)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
#define ANOMALY_05000432 (ANOMALY_BF526)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
@ -97,6 +165,8 @@
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)

21
arch/blackfin/mach-bf527/include/mach/bf527.h
View File

@ -30,8 +30,6 @@
#ifndef __MACH_BF527_H__
#define __MACH_BF527_H__
#define SUPPORTED_REVID 2
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
@ -112,16 +110,31 @@
#ifdef CONFIG_BF527
#define CPU "BF527"
#define CPUID 0x27e4
#endif
#ifdef CONFIG_BF526
#define CPU "BF526"
#define CPUID 0x27e4
#endif
#ifdef CONFIG_BF525
#define CPU "BF525"
#define CPUID 0x27e4
#endif
#ifdef CONFIG_BF524
#define CPU "BF524"
#define CPUID 0x27e4
#endif
#ifdef CONFIG_BF523
#define CPU "BF523"
#define CPUID 0x27e4
#endif
#ifdef CONFIG_BF522
#define CPU "BF522"
#define CPUID 0x27e4
#endif
#ifndef CPU
#define CPU "UNKNOWN"
#define CPUID 0x0
#error Unknown CPU type - This kernel doesn't seem to be configured properly
#endif
#endif /* __MACH_BF527_H__ */

27
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
View File

@ -1840,6 +1840,33 @@
#define DPRESCALE 0xf /* Load Counter Register */
/* CNT_COMMAND bit field options */
#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
/* CNT_CONFIG bit field options */
#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
#define BNDMODE_COMP 0x0000 /* boundary compare mode */
#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
/* Bit masks for OTP_CONTROL */
#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */

4
arch/blackfin/mach-bf527/include/mach/portmux.h
View File

@ -67,6 +67,10 @@
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
#endif
#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
#define P_HWAIT (P_DONTCARE)
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))

34
arch/blackfin/mach-bf533/boards/H8606.c
View File

@ -9,7 +9,7 @@
* Modified:
* Copyright 2005 National ICT Australia (NICTA)
* Copyright 2004-2006 Analog Devices Inc
* Copyright 2007 HV Sistemas S.L.
* Copyright 2007,2008 HV Sistemas S.L.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@ -64,18 +64,18 @@ static struct platform_device rtc_device = {
static struct resource dm9000_resources[] = {
[0] = {
.start = 0x20300000,
.end = 0x20300000 + 1,
.end = 0x20300002,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 0x20300000 + 4,
.end = 0x20300000 + 5,
.start = 0x20300004,
.end = 0x20300006,
.flags = IORESOURCE_MEM,
},
[2] = {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
.flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | IRQF_SHARED | IRQF_TRIGGER_HIGH),
},
};
@ -140,18 +140,22 @@ static struct platform_device net2272_bfin_device = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
static struct mtd_partition bfin_spi_flash_partitions[] = {
{
.name = "bootloader(spi)",
.size = 0x00060000,
.name = "bootloader (spi)",
.size = 0x40000,
.offset = 0,
.mask_flags = MTD_CAP_ROM
}, {
.name = "linux kernel(spi)",
.size = 0x100000,
.offset = 0x60000
.name = "fpga (spi)",
.size = 0x30000,
.offset = 0x40000
}, {
.name = "file system(spi)",
.size = 0x6a0000,
.offset = 0x00160000,
.name = "linux kernel (spi)",
.size = 0x150000,
.offset = 0x70000
}, {
.name = "jffs2 root file system (spi)",
.size = 0x640000,
.offset = 0x1c0000,
}
};
@ -340,7 +344,7 @@ static struct platform_device bfin_sir_device = {
static struct plat_serial8250_port serial8250_platform_data [] = {
{
.membase = 0x20200000,
.membase = (void *)0x20200000,
.mapbase = 0x20200000,
.irq = IRQ_PF8,
.flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,
@ -348,7 +352,7 @@ static struct plat_serial8250_port serial8250_platform_data [] = {
.regshift = 1,
.uartclk = 66666667,
}, {
.membase = 0x20200010,
.membase = (void *)0x20200010,
.mapbase = 0x20200010,
.irq = IRQ_PF8,
.flags = UPF_BOOT_AUTOCONF | UART_CONFIG_TYPE,

3
arch/blackfin/mach-bf533/head.S
View File

@ -78,6 +78,9 @@ ENTRY(_start_dma_code)
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */

49
arch/blackfin/mach-bf533/include/mach/anomaly.h
View File

@ -7,7 +7,7 @@
*/
/* This file shoule be up to date with:
* - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
* - Revision D, 06/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@ -97,11 +97,11 @@
/* UART STB Bit Incorrectly Affects Receiver Setting */
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
/* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
@ -131,7 +131,7 @@
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
#define ANOMALY_05000265 (1)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
@ -141,56 +141,59 @@
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Writes to Synchronous SDRAM Memory May Be Lost */
#define ANOMALY_05000273 (1)
#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (1)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (1)
#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (1)
#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
/* False Hardware Error Exception When ISR Context Is Not Restored */
#define ANOMALY_05000281 (1)
#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
#define ANOMALY_05000282 (1)
#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
#define ANOMALY_05000283 (1)
#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (1)
#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1)
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
#define ANOMALY_05000311 (1)
#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
/* PPI Is Level-Sensitive on First Transfer */
#define ANOMALY_05000313 (1)
#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
#define ANOMALY_05000315 (1)
#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
/* PPI Does Not Start Properly In Specific Mode */
#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
@ -268,5 +271,7 @@
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000266 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000386 (1)
#endif

12
arch/blackfin/mach-bf533/include/mach/bf533.h
View File

@ -30,8 +30,6 @@
#ifndef __MACH_BF533_H__
#define __MACH_BF533_H__
#define SUPPORTED_REVID 2
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
@ -143,19 +141,19 @@
#ifdef CONFIG_BF533
#define CPU "BF533"
#define CPUID 0x027a5000
#define CPUID 0x27a5
#endif
#ifdef CONFIG_BF532
#define CPU "BF532"
#define CPUID 0x0275A000
#define CPUID 0x275A
#endif
#ifdef CONFIG_BF531
#define CPU "BF531"
#define CPUID 0x027a5000
#define CPUID 0x27a5
#endif
#ifndef CPU
#define CPU "UNKNOWN"
#define CPUID 0x0
#error Unknown CPU type - This kernel doesn't seem to be configured properly
#endif
#endif /* __MACH_BF533_H__ */

2
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
View File

@ -85,7 +85,7 @@ struct bfin_serial_port {
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#else
# if ANOMALY_05000230
# if ANOMALY_05000363
unsigned int anomaly_threshold;
# endif
#endif

85
arch/blackfin/mach-bf537/boards/stamp.c
View File

@ -51,7 +51,6 @@
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <linux/spi/ad7877.h>
/*
* Name the Board for the /proc/cpuinfo
@ -555,6 +554,7 @@ static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
#include <linux/spi/ad7877.h>
static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
@ -575,6 +575,28 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
#include <linux/spi/ad7879.h>
static struct bfin5xx_spi_chip spi_ad7879_chip_info = {
.enable_dma = 0,
.bits_per_word = 16,
};
static const struct ad7879_platform_data bfin_ad7879_ts_info = {
.model = 7879, /* Model = AD7879 */
.x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
.pressure_max = 10000,
.pressure_min = 0,
.first_conversion_delay = 3, /* wait 512us before do a first conversion */
.acquisition_time = 1, /* 4us acquisition time per sample */
.median = 2, /* do 8 measurements */
.averaging = 1, /* take the average of 4 middle samples */
.pen_down_acc_interval = 255, /* 9.4 ms */
.gpio_output = 1, /* configure AUX/VBAT/GPIO as GPIO output */
.gpio_default = 1, /* During initialization set GPIO = HIGH */
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
@ -582,6 +604,13 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
};
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
static struct bfin5xx_spi_chip lq035q1_spi_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
#if defined(CONFIG_MTD_DATAFLASH) \
|| defined(CONFIG_MTD_DATAFLASH_MODULE)
@ -721,6 +750,18 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &spi_ad7877_chip_info,
},
#endif
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
{
.modalias = "ad7879",
.platform_data = &bfin_ad7879_ts_info,
.irq = IRQ_PF7,
.max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spi_ad7879_chip_info,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
@ -730,6 +771,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &spidev_chip_info,
},
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
{
.modalias = "bfin-lq035q1-spi",
.max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 2,
.controller_data = &lq035q1_spi_chip_info,
.mode = SPI_CPHA | SPI_CPOL,
},
#endif
};
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
@ -777,6 +828,34 @@ static struct platform_device bfin_fb_adv7393_device = {
};
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
#include <asm/bfin-lq035q1.h>
static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
.mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
.use_bl = 0, /* let something else control the LCD Blacklight */
.gpio_bl = GPIO_PF7,
};
static struct resource bfin_lq035q1_resources[] = {
{
.start = IRQ_PPI_ERROR,
.end = IRQ_PPI_ERROR,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_lq035q1_device = {
.name = "bfin-lq035q1",
.id = -1,
.num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
.resource = bfin_lq035q1_resources,
.dev = {
.platform_data = &bfin_lq035q1_data,
},
};
#endif
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
static struct resource bfin_uart_resources[] = {
#ifdef CONFIG_SERIAL_BFIN_UART0
@ -997,6 +1076,10 @@ static struct platform_device *stamp_devices[] __initdata = {
&bfin_fb_device,
#endif
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
&bfin_lq035q1_device,
#endif
#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
&bfin_fb_adv7393_device,
#endif

3
arch/blackfin/mach-bf537/head.S
View File

@ -87,6 +87,9 @@ ENTRY(_start_dma_code)
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */

2
arch/blackfin/mach-bf537/include/mach/anomaly.h
View File

@ -158,6 +158,8 @@
#define ANOMALY_05000266 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000386 (1)
#endif

12
arch/blackfin/mach-bf537/include/mach/bf537.h
View File

@ -30,8 +30,6 @@
#ifndef __MACH_BF537_H__
#define __MACH_BF537_H__
#define SUPPORTED_REVID 2
/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE) /* SPI_STAT */
@ -123,19 +121,19 @@
#ifdef CONFIG_BF537
#define CPU "BF537"
#define CPUID 0x027c8000
#define CPUID 0x27c8
#endif
#ifdef CONFIG_BF536
#define CPU "BF536"
#define CPUID 0x027c8000
#define CPUID 0x27c8
#endif
#ifdef CONFIG_BF534
#define CPU "BF534"
#define CPUID 0x027c6000
#define CPUID 0x27c6
#endif
#ifndef CPU
#define CPU "UNKNOWN"
#define CPUID 0x0
#error Unknown CPU type - This kernel doesn't seem to be configured properly
#endif
#endif /* __MACH_BF537_H__ */

22
arch/blackfin/mach-bf548/boards/cm_bf548.c
View File

@ -36,11 +36,8 @@
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
#endif
#include <asm/bfin5xx_spi.h>
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/gpio.h>
#include <asm/nand.h>
@ -175,6 +172,7 @@ static struct resource bfin_uart_resources[] = {
{
.start = 0xFFC03100,
.end = 0xFFC031FF,
.flags = IORESOURCE_MEM,
},
#endif
};
@ -268,6 +266,16 @@ static struct resource musb_resources[] = {
},
};
static struct musb_hdrc_config musb_config = {
.multipoint = 0,
.dyn_fifo = 0,
.soft_con = 1,
.dma = 1,
.num_eps = 7,
.dma_channels = 7,
.gpio_vrsel = GPIO_PH6,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG)
.mode = MUSB_OTG,
@ -276,7 +284,7 @@ static struct musb_hdrc_platform_data musb_plat = {
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL,
#endif
.multipoint = 0,
.config = &musb_config,
};
static u64 musb_dmamask = ~(u32)0;
@ -321,12 +329,12 @@ static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.offset = 0,
.size = 4 * SIZE_1M,
.size = 4 * 1024 * 1024,
},
{
.name = "file system(nand)",
.offset = 4 * SIZE_1M,
.size = (256 - 4) * SIZE_1M,
.offset = 4 * 1024 * 1024,
.size = (256 - 4) * 1024 * 1024,
},
};

58
arch/blackfin/mach-bf548/boards/ezkit.c
View File

@ -38,11 +38,8 @@
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
#endif
#include <asm/bfin5xx_spi.h>
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/gpio.h>
#include <asm/nand.h>
@ -186,6 +183,37 @@ static struct platform_device bf54x_kpad_device = {
};
#endif
#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
#include <asm/bfin_rotary.h>
static struct bfin_rotary_platform_data bfin_rotary_data = {
/*.rotary_up_key = KEY_UP,*/
/*.rotary_down_key = KEY_DOWN,*/
.rotary_rel_code = REL_WHEEL,
.rotary_button_key = KEY_ENTER,
.debounce = 10, /* 0..17 */
.mode = ROT_QUAD_ENC | ROT_DEBE,
};
static struct resource bfin_rotary_resources[] = {
{
.start = IRQ_CNT,
.end = IRQ_CNT,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device bfin_rotary_device = {
.name = "bfin-rotary",
.id = -1,
.num_resources = ARRAY_SIZE(bfin_rotary_resources),
.resource = bfin_rotary_resources,
.dev = {
.platform_data = &bfin_rotary_data,
},
};
#endif
#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
static struct platform_device rtc_device = {
.name = "rtc-bfin",
@ -314,6 +342,16 @@ static struct resource musb_resources[] = {
},
};
static struct musb_hdrc_config musb_config = {
.multipoint = 0,
.dyn_fifo = 0,
.soft_con = 1,
.dma = 1,
.num_eps = 7,
.dma_channels = 7,
.gpio_vrsel = GPIO_PE7,
};
static struct musb_hdrc_platform_data musb_plat = {
#if defined(CONFIG_USB_MUSB_OTG)
.mode = MUSB_OTG,
@ -322,7 +360,7 @@ static struct musb_hdrc_platform_data musb_plat = {
#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
.mode = MUSB_PERIPHERAL,
#endif
.multipoint = 0,
.config = &musb_config,
};
static u64 musb_dmamask = ~(u32)0;
@ -367,7 +405,7 @@ static struct mtd_partition partition_info[] = {
{
.name = "linux kernel(nand)",
.offset = 0,
.size = 4 * SIZE_1M,
.size = 4 * 1024 * 1024,
},
{
.name = "file system(nand)",
@ -424,7 +462,7 @@ static struct mtd_partition ezkit_partitions[] = {
.offset = 0,
}, {
.name = "linux kernel(nor)",
.size = 0x1C0000,
.size = 0x400000,
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
@ -441,7 +479,7 @@ static struct physmap_flash_data ezkit_flash_data = {
static struct resource ezkit_flash_resource = {
.start = 0x20000000,
.end = 0x20ffffff,
.end = 0x21ffffff,
.flags = IORESOURCE_MEM,
};
@ -551,7 +589,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
{
.modalias = "ad7877",
.platform_data = &bfin_ad7877_ts_info,
.irq = IRQ_PJ11,
.irq = IRQ_PJ11, /* newer boards (Rev 1.4+) use IRQ_PB4 */
.max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 2,
@ -810,6 +848,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
&bf54x_kpad_device,
#endif
#if defined(CONFIG_JOYSTICK_BFIN_ROTARY) || defined(CONFIG_JOYSTICK_BFIN_ROTARY_MODULE)
&bfin_rotary_device,
#endif
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
&i2c_bfin_twi0_device,
#if !defined(CONFIG_BF542)

52
arch/blackfin/mach-bf548/head.S
View File

@ -73,25 +73,19 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
#if defined(CONFIG_BF54x)
/* enable self refresh via SRREQ */
P2.H = hi(EBIU_RSTCTL);
P2.L = lo(EBIU_RSTCTL);
R0 = [P2];
BITSET (R0, 3);
#else
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITSET (R0, 24);
#endif
[P2] = R0;
SSYNC;
#if defined(CONFIG_BF54x)
/* wait for SRACK bit to be set */
.LSRR_MODE:
R0 = [P2];
CC = BITTST(R0, 4);
if !CC JUMP .LSRR_MODE;
#endif
r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
r0 = r0 << 9; /* Shift it over, */
@ -100,6 +94,9 @@ ENTRY(_start_dma_code)
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */
@ -123,7 +120,7 @@ ENTRY(_start_dma_code)
w[p0] = r0.l;
ssync;
#if defined(CONFIG_BF54x)
/* disable self refresh by clearing SRREQ */
P2.H = hi(EBIU_RSTCTL);
P2.L = lo(EBIU_RSTCTL);
R0 = [P2];
@ -155,41 +152,6 @@ ENTRY(_start_dma_code)
r0.h = hi(mem_DDRCTL2);
[p0] = r0;
ssync;
#else
p0.l = lo(EBIU_SDRRC);
p0.h = hi(EBIU_SDRRC);
r0 = mem_SDRRC;
w[p0] = r0.l;
ssync;
p0.l = LO(EBIU_SDBCTL);
p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
r0 = mem_SDBCTL;
w[p0] = r0.l;
ssync;
P2.H = hi(EBIU_SDGCTL);
P2.L = lo(EBIU_SDGCTL);
R0 = [P2];
BITCLR (R0, 24);
p0.h = hi(EBIU_SDSTAT);
p0.l = lo(EBIU_SDSTAT);
r2.l = w[p0];
cc = bittst(r2,3);
if !cc jump .Lskip;
NOP;
BITSET (R0, 23);
.Lskip:
[P2] = R0;
SSYNC;
R0.L = lo(mem_SDGCTL);
R0.H = hi(mem_SDGCTL);
R1 = [p2];
R1 = R1 | R0;
[P2] = R1;
SSYNC;
#endif
RTS;
ENDPROC(_start_dma_code)

93
arch/blackfin/mach-bf548/include/mach/anomaly.h
View File

@ -2,18 +2,18 @@
* File: include/asm-blackfin/mach-bf548/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (C) 2004-2007 Analog Devices Inc.
* Copyright (C) 2004-2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
/* This file shoule be up to date with:
* - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
* - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
@ -36,14 +36,14 @@
/* TWI Slave Boot Mode Is Not Functional */
#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
/* External FIFO Boot Mode Is Not Functional */
#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
/* Incorrect Access of OTP_STATUS During otp_write() Function */
#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
/* Synchronous Burst Flash Boot Mode Is Not Functional */
#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
/* Host DMA Boot Mode Is Not Functional */
/* Host DMA Boot Modes Are Not Functional */
#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
@ -61,26 +61,102 @@
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
/* USB Calibration Value Is Not Intialized */
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
/* USB Calibration Value to use */
#define ANOMALY_05000346_value 0x5411
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
/* Data Lost when Core Reads SDH Data FIFO */
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
/* PLL Status Register Is Inaccurate */
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
#define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* External Memory Read Access Hangs Core With PLL Bypass */
#define ANOMALY_05000360 (1)
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
#define ANOMALY_05000365 (1)
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
#define ANOMALY_05000369 (1)
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
/* Mobile DDR Operation Not Functional */
#define ANOMALY_05000377 (1)
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
#define ANOMALY_05000378 (1)
#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
#define ANOMALY_05000379 (1)
/* 8-Bit NAND Flash Boot Mode Not Functional */
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
/* Some ATAPI Modes Are Not Functional */
#define ANOMALY_05000383 (1)
/* Boot from OTP Memory Not Functional */
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Firmware Routine Not Functional */
#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
/* Programmable Preboot Settings Not Functional */
#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
/* CRC32 Checksum Support Not Functional */
#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
/* Reset Vector Must Not Be in SDRAM Memory Space */
#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
/* Changed Meaning of BCODE Field in SYSCR Register */
#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
/* Log Buffer Not Functional */
#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
/* Hook Routine Not Functional */
#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
/* Header Indirect Bit Not Functional */
#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
/* Lockbox SESR Disallows Certain User Interrupts */
#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Lockbox firmware leaves MDMA0 channel enabled */
#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */
#define ANOMALY_05000426 (1)
/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */
#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
@ -93,6 +169,7 @@
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000363 (0)

25
arch/blackfin/mach-bf548/include/mach/bf548.h
View File

@ -30,8 +30,6 @@
#ifndef __MACH_BF548_H__
#define __MACH_BF548_H__
#define SUPPORTED_REVID 0
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
@ -108,20 +106,23 @@
#if defined(CONFIG_BF542)
# define CPU "BF542"
# define CPUID 0x027c8000
# define CPUID 0x27de
#elif defined(CONFIG_BF544)
# define CPU "BF544"
# define CPUID 0x027c8000
# define CPU "BF544"
# define CPUID 0x27de
#elif defined(CONFIG_BF547)
# define CPU "BF547"
# define CPU "BF547"
# define CPUID 0x27de
#elif defined(CONFIG_BF548)
# define CPU "BF548"
# define CPUID 0x027c6000
# define CPU "BF548"
# define CPUID 0x27de
#elif defined(CONFIG_BF549)
# define CPU "BF549"
#else
# define CPU "UNKNOWN"
# define CPUID 0x0
# define CPU "BF549"
# define CPUID 0x27de
#endif
#ifndef CPU
#error Unknown CPU type - This kernel doesn't seem to be configured properly
#endif
#endif /* __MACH_BF48_H__ */

14
arch/blackfin/mach-bf548/include/mach/mem_map.h
View File

@ -94,13 +94,13 @@
#endif /*CONFIG_BFIN_DCACHE*/
/* Level 2 Memory */
#if !defined(CONFIG_BF542)
# define L2_START 0xFEB00000
# if defined(CONFIG_BF544)
# define L2_LENGTH 0x10000
# else
# define L2_LENGTH 0x20000
# endif
#define L2_START 0xFEB00000
#if defined(CONFIG_BF542)
# define L2_LENGTH 0
#elif defined(CONFIG_BF544)
# define L2_LENGTH 0x10000
#else
# define L2_LENGTH 0x20000
#endif
/* Scratch Pad Memory */

3
arch/blackfin/mach-bf561/head.S
View File

@ -77,6 +77,9 @@ ENTRY(_start_dma_code)
r1 = PLL_BYPASS; /* Bypass the PLL? */
r1 = r1 << 8; /* Shift it over */
r0 = r1 | r0; /* add them all together */
#ifdef ANOMALY_05000265
r0 = BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
#endif
p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL); /* Load the address */

2
arch/blackfin/mach-bf561/include/mach/anomaly.h
View File

@ -270,5 +270,7 @@
#define ANOMALY_05000183 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000386 (1)
#endif

8
arch/blackfin/mach-bf561/include/mach/bf561.h
View File

@ -30,8 +30,6 @@
#ifndef __MACH_BF561_H__
#define __MACH_BF561_H__
#define SUPPORTED_REVID 0x3
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
@ -213,11 +211,11 @@
#ifdef CONFIG_BF561
#define CPU "BF561"
#define CPUID 0x027bb000
#define CPUID 0x27bb
#endif
#ifndef CPU
#define CPU "UNKNOWN"
#define CPUID 0x0
#error Unknown CPU type - This kernel doesn't seem to be configured properly
#endif
#endif /* __MACH_BF561_H__ */

2
arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
View File

@ -85,7 +85,7 @@ struct bfin_serial_port {
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#else
# if ANOMALY_05000230
# if ANOMALY_05000363
unsigned int anomaly_threshold;
# endif
#endif

18
arch/blackfin/mach-bf561/include/mach/mem_map.h
View File

@ -35,9 +35,16 @@
/* Memory Map for ADSP-BF561 processors */
#ifdef CONFIG_BF561
#define L1_CODE_START 0xFFA00000
#define L1_DATA_A_START 0xFF800000
#define L1_DATA_B_START 0xFF900000
#define COREA_L1_CODE_START 0xFFA00000
#define COREA_L1_DATA_A_START 0xFF800000
#define COREA_L1_DATA_B_START 0xFF900000
#define COREB_L1_CODE_START 0xFF600000
#define COREB_L1_DATA_A_START 0xFF400000
#define COREB_L1_DATA_B_START 0xFF500000
#define L1_CODE_START COREA_L1_CODE_START
#define L1_DATA_A_START COREA_L1_DATA_A_START
#define L1_DATA_B_START COREA_L1_DATA_B_START
#define L1_CODE_LENGTH 0x4000
@ -72,7 +79,10 @@
/* Scratch Pad Memory */
#define L1_SCRATCH_START 0xFFB00000
#define COREA_L1_SCRATCH_START 0xFFB00000
#define COREB_L1_SCRATCH_START 0xFF700000
#define L1_SCRATCH_START COREA_L1_SCRATCH_START
#define L1_SCRATCH_LENGTH 0x1000
#endif /* _MEM_MAP_533_H_ */

209
arch/blackfin/mach-common/entry.S
View File

@ -129,6 +129,18 @@ ENTRY(_ex_icplb_miss)
#else
call __cplb_hdr;
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT
/* While we were processing this, did we double fault? */
r7 = SEQSTAT; /* reason code is in bit 5:0 */
r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE);
r7 = r7 & r6;
r6 = 0x25;
CC = R7 == R6;
if CC JUMP _double_fault;
#endif
DEBUG_HWTRACE_RESTORE(p5, r7)
RESTORE_ALL_SYS
SP = EX_SCRATCH_REG;
@ -136,11 +148,8 @@ ENTRY(_ex_icplb_miss)
ENDPROC(_ex_icplb_miss)
ENTRY(_ex_syscall)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
raise 15; /* invoked by TRAP #0, for sys call */
sp = EX_SCRATCH_REG;
rtx
jump.s _bfin_return_from_exception;
ENDPROC(_ex_syscall)
ENTRY(_ex_soft_bp)
@ -181,8 +190,8 @@ ENTRY(_ex_single_step)
if cc jump .Lfind_priority_done;
jump.s .Lfind_priority_start;
.Lfind_priority_done:
p4.l = _debugger_step;
p4.h = _debugger_step;
p4.l = _kgdb_single_step;
p4.h = _kgdb_single_step;
r6 = [p4];
cc = r6 == 0;
if cc jump .Ldo_single_step;
@ -250,6 +259,29 @@ ENTRY(_bfin_return_from_exception)
R7=LC1;
LC1=R7;
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT
/* While we were processing the current exception,
* did we cause another, and double fault?
*/
r7 = SEQSTAT; /* reason code is in bit 5:0 */
r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE);
r7 = r7 & r6;
r6 = 0x25;
CC = R7 == R6;
if CC JUMP _double_fault;
/* Did we cause a HW error? */
p5.l = lo(ILAT);
p5.h = hi(ILAT);
r6 = [p5];
r7 = 0x20; /* Did I just cause anther HW error? */
r7 = r7 & r1;
CC = R7 == R6;
if CC JUMP _double_fault;
#endif
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
sp = EX_SCRATCH_REG;
@ -292,6 +324,14 @@ ENTRY(_ex_trap_c)
[p4] = p5;
csync;
#ifndef CONFIG_DEBUG_DOUBLEFAULT
/*
* Save these registers, as they are only valid in exception context
* (where we are now - as soon as we defer to IRQ5, they can change)
* DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
* but they are not very interesting, so don't save them
*/
p4.l = lo(DCPLB_FAULT_ADDR);
p4.h = hi(DCPLB_FAULT_ADDR);
r7 = [p4];
@ -304,12 +344,11 @@ ENTRY(_ex_trap_c)
p5.l = _saved_icplb_fault_addr;
[p5] = r7;
p4.l = _excpt_saved_stuff;
p4.h = _excpt_saved_stuff;
r6 = retx;
p4.l = _saved_retx;
p4.h = _saved_retx;
[p4] = r6;
#endif
r6 = SYSCFG;
[p4 + 4] = r6;
BITCLR(r6, 0);
@ -327,59 +366,56 @@ ENTRY(_ex_trap_c)
r6 = 0x3f;
sti r6;
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SP = EX_SCRATCH_REG;
raise 5;
rtx;
jump.s _bfin_return_from_exception;
ENDPROC(_ex_trap_c)
/* We just realized we got an exception, while we were processing a different
* exception. This is a unrecoverable event, so crash
*/
ENTRY(_double_fault)
/* Turn caches & protection off, to ensure we don't get any more
* double exceptions
*/
/* Turn caches & protection off, to ensure we don't get any more
* double exceptions
*/
P4.L = LO(IMEM_CONTROL);
P4.H = HI(IMEM_CONTROL);
P4.L = LO(IMEM_CONTROL);
P4.H = HI(IMEM_CONTROL);
R5 = [P4]; /* Control Register*/
BITCLR(R5,ENICPLB_P);
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
R5 = [P4]; /* Control Register*/
BITCLR(R5,ENICPLB_P);
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
P4.L = LO(DMEM_CONTROL);
P4.H = HI(DMEM_CONTROL);
R5 = [P4];
BITCLR(R5,ENDCPLB_P);
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
P4.L = LO(DMEM_CONTROL);
P4.H = HI(DMEM_CONTROL);
R5 = [P4];
BITCLR(R5,ENDCPLB_P);
SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
.align 8;
[P4] = R5;
SSYNC;
/* Fix up the stack */
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SP = EX_SCRATCH_REG;
/* Fix up the stack */
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SP = EX_SCRATCH_REG;
/* We should be out of the exception stack, and back down into
* kernel or user space stack
*/
SAVE_ALL_SYS
/* We should be out of the exception stack, and back down into
* kernel or user space stack
*/
SAVE_ALL_SYS
/* The dumping functions expect the return address in the RETI
* slot. */
r6 = retx;
[sp + PT_PC] = r6;
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
SP += -12;
call _double_fault_c;
SP += 12;
r0 = sp; /* stack frame pt_regs pointer argument ==> r0 */
SP += -12;
call _double_fault_c;
SP += 12;
.L_double_fault_panic:
JUMP .L_double_fault_panic
@ -388,8 +424,8 @@ ENDPROC(_double_fault)
ENTRY(_exception_to_level5)
SAVE_ALL_SYS
p4.l = _excpt_saved_stuff;
p4.h = _excpt_saved_stuff;
p4.l = _saved_retx;
p4.h = _saved_retx;
r6 = [p4];
[sp + PT_PC] = r6;
@ -420,6 +456,17 @@ ENTRY(_exception_to_level5)
call _trap_c;
SP += 12;
#ifdef CONFIG_DEBUG_DOUBLEFAULT
/* Grab ILAT */
p2.l = lo(ILAT);
p2.h = hi(ILAT);
r0 = [p2];
r1 = 0x20; /* Did I just cause anther HW error? */
r0 = r0 & r1;
CC = R0 == R1;
if CC JUMP _double_fault;
#endif
call _ret_from_exception;
RESTORE_ALL_SYS
rti;
@ -436,7 +483,48 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
/* Try to deal with syscalls quickly. */
[--sp] = ASTAT;
[--sp] = (R7:6,P5:4);
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r7 == r7;
p5.h = HI(CHIPID);
p5.l = LO(CHIPID);
if cc jump 1f;
r7.l = W[p5];
1:
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT
/*
* Save these registers, as they are only valid in exception context
* (where we are now - as soon as we defer to IRQ5, they can change)
* DCPLB_STATUS and ICPLB_STATUS are also only valid in EVT3,
* but they are not very interesting, so don't save them
*/
p4.l = lo(DCPLB_FAULT_ADDR);
p4.h = hi(DCPLB_FAULT_ADDR);
r7 = [p4];
p5.h = _saved_dcplb_fault_addr;
p5.l = _saved_dcplb_fault_addr;
[p5] = r7;
r7 = [p4 + (ICPLB_FAULT_ADDR - DCPLB_FAULT_ADDR)];
p5.h = _saved_icplb_fault_addr;
p5.l = _saved_icplb_fault_addr;
[p5] = r7;
p4.l = _saved_retx;
p4.h = _saved_retx;
r6 = retx;
[p4] = r6;
r7 = SEQSTAT; /* reason code is in bit 5:0 */
p4.l = _saved_seqstat;
p4.h = _saved_seqstat;
[p4] = r7;
#else
r7 = SEQSTAT; /* reason code is in bit 5:0 */
#endif
r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE);
r7 = r7 & r6;
@ -616,6 +704,9 @@ ENTRY(_system_call)
rts;
ENDPROC(_system_call)
/* Do not mark as ENTRY() to avoid error in assembler ...
* this symbol need not be global anyways, so ...
*/
_sys_trace:
call _syscall_trace;
@ -941,6 +1032,15 @@ ENTRY(_early_trap)
SAVE_ALL_SYS
trace_buffer_stop(p0,r0);
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r5 == r5;
p4.h = HI(CHIPID);
p4.l = LO(CHIPID);
if cc jump 1f;
r5.l = W[p4];
1:
#endif
/* Turn caches off, to ensure we don't get double exceptions */
P4.L = LO(IMEM_CONTROL);
@ -992,7 +1092,12 @@ ENTRY(_ex_table)
*/
.long _ex_syscall /* 0x00 - User Defined - Linux Syscall */
.long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
#ifdef CONFIG_KGDB
.long _ex_trap_c /* 0x02 - User Defined - KGDB initial connection
and break signal trap */
#else
.long _ex_replaceable /* 0x02 - User Defined */
#endif
.long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
.long _ex_trap_c /* 0x04 - User Defined - dump trace buffer */
.long _ex_replaceable /* 0x05 - User Defined */
@ -1432,15 +1537,7 @@ ENTRY(_sys_call_table)
.rept NR_syscalls-(.-_sys_call_table)/4
.long _sys_ni_syscall
.endr
/*
* Used to save the real RETX, IMASK and SYSCFG when temporarily
* storing safe values across the transition from exception to IRQ5.
*/
_excpt_saved_stuff:
.long 0;
.long 0;
.long 0;
END(_sys_call_table)
_exception_stack:
.rept 1024

52
arch/blackfin/mach-common/head.S
View File

@ -68,6 +68,16 @@ ENTRY(__start)
M2 = r0;
M3 = r0;
/*
* Clear ITEST_COMMAND and DTEST_COMMAND registers,
* Leaving these as non-zero can confuse the emulator
*/
p0.L = LO(DTEST_COMMAND);
p0.H = HI(DTEST_COMMAND);
[p0] = R0;
[p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
CSYNC;
trace_buffer_init(p0,r0);
P0 = R1;
R0 = R1;
@ -90,12 +100,46 @@ ENTRY(__start)
[p0] = R0;
SSYNC;
/* Save RETX, in case of doublefault */
p0.l = ___retx;
p0.h = ___retx;
/* in case of double faults, save a few things */
p0.l = _init_retx;
p0.h = _init_retx;
R0 = RETX;
[P0] = R0;
#ifdef CONFIG_DEBUG_DOUBLEFAULT
/* Only save these if we are storing them,
* This happens here, since L1 gets clobbered
* below
*/
p0.l = _saved_retx;
p0.h = _saved_retx;
p1.l = _init_saved_retx;
p1.h = _init_saved_retx;
r0 = [p0];
[p1] = r0;
p0.l = _saved_dcplb_fault_addr;
p0.h = _saved_dcplb_fault_addr;
p1.l = _init_saved_dcplb_fault_addr;
p1.h = _init_saved_dcplb_fault_addr;
r0 = [p0];
[p1] = r0;
p0.l = _saved_icplb_fault_addr;
p0.h = _saved_icplb_fault_addr;
p1.l = _init_saved_icplb_fault_addr;
p1.h = _init_saved_icplb_fault_addr;
r0 = [p0];
[p1] = r0;
p0.l = _saved_seqstat;
p0.h = _saved_seqstat;
p1.l = _init_saved_seqstat;
p1.h = _init_saved_seqstat;
r0 = [p0];
[p1] = r0;
#endif
/* Initialize stack pointer */
sp.l = lo(INITIAL_STACK);
sp.h = hi(INITIAL_STACK);
@ -107,7 +151,7 @@ ENTRY(__start)
#endif
/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
call _bf53x_relocate_l1_mem;
call _bfin_relocate_l1_mem;
#ifdef CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif

11
arch/blackfin/mach-common/interrupt.S
View File

@ -143,7 +143,7 @@ ENTRY(_evt_ivhw)
fp = 0;
#endif
#if ANOMALY_05000283
#if ANOMALY_05000283 || ANOMALY_05000315
cc = r7 == r7;
p5.h = HI(CHIPID);
p5.l = LO(CHIPID);
@ -179,7 +179,16 @@ ENTRY(_evt_ivhw)
call _trap_c;
SP += 12;
#ifdef EBIU_ERRMST
/* make sure EBIU_ERRMST is clear */
p0.l = LO(EBIU_ERRMST);
p0.h = HI(EBIU_ERRMST);
r0.l = (CORE_ERROR | CORE_MERROR);
w[p0] = r0.l;
#endif
call _ret_from_exception;
.Lcommon_restore_all_sys:
RESTORE_ALL_SYS
rti;

25
arch/blackfin/mach-common/ints-priority.c
View File

@ -243,12 +243,14 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
#endif
static struct irq_chip bfin_core_irqchip = {
.name = "CORE",
.ack = bfin_ack_noop,
.mask = bfin_core_mask_irq,
.unmask = bfin_core_unmask_irq,
};
static struct irq_chip bfin_internal_irqchip = {
.name = "INTN",
.ack = bfin_ack_noop,
.mask = bfin_internal_mask_irq,
.unmask = bfin_internal_unmask_irq,
@ -278,6 +280,7 @@ static void bfin_generic_error_unmask_irq(unsigned int irq)
}
static struct irq_chip bfin_generic_error_irqchip = {
.name = "ERROR",
.ack = bfin_ack_noop,
.mask_ack = bfin_generic_error_mask_irq,
.mask = bfin_generic_error_mask_irq,
@ -361,6 +364,14 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
}
#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
{
struct irq_desc *desc = irq_desc + irq;
/* May not call generic set_irq_handler() due to spinlock
recursion. */
desc->handle_irq = handle;
}
#if !defined(CONFIG_BF54x)
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
@ -473,9 +484,9 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
SSYNC();
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
set_irq_handler(irq, handle_edge_irq);
bfin_set_irq_handler(irq, handle_edge_irq);
else
set_irq_handler(irq, handle_level_irq);
bfin_set_irq_handler(irq, handle_level_irq);
return 0;
}
@ -495,6 +506,7 @@ int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
#endif
static struct irq_chip bfin_gpio_irqchip = {
.name = "GPIO",
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
.mask_ack = bfin_gpio_mask_ack_irq,
@ -804,10 +816,10 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
pint[bank]->edge_set = pintbit;
set_irq_handler(irq, handle_edge_irq);
bfin_set_irq_handler(irq, handle_edge_irq);
} else {
pint[bank]->edge_clear = pintbit;
set_irq_handler(irq, handle_level_irq);
bfin_set_irq_handler(irq, handle_level_irq);
}
SSYNC();
@ -884,6 +896,7 @@ void bfin_pm_restore(void)
#endif
static struct irq_chip bfin_gpio_irqchip = {
.name = "GPIO",
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
.mask_ack = bfin_gpio_mask_ack_irq,
@ -1136,8 +1149,4 @@ void do_irq(int vec, struct pt_regs *fp)
vec = ivg->irqno;
}
asm_do_IRQ(vec, fp);
#ifdef CONFIG_KGDB
kgdb_process_breakpoint();
#endif
}

2
arch/blackfin/mm/Makefile
View File

@ -2,4 +2,4 @@
# arch/blackfin/mm/Makefile
#
obj-y := blackfin_sram.o init.o
obj-y := sram-alloc.o isram-driver.o init.o

201
arch/blackfin/mm/isram-driver.c Normal file
View File

@ -0,0 +1,201 @@
/*
* Description: Instruction SRAM accessor functions for the Blackfin
*
* Copyright 2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/sched.h>
#include <asm/blackfin.h>
/*
* IMPORTANT WARNING ABOUT THESE FUNCTIONS
*
* The emulator will not function correctly if a write command is left in
* ITEST_COMMAND or DTEST_COMMAND AND access to cache memory is needed by
* the emulator. To avoid such problems, ensure that both ITEST_COMMAND
* and DTEST_COMMAND are zero when exiting these functions.
*/
/*
* On the Blackfin, L1 instruction sram (which operates at core speeds) can not
* be accessed by a normal core load, so we need to go through a few hoops to
* read/write it.
* To try to make it easier - we export a memcpy interface, where either src or
* dest can be in this special L1 memory area.
* The low level read/write functions should not be exposed to the rest of the
* kernel, since they operate on 64-bit data, and need specific address alignment
*/
static DEFINE_SPINLOCK(dtest_lock);
/* Takes a void pointer */
#define IADDR2DTEST(x) \
({ unsigned long __addr = (unsigned long)(x); \
(__addr & 0x47F8) | /* address bits 14 & 10:3 */ \
(__addr & 0x0800) << 15 | /* address bit 11 */ \
(__addr & 0x3000) << 4 | /* address bits 13:12 */ \
(__addr & 0x8000) << 8 | /* address bit 15 */ \
(0x1000004); /* isram access */ \
})
/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
#define ADDR2OFFSET(x) ((((unsigned long)(x)) & 0x7) * 8)
/* Takes a pointer, determines if it is the last byte in the isram 64-bit data type */
#define ADDR2LAST(x) ((((unsigned long)x) & 0x7) == 0x7)
static void isram_write(const void *addr, uint64_t data)
{
uint32_t cmd;
unsigned long flags;
if (addr >= (void *)(L1_CODE_START + L1_CODE_LENGTH))
return;
cmd = IADDR2DTEST(addr) | 1; /* write */
/*
* Writes to DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
* While in exception context - atomicity is guaranteed or double fault
*/
spin_lock_irqsave(&dtest_lock, flags);
bfin_write_DTEST_DATA0(data & 0xFFFFFFFF);
bfin_write_DTEST_DATA1(data >> 32);
/* use the builtin, since interrupts are already turned off */
__builtin_bfin_csync();
bfin_write_DTEST_COMMAND(cmd);
__builtin_bfin_csync();
bfin_write_DTEST_COMMAND(0);
__builtin_bfin_csync();
spin_unlock_irqrestore(&dtest_lock, flags);
}
static uint64_t isram_read(const void *addr)
{
uint32_t cmd;
unsigned long flags;
uint64_t ret;
if (addr > (void *)(L1_CODE_START + L1_CODE_LENGTH))
return 0;
cmd = IADDR2DTEST(addr) | 0; /* read */
/*
* Reads of DTEST_DATA[0:1] need to be atomic with write to DTEST_COMMAND
* While in exception context - atomicity is guaranteed or double fault
*/
spin_lock_irqsave(&dtest_lock, flags);
/* use the builtin, since interrupts are already turned off */
__builtin_bfin_csync();
bfin_write_DTEST_COMMAND(cmd);
__builtin_bfin_csync();
ret = bfin_read_DTEST_DATA0() | ((uint64_t)bfin_read_DTEST_DATA1() << 32);
bfin_write_DTEST_COMMAND(0);
__builtin_bfin_csync();
spin_unlock_irqrestore(&dtest_lock, flags);
return ret;
}
static bool isram_check_addr(const void *addr, size_t n)
{
if ((addr >= (void *)L1_CODE_START) &&
(addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))) {
if ((addr + n) >= (void *)(L1_CODE_START + L1_CODE_LENGTH)) {
show_stack(NULL, NULL);
printk(KERN_ERR "isram_memcpy: copy involving %p length "
"(%zu) too long\n", addr, n);
}
return true;
}
return false;
}
/*
* The isram_memcpy() function copies n bytes from memory area src to memory area dest.
* The isram_memcpy() function returns a pointer to dest.
* Either dest or src can be in L1 instruction sram.
*/
void *isram_memcpy(void *dest, const void *src, size_t n)
{
uint64_t data_in = 0, data_out = 0;
size_t count;
bool dest_in_l1, src_in_l1, need_data, put_data;
unsigned char byte, *src_byte, *dest_byte;
src_byte = (unsigned char *)src;
dest_byte = (unsigned char *)dest;
dest_in_l1 = isram_check_addr(dest, n);
src_in_l1 = isram_check_addr(src, n);
need_data = true;
put_data = true;
for (count = 0; count < n; count++) {
if (src_in_l1) {
if (need_data) {
data_in = isram_read(src + count);
need_data = false;
}
if (ADDR2LAST(src + count))
need_data = true;
byte = (unsigned char)((data_in >> ADDR2OFFSET(src + count)) & 0xff);
} else {
/* src is in L2 or L3 - so just dereference*/
byte = src_byte[count];
}
if (dest_in_l1) {
if (put_data) {
data_out = isram_read(dest + count);
put_data = false;
}
data_out &= ~((uint64_t)0xff << ADDR2OFFSET(dest + count));
data_out |= ((uint64_t)byte << ADDR2OFFSET(dest + count));
if (ADDR2LAST(dest + count)) {
put_data = true;
isram_write(dest + count, data_out);
}
} else {
/* dest in L2 or L3 - so just dereference */
dest_byte[count] = byte;
}
}
/* make sure we dump the last byte if necessary */
if (dest_in_l1 && !put_data)
isram_write(dest + count, data_out);
return dest;
}
EXPORT_SYMBOL(isram_memcpy);

31
arch/blackfin/mm/blackfin_sram.c → arch/blackfin/mm/sram-alloc.c
View File

@ -1,13 +1,13 @@
/*
* File: arch/blackfin/mm/blackfin_sram.c
* File: arch/blackfin/mm/sram-alloc.c
* Based on:
* Author:
*
* Created:
* Description: SRAM driver for Blackfin ADSP-BF5xx
* Description: SRAM allocator for Blackfin L1 and L2 memory
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
@ -78,7 +78,7 @@ static void __init l1sram_init(void)
free_l1_ssram_head.next =
kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
if (!free_l1_ssram_head.next) {
printk(KERN_INFO"Fail to initialize Scratchpad data SRAM.\n");
printk(KERN_INFO "Failed to initialize Scratchpad data SRAM\n");
return;
}
@ -102,7 +102,7 @@ static void __init l1_data_sram_init(void)
free_l1_data_A_sram_head.next =
kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
if (!free_l1_data_A_sram_head.next) {
printk(KERN_INFO"Fail to initialize L1 Data A SRAM.\n");
printk(KERN_INFO "Failed to initialize L1 Data A SRAM\n");
return;
}
@ -123,7 +123,7 @@ static void __init l1_data_sram_init(void)
free_l1_data_B_sram_head.next =
kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
if (!free_l1_data_B_sram_head.next) {
printk(KERN_INFO"Fail to initialize L1 Data B SRAM.\n");
printk(KERN_INFO "Failed to initialize L1 Data B SRAM\n");
return;
}
@ -151,7 +151,7 @@ static void __init l1_inst_sram_init(void)
free_l1_inst_sram_head.next =
kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
if (!free_l1_inst_sram_head.next) {
printk(KERN_INFO"Fail to initialize L1 Instruction SRAM.\n");
printk(KERN_INFO "Failed to initialize L1 Instruction SRAM\n");
return;
}
@ -179,7 +179,7 @@ static void __init l2_sram_init(void)
free_l2_sram_head.next =
kmem_cache_alloc(sram_piece_cache, GFP_KERNEL);
if (!free_l2_sram_head.next) {
printk(KERN_INFO"Fail to initialize L2 SRAM.\n");
printk(KERN_INFO "Failed to initialize L2 SRAM\n");
return;
}
@ -351,28 +351,31 @@ static int _sram_free(const void *addr,
int sram_free(const void *addr)
{
if (0) {}
#if L1_CODE_LENGTH != 0
else if (addr >= (void *)L1_CODE_START
if (addr >= (void *)L1_CODE_START
&& addr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
return l1_inst_sram_free(addr);
else
#endif
#if L1_DATA_A_LENGTH != 0
else if (addr >= (void *)L1_DATA_A_START
if (addr >= (void *)L1_DATA_A_START
&& addr < (void *)(L1_DATA_A_START + L1_DATA_A_LENGTH))
return l1_data_A_sram_free(addr);
else
#endif
#if L1_DATA_B_LENGTH != 0
else if (addr >= (void *)L1_DATA_B_START
if (addr >= (void *)L1_DATA_B_START
&& addr < (void *)(L1_DATA_B_START + L1_DATA_B_LENGTH))
return l1_data_B_sram_free(addr);
else
#endif
#if L2_LENGTH != 0
else if (addr >= (void *)L2_START
if (addr >= (void *)L2_START
&& addr < (void *)(L2_START + L2_LENGTH))
return l2_sram_free(addr);
#endif
else
#endif
return -1;
}
EXPORT_SYMBOL(sram_free);