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drm/bridge: anx7625: send DPCD command to downstream

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Send DPCD command to downstream before anx7625 power down,
let downstream monitor enter into standby mode.

Signed-off-by: Xin Ji <xji@analogixsemi.com>
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220213103437.3363848-1-hsinyi@chromium.org
This commit is contained in:
Xin Ji 2022-02-13 18:34:34 +08:00 committed by Robert Foss
parent 5357402398
commit 548b512e14
No known key found for this signature in database
GPG Key ID: 3EFD900F76D1D784
2 changed files with 35 additions and 9 deletions
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42
drivers/gpu/drm/bridge/analogix/anx7625.c
View File

@ -129,6 +129,23 @@ static int anx7625_reg_write(struct anx7625_data *ctx,
return ret; return ret;
} }
static int anx7625_reg_block_write(struct anx7625_data *ctx,
struct i2c_client *client,
u8 reg_addr, u8 len, u8 *buf)
{
int ret;
struct device *dev = &client->dev;
i2c_access_workaround(ctx, client);
ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf);
if (ret < 0)
dev_err(dev, "write i2c block failed id=%x\n:%x",
client->addr, reg_addr);
return ret;
}
static int anx7625_write_or(struct anx7625_data *ctx, static int anx7625_write_or(struct anx7625_data *ctx,
struct i2c_client *client, struct i2c_client *client,
u8 offset, u8 mask) u8 offset, u8 mask)
@ -214,8 +231,8 @@ static int wait_aux_op_finish(struct anx7625_data *ctx)
return 0; return 0;
} }
static int anx7625_aux_dpcd_read(struct anx7625_data *ctx, static int anx7625_aux_dpcd_trans(struct anx7625_data *ctx, u8 op,
u32 address, u8 len, u8 *buf) u32 address, u8 len, u8 *buf)
{ {
struct device *dev = &ctx->client->dev; struct device *dev = &ctx->client->dev;
int ret; int ret;
@ -231,8 +248,7 @@ static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
addrm = (address >> 8) & 0xFF; addrm = (address >> 8) & 0xFF;
addrh = (address >> 16) & 0xFF; addrh = (address >> 16) & 0xFF;
cmd = DPCD_CMD(len, DPCD_READ); cmd = DPCD_CMD(len, op);
cmd = ((len - 1) << 4) | 0x09;
/* Set command and length */ /* Set command and length */
ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
@ -246,6 +262,9 @@ static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_ADDR_19_16, addrh); AP_AUX_ADDR_19_16, addrh);
if (op == DP_AUX_NATIVE_WRITE)
ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
AP_AUX_BUFF_START, len, buf);
/* Enable aux access */ /* Enable aux access */
ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
@ -255,14 +274,17 @@ static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
return -EIO; return -EIO;
} }
usleep_range(2000, 2100);
ret = wait_aux_op_finish(ctx); ret = wait_aux_op_finish(ctx);
if (ret) { if (ret) {
dev_err(dev, "aux IO error: wait aux op finish.\n"); dev_err(dev, "aux IO error: wait aux op finish.\n");
return ret; return ret;
} }
/* Write done */
if (op == DP_AUX_NATIVE_WRITE)
return 0;
/* Read done, read out dpcd data */
ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
AP_AUX_BUFF_START, len, buf); AP_AUX_BUFF_START, len, buf);
if (ret < 0) { if (ret < 0) {
@ -845,7 +867,7 @@ static int anx7625_hdcp_enable(struct anx7625_data *ctx)
} }
/* Read downstream capability */ /* Read downstream capability */
anx7625_aux_dpcd_read(ctx, 0x68028, 1, &bcap); anx7625_aux_dpcd_trans(ctx, DP_AUX_NATIVE_READ, 0x68028, 1, &bcap);
if (!(bcap & 0x01)) { if (!(bcap & 0x01)) {
pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap);
return 0; return 0;
@ -918,6 +940,7 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
{ {
struct device *dev = &ctx->client->dev; struct device *dev = &ctx->client->dev;
int ret; int ret;
u8 data;
DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
@ -929,6 +952,11 @@ static void anx7625_dp_stop(struct anx7625_data *ctx)
ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
ret |= anx7625_video_mute_control(ctx, 1); ret |= anx7625_video_mute_control(ctx, 1);
dev_dbg(dev, "notify downstream enter into standby\n");
/* Downstream monitor enter into standby mode */
data = 2;
ret |= anx7625_aux_dpcd_trans(ctx, DP_AUX_NATIVE_WRITE, 0x000600, 1, &data);
if (ret < 0) if (ret < 0)
DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); DRM_DEV_ERROR(dev, "IO error : mute video fail\n");

2
drivers/gpu/drm/bridge/analogix/anx7625.h
View File

@ -242,8 +242,6 @@
#define AP_AUX_COMMAND 0x27 /* com+len */ #define AP_AUX_COMMAND 0x27 /* com+len */
#define LENGTH_SHIFT 4 #define LENGTH_SHIFT 4
#define DPCD_READ 0x09
#define DPCD_WRITE 0x08
#define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd)) #define DPCD_CMD(len, cmd) ((((len) - 1) << LENGTH_SHIFT) | (cmd))
/* Bit 0&1: 3D video structure */ /* Bit 0&1: 3D video structure */