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x86/smpboot: Remove the CPU0 hotplug kludge
This was introduced with commit e1c467e690 ("x86, hotplug: Wake up CPU0
via NMI instead of INIT, SIPI, SIPI") to eventually support physical
hotplug of CPU0:
"We'll change this code in the future to wake up hard offlined CPU0 if
real platform and request are available."
11 years later this has not happened and physical hotplug is not officially
supported. Remove the cruft.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Michael Kelley <mikelley@microsoft.com>
Tested-by: Oleksandr Natalenko <oleksandr@natalenko.name>
Tested-by: Helge Deller <deller@gmx.de> # parisc
Tested-by: Guilherme G. Piccoli <gpiccoli@igalia.com> # Steam Deck
Link: https://lore.kernel.org/r/20230512205255.768845190@linutronix.de
This commit is contained in:
Thomas Gleixner
Peter Zijlstra
parent
e59e74dc48
commit
5475abbde7
@ -377,7 +377,6 @@ extern struct apic *__apicdrivers[], *__apicdrivers_end[];
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* APIC functionality to boot other CPUs - only used on SMP:
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*/
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#ifdef CONFIG_SMP
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extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
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extern int lapic_can_unplug_cpu(void);
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#endif
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@ -130,7 +130,6 @@ void native_play_dead(void);
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void play_dead_common(void);
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void wbinvd_on_cpu(int cpu);
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int wbinvd_on_all_cpus(void);
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void cond_wakeup_cpu0(void);
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void native_smp_send_reschedule(int cpu);
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void native_send_call_func_ipi(const struct cpumask *mask);
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@ -216,9 +216,6 @@ static void ap_calibrate_delay(void)
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cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
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}
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static int cpu0_logical_apicid;
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static int enable_start_cpu0;
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/*
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* Activate a secondary processor.
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*/
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@ -241,8 +238,6 @@ static void notrace start_secondary(void *unused)
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x86_cpuinit.early_percpu_clock_init();
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smp_callin();
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enable_start_cpu0 = 0;
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/* otherwise gcc will move up smp_processor_id before the cpu_init */
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barrier();
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/* Check TSC synchronization with the control CPU: */
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@ -410,7 +405,7 @@ void smp_store_cpu_info(int id)
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c->cpu_index = id;
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/*
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* During boot time, CPU0 has this setup already. Save the info when
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* bringing up AP or offlined CPU0.
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* bringing up an AP.
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*/
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identify_secondary_cpu(c);
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c->initialized = true;
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@ -807,51 +802,14 @@ static void __init smp_quirk_init_udelay(void)
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}
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/*
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* Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
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* INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
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* won't ... remember to clear down the APIC, etc later.
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* Wake up AP by INIT, INIT, STARTUP sequence.
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*/
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int
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wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
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{
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u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
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unsigned long send_status, accept_status = 0;
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int maxlvt;
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/* Target chip */
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/* Boot on the stack */
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/* Kick the second */
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apic_icr_write(APIC_DM_NMI | dm, apicid);
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pr_debug("Waiting for send to finish...\n");
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send_status = safe_apic_wait_icr_idle();
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/*
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* Give the other CPU some time to accept the IPI.
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*/
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udelay(200);
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if (APIC_INTEGRATED(boot_cpu_apic_version)) {
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maxlvt = lapic_get_maxlvt();
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if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
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apic_write(APIC_ESR, 0);
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accept_status = (apic_read(APIC_ESR) & 0xEF);
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}
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pr_debug("NMI sent\n");
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if (send_status)
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pr_err("APIC never delivered???\n");
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if (accept_status)
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pr_err("APIC delivery error (%lx)\n", accept_status);
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return (send_status | accept_status);
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}
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static int
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wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
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static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
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{
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unsigned long send_status = 0, accept_status = 0;
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int maxlvt, num_starts, j;
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preempt_disable();
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maxlvt = lapic_get_maxlvt();
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/*
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@ -957,6 +915,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
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if (accept_status)
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pr_err("APIC delivery error (%lx)\n", accept_status);
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preempt_enable();
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return (send_status | accept_status);
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}
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@ -997,67 +956,6 @@ static void announce_cpu(int cpu, int apicid)
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node, cpu, apicid);
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}
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static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
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{
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int cpu;
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cpu = smp_processor_id();
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if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
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return NMI_HANDLED;
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return NMI_DONE;
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}
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/*
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* Wake up AP by INIT, INIT, STARTUP sequence.
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*
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* Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
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* boot-strap code which is not a desired behavior for waking up BSP. To
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* void the boot-strap code, wake up CPU0 by NMI instead.
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*
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* This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
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* (i.e. physically hot removed and then hot added), NMI won't wake it up.
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* We'll change this code in the future to wake up hard offlined CPU0 if
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* real platform and request are available.
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*/
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static int
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wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
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int *cpu0_nmi_registered)
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{
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int id;
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int boot_error;
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preempt_disable();
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/*
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* Wake up AP by INIT, INIT, STARTUP sequence.
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*/
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if (cpu) {
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boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
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goto out;
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}
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/*
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* Wake up BSP by nmi.
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*
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* Register a NMI handler to help wake up CPU0.
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*/
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boot_error = register_nmi_handler(NMI_LOCAL,
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wakeup_cpu0_nmi, 0, "wake_cpu0");
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if (!boot_error) {
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enable_start_cpu0 = 1;
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*cpu0_nmi_registered = 1;
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id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid;
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boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
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}
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out:
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preempt_enable();
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return boot_error;
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}
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int common_cpu_up(unsigned int cpu, struct task_struct *idle)
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{
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int ret;
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@ -1086,8 +984,7 @@ int common_cpu_up(unsigned int cpu, struct task_struct *idle)
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* Returns zero if CPU booted OK, else error code from
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* ->wakeup_secondary_cpu.
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*/
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static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
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int *cpu0_nmi_registered)
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static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
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{
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/* start_ip had better be page-aligned! */
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unsigned long start_ip = real_mode_header->trampoline_start;
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@ -1120,7 +1017,6 @@ static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
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* This grunge runs the startup process for
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* the targeted processor.
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*/
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if (x86_platform.legacy.warm_reset) {
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pr_debug("Setting warm reset code and vector.\n");
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@ -1149,15 +1045,14 @@ static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
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* - Use a method from the APIC driver if one defined, with wakeup
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* straight to 64-bit mode preferred over wakeup to RM.
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* Otherwise,
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* - Use an INIT boot APIC message for APs or NMI for BSP.
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* - Use an INIT boot APIC message
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*/
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if (apic->wakeup_secondary_cpu_64)
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boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip);
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else if (apic->wakeup_secondary_cpu)
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boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
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else
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boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
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cpu0_nmi_registered);
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boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
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if (!boot_error) {
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/*
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@ -1206,9 +1101,8 @@ static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
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int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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int apicid = apic->cpu_present_to_apicid(cpu);
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int cpu0_nmi_registered = 0;
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unsigned long flags;
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int err, ret = 0;
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int err;
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lockdep_assert_irqs_enabled();
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@ -1247,11 +1141,10 @@ int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
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if (err)
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return err;
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err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
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err = do_boot_cpu(apicid, cpu, tidle);
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if (err) {
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pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
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ret = -EIO;
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goto unreg_nmi;
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return err;
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}
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/*
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@ -1267,15 +1160,7 @@ int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
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touch_nmi_watchdog();
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}
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unreg_nmi:
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/*
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* Clean up the nmi handler. Do this after the callin and callout sync
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* to avoid impact of possible long unregister time.
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*/
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if (cpu0_nmi_registered)
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unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
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return ret;
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return 0;
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}
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/**
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@ -1373,14 +1258,6 @@ static void __init smp_cpu_index_default(void)
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}
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}
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static void __init smp_get_logical_apicid(void)
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{
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if (x2apic_mode)
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cpu0_logical_apicid = apic_read(APIC_LDR);
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else
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cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
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}
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void __init smp_prepare_cpus_common(void)
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{
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unsigned int i;
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@ -1443,8 +1320,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
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/* Setup local timer */
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x86_init.timers.setup_percpu_clockev();
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smp_get_logical_apicid();
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pr_info("CPU0: ");
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print_cpu_info(&cpu_data(0));
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@ -1752,18 +1627,6 @@ void play_dead_common(void)
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local_irq_disable();
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}
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/**
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* cond_wakeup_cpu0 - Wake up CPU0 if needed.
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*
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* If NMI wants to wake up CPU0, start CPU0.
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*/
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void cond_wakeup_cpu0(void)
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{
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if (smp_processor_id() == 0 && enable_start_cpu0)
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start_cpu0();
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}
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EXPORT_SYMBOL_GPL(cond_wakeup_cpu0);
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/*
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* We need to flush the caches before going to sleep, lest we have
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* dirty data in our caches when we come back up.
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@ -1831,8 +1694,6 @@ static inline void mwait_play_dead(void)
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__monitor(mwait_ptr, 0, 0);
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mb();
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__mwait(eax, 0);
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cond_wakeup_cpu0();
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}
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}
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@ -1841,11 +1702,8 @@ void __noreturn hlt_play_dead(void)
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if (__this_cpu_read(cpu_info.x86) >= 4)
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wbinvd();
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while (1) {
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while (1)
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native_halt();
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cond_wakeup_cpu0();
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}
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}
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void native_play_dead(void)
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@ -597,10 +597,6 @@ static int acpi_idle_play_dead(struct cpuidle_device *dev, int index)
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io_idle(cx->address);
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} else
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return -ENODEV;
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#if defined(CONFIG_X86) && defined(CONFIG_HOTPLUG_CPU)
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cond_wakeup_cpu0();
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#endif
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}
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/* Never reached */
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