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ARM: dts: Add devicetree for RDA8810PL SoC

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Add initial device tree for RDA8810PL SoC from RDA Microelectronics.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Manivannan Sadhasivam 2018-12-18 20:32:31 +05:30 committed by Olof Johansson
parent 78e3dbc166
commit 542e1c9dba
1 changed files with 86 additions and 0 deletions
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arch/arm/boot/dts/rda8810pl.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RDA8810PL SoC
*
* Copyright (c) 2017 Andreas Färber
* Copyright (c) 2018 Manivannan Sadhasivam
*/
/ {
compatible = "rda,8810pl";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0x0>;
};
};
sram@100000 {
compatible = "mmio-sram";
reg = <0x100000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
apb@20800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20800000 0x100000>;
intc: interrupt-controller@0 {
compatible = "rda,8810pl-intc";
reg = <0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
apb@20900000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20900000 0x100000>;
};
apb@20a00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20a00000 0x100000>;
uart1: serial@0 {
compatible = "rda,8810pl-uart";
reg = <0x0 0x1000>;
status = "disabled";
};
uart2: serial@10000 {
compatible = "rda,8810pl-uart";
reg = <0x10000 0x1000>;
status = "disabled";
};
uart3: serial@90000 {
compatible = "rda,8810pl-uart";
reg = <0x90000 0x1000>;
status = "disabled";
};
};
l2: cache-controller@21100000 {
compatible = "arm,pl310-cache";
reg = <0x21100000 0x1000>;
cache-unified;
cache-level = <2>;
};
};