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drm/amd/display: Add driver support for future FAMS versions

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[WHY&HOW]
Changes to support future versions of FAMS.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dillon Varone 2024-03-16 00:31:19 -04:00 committed by Alex Deucher
parent 19407237e7
commit 5324e2b205
11 changed files with 37 additions and 6 deletions
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2
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
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@ -44,8 +44,6 @@
#include "bios_parser_common.h"
#include "dc.h"
#define THREE_PERCENT_OF_10000 300
#define LAST_RECORD_TYPE 0xff

5
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -36,6 +36,7 @@
#include "resource.h"
#include "dc_state.h"
#include "dc_state_priv.h"
#include "dc_plane_priv.h"
#include "gpio_service_interface.h"
#include "clk_mgr.h"
@ -3561,6 +3562,7 @@ static void commit_planes_for_stream_fast(struct dc *dc,
int i, j;
struct pipe_ctx *top_pipe_to_program = NULL;
struct dc_stream_status *stream_status = NULL;
dc_exit_ips_for_hw_access(dc);
dc_z10_restore(dc);
@ -3618,7 +3620,8 @@ static void commit_planes_for_stream_fast(struct dc *dc,
context->block_sequence,
&(context->block_sequence_steps),
top_pipe_to_program,
stream_status);
stream_status,
context);
hwss_execute_sequence(dc,
context->block_sequence,
context->block_sequence_steps);

3
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
View File

@ -560,7 +560,8 @@ void hwss_build_fast_sequence(struct dc *dc,
struct block_sequence block_sequence[],
unsigned int *num_steps,
struct pipe_ctx *pipe_ctx,
struct dc_stream_status *stream_status)
struct dc_stream_status *stream_status,
struct dc_state *context)
{
struct dc_plane_state *plane = pipe_ctx->plane_state;
struct dc_stream_state *stream = pipe_ctx->stream;

1
drivers/gpu/drm/amd/display/dc/core/dc_state.c
View File

@ -915,3 +915,4 @@ struct dc_stream_state *dc_state_get_stream_from_id(const struct dc_state *state
return stream;
}

20
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
View File

@ -60,6 +60,26 @@ void dc_plane_destruct(struct dc_plane_state *plane_state)
// no more pointers to free within dc_plane_state
}
/* dc_state is passed in separately since it may differ from the current dc state accessible from plane_state e.g.
* if the driver is doing an update from an old context to a new one and the caller wants the pipe mask for the new
* context rather than the existing one
*/
uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state)
{
uint8_t pipe_mask = 0;
int i;
for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];
if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)
pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;
}
return pipe_mask;
}
/*******************************************************************************
* Public functions
******************************************************************************/

3
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -44,6 +44,8 @@
#include "dml2/dml2_wrapper.h"
#include "dmub/inc/dmub_cmd.h"
struct abm_save_restore;
/* forward declaration */
@ -219,6 +221,7 @@ struct dc_dmub_caps {
bool mclk_sw;
bool subvp_psr;
bool gecc_enable;
uint8_t fams_ver;
};
struct dc_caps {

2
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
View File

@ -35,6 +35,7 @@
#include "resource.h"
#include "clk_mgr.h"
#include "dc_state_priv.h"
#include "dc_plane_priv.h"
#define CTX dc_dmub_srv->ctx
#define DC_LOGGER CTX->logger
@ -1593,3 +1594,4 @@ bool dc_wake_and_execute_gpint(const struct dc_context *ctx, enum dmub_gpint_com
return result;
}

1
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h
View File

@ -35,6 +35,7 @@ struct pipe_ctx;
struct dc_crtc_timing_adjust;
struct dc_crtc_timing;
struct dc_state;
struct dc_surface_update;
struct dc_reg_helper_state {
bool gather_in_progress;

1
drivers/gpu/drm/amd/display/dc/dc_plane_priv.h
View File

@ -30,5 +30,6 @@
void dc_plane_construct(struct dc_context *ctx, struct dc_plane_state *plane_state);
void dc_plane_destruct(struct dc_plane_state *plane_state);
uint8_t dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane_state *plane_state);
#endif /* _DC_PLANE_PRIV_H_ */

2
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
View File

@ -956,7 +956,7 @@ void dcn32_init_hw(struct dc *dc)
dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;
if (dc->ctx->dmub_srv->dmub->fw_version <
DMUB_FW_VERSION(7, 0, 35)) {
DMUB_FW_VERSION(7, 0, 35)) {
dc->debug.force_disable_subvp = true;
dc->debug.disable_fpo_optimizations = true;
}

3
drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
View File

@ -482,7 +482,8 @@ void hwss_build_fast_sequence(struct dc *dc,
struct block_sequence block_sequence[],
unsigned int *num_steps,
struct pipe_ctx *pipe_ctx,
struct dc_stream_status *stream_status);
struct dc_stream_status *stream_status,
struct dc_state *context);
void hwss_send_dmcub_cmd(union block_sequence_params *params);