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drm/nv50: improve vram page table construction
This commit changes nouveau to construct PTEs which look very much like the ones the binary driver creates. I presume that filling multiple PTEs identically with length flags and the physical address of the start of a block of VRAM is a hint to the memory controller that it need not perform additional page table lookups for that range of addresses. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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4c27bd339d
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@ -285,23 +285,45 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
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uint32_t flags, uint64_t phys)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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unsigned pages;
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struct nouveau_gpuobj *pgt;
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unsigned block;
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int i;
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virt -= dev_priv->vm_vram_base;
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pages = size >> 16;
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virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
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size = (size >> 16) << 1;
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phys |= ((uint64_t)flags << 32) | 1;
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dev_priv->engine.instmem.prepare_access(dev, true);
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while (pages--) {
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struct nouveau_gpuobj *pt = dev_priv->vm_vram_pt[virt >> 29];
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unsigned pte = ((virt & 0x1fffffffULL) >> 16) << 1;
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unsigned offset_h = upper_32_bits(phys) & 0xff;
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while (size) {
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unsigned offset_h = upper_32_bits(phys);
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unsigned offset_l = lower_32_bits(phys);
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unsigned pte, end;
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nv_wo32(dev, pt, pte++, offset_l | 1);
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nv_wo32(dev, pt, pte++, offset_h | flags);
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for (i = 7; i >= 0; i--) {
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block = 1 << (i + 1);
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if (size >= block && !(virt & (block - 1)))
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break;
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}
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offset_l |= (i << 7);
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phys += (1 << 16);
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virt += (1 << 16);
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phys += block << 15;
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size -= block;
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while (block) {
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pgt = dev_priv->vm_vram_pt[virt >> 14];
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pte = virt & 0x3ffe;
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end = pte + block;
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if (end > 16384)
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end = 16384;
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block -= (end - pte);
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virt += (end - pte);
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while (pte < end) {
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nv_wo32(dev, pgt, pte++, offset_l);
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nv_wo32(dev, pgt, pte++, offset_h);
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}
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}
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}
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dev_priv->engine.instmem.finish_access(dev);
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