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mei: add trc detection register to sysfs

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The glitch detection HW (TRC) save it status information into
TRC status register.
Make it available to user-space via read-only sysfs file.
The TRC register is availab for PCH15 gen and newer, for older
platforms reading the sysfs file will fail with EOPNOTSUPP.

Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Link: https://lore.kernel.org/r/20191107104445.19101-1-tomas.winkler@intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Usyskin 2019-11-07 12:44:45 +02:00 committed by Greg Kroah-Hartman
parent 261e071acd
commit 52f6efdf80
7 changed files with 86 additions and 3 deletions
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10
Documentation/ABI/testing/sysfs-class-mei
View File

@ -80,3 +80,13 @@ Description: Display the ME device state.
DISABLED
POWER_DOWN
POWER_UP
What: /sys/class/mei/meiN/trc
Date: Nov 2019
KernelVersion: 5.5
Contact: Tomas Winkler <tomas.winkler@intel.com>
Description: Display trc status register content
The ME FW writes Glitch Detection HW (TRC)
status information into trc status register
for BIOS and OS to monitor fw health.

3
drivers/misc/mei/hw-me-regs.h
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@ -163,7 +163,8 @@ access to ME_CBD */
#define ME_IS_HRA 0x00000002
/* ME Interrupt Enable HRA - host read only access to ME_IE */
#define ME_IE_HRA 0x00000001
/* TRC control shadow register */
#define ME_TRC 0x00000030
/* H_HPG_CSR register bits */
#define H_HPG_CSR_PGIHEXR 0x00000001

34
drivers/misc/mei/hw-me.c
View File

@ -172,6 +172,27 @@ static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
}
/**
* mei_me_trc_status - read trc status register
*
* @dev: mei device
* @trc: trc status register value
*
* Return: 0 on success, error otherwise
*/
static int mei_me_trc_status(struct mei_device *dev, u32 *trc)
{
struct mei_me_hw *hw = to_me_hw(dev);
if (!hw->cfg->hw_trc_supported)
return -EOPNOTSUPP;
*trc = mei_me_reg_read(hw, ME_TRC);
trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc);
return 0;
}
/**
* mei_me_fw_status - read fw status register from pci config space
*
@ -1302,6 +1323,7 @@ end:
static const struct mei_hw_ops mei_me_hw_ops = {
.trc_status = mei_me_trc_status,
.fw_status = mei_me_fw_status,
.pg_state = mei_me_pg_state,
@ -1392,6 +1414,9 @@ static bool mei_me_fw_type_sps(struct pci_dev *pdev)
.dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
.dma_size[DMA_DSCR_CTRL] = PAGE_SIZE
#define MEI_CFG_TRC \
.hw_trc_supported = 1
/* ICH Legacy devices */
static const struct mei_cfg mei_me_ich_cfg = {
MEI_CFG_ICH_HFS,
@ -1440,6 +1465,14 @@ static const struct mei_cfg mei_me_pch12_cfg = {
MEI_CFG_DMA_128,
};
/* Tiger Lake and newer devices */
static const struct mei_cfg mei_me_pch15_cfg = {
MEI_CFG_PCH8_HFS,
MEI_CFG_FW_VER_SUPP,
MEI_CFG_DMA_128,
MEI_CFG_TRC,
};
/*
* mei_cfg_list - A list of platform platform specific configurations.
* Note: has to be synchronized with enum mei_cfg_idx.
@ -1454,6 +1487,7 @@ static const struct mei_cfg *const mei_cfg_list[] = {
[MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
[MEI_ME_PCH8_SPS_CFG] = &mei_me_pch8_sps_cfg,
[MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
};
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)

4
drivers/misc/mei/hw-me.h
View File

@ -21,12 +21,14 @@
* @quirk_probe: device exclusion quirk
* @dma_size: device DMA buffers size
* @fw_ver_supported: is fw version retrievable from FW
* @hw_trc_supported: does the hw support trc register
*/
struct mei_cfg {
const struct mei_fw_status fw_status;
bool (*quirk_probe)(struct pci_dev *pdev);
size_t dma_size[DMA_DSCR_NUM];
u32 fw_ver_supported:1;
u32 hw_trc_supported:1;
};
@ -78,6 +80,7 @@ struct mei_me_hw {
* servers platforms with quirk for
* SPS firmware exclusion.
* @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer
* @MEI_ME_PCH15_CFG: Platform Controller Hub Gen15 and newer
* @MEI_ME_NUM_CFG: Upper Sentinel.
*/
enum mei_cfg_idx {
@ -90,6 +93,7 @@ enum mei_cfg_idx {
MEI_ME_PCH8_CFG,
MEI_ME_PCH8_SPS_CFG,
MEI_ME_PCH12_CFG,
MEI_ME_PCH15_CFG,
MEI_ME_NUM_CFG,
};

24
drivers/misc/mei/main.c
View File

@ -700,6 +700,29 @@ static int mei_fasync(int fd, struct file *file, int band)
return fasync_helper(fd, file, band, &cl->ev_async);
}
/**
* trc_show - mei device trc attribute show method
*
* @device: device pointer
* @attr: attribute pointer
* @buf: char out buffer
*
* Return: number of the bytes printed into buf or error
*/
static ssize_t trc_show(struct device *device,
struct device_attribute *attr, char *buf)
{
struct mei_device *dev = dev_get_drvdata(device);
u32 trc;
int ret;
ret = mei_trc_status(dev, &trc);
if (ret)
return ret;
return sprintf(buf, "%08X\n", trc);
}
static DEVICE_ATTR_RO(trc);
/**
* fw_status_show - mei device fw_status attribute show method
*
@ -887,6 +910,7 @@ static struct attribute *mei_attrs[] = {
&dev_attr_tx_queue_limit.attr,
&dev_attr_fw_ver.attr,
&dev_attr_dev_state.attr,
&dev_attr_trc.attr,
NULL
};
ATTRIBUTE_GROUPS(mei);

10
drivers/misc/mei/mei_dev.h
View File

@ -260,6 +260,7 @@ struct mei_cl {
* @hw_config : configure hw
*
* @fw_status : get fw status registers
* @trc_status : get trc status register
* @pg_state : power gating state of the device
* @pg_in_transition : is device now in pg transition
* @pg_is_enabled : is power gating enabled
@ -290,6 +291,8 @@ struct mei_hw_ops {
int (*hw_config)(struct mei_device *dev);
int (*fw_status)(struct mei_device *dev, struct mei_fw_status *fw_sts);
int (*trc_status)(struct mei_device *dev, u32 *trc);
enum mei_pg_state (*pg_state)(struct mei_device *dev);
bool (*pg_in_transition)(struct mei_device *dev);
bool (*pg_is_enabled)(struct mei_device *dev);
@ -711,6 +714,13 @@ static inline int mei_count_full_read_slots(struct mei_device *dev)
return dev->ops->rdbuf_full_slots(dev);
}
static inline int mei_trc_status(struct mei_device *dev, u32 *trc)
{
if (dev->ops->trc_status)
return dev->ops->trc_status(dev, trc);
return -EOPNOTSUPP;
}
static inline int mei_fw_status(struct mei_device *dev,
struct mei_fw_status *fw_status)
{

4
drivers/misc/mei/pci-me.c
View File

@ -102,9 +102,9 @@ static const struct pci_device_id mei_me_pci_tbl[] = {
{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
/* required last entry */