Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-17 01:22:07 +00:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: reneas: rzg2: Add SDnH clocks

Browse Source 
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-9-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-10-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-11-wsa+renesas@sang-engineering.com
Link: https://lore.kernel.org/r/20211110191610.5664-12-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Wolfram Sang 2021-11-10 20:15:57 +01:00 committed by Geert Uytterhoeven
parent f9a2adcc9e
commit 52e844ee9a
4 changed files with 30 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -2276,7 +2276,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774A1_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2288,7 +2289,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774A1_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2300,7 +2302,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774A1_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2312,7 +2315,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774A1_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 311>;

12
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -2133,7 +2133,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2145,7 +2146,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2157,7 +2159,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2169,7 +2172,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 311>;

9
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -1626,7 +1626,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -1638,7 +1639,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -1650,7 +1652,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 311>;

12
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -2362,7 +2362,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774E1_CLK_SD0H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 314>;
@ -2375,7 +2376,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 313>;
clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774E1_CLK_SD1H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 313>;
@ -2388,7 +2390,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774E1_CLK_SD2H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 312>;
@ -2401,7 +2404,8 @@
"renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774E1_CLK_SD3H>;
clock-names = "core", "clkh";
max-frequency = <200000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 311>;