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drm/msm: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
8432a903fb
commit
52260ae4c4
@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
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Copyright (C) 2013-2016 by the following authors:
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Copyright (C) 2013-2017 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -352,6 +352,38 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
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#define REG_A2XX_RBBM_DEBUG 0x0000039b
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#define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c
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#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001
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#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002
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#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004
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#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008
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#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080
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#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100
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#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200
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#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000
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#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000
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#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000
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#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000
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#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000
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#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000
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#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000
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#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000
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#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000
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#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000
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#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000
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#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000
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#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000
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#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000
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#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000
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#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000
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#define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d
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@ -477,12 +509,43 @@ static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000
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#define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81
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#define REG_A2XX_PA_SU_FACE_DATA 0x00000c86
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#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0
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#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5
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static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
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{
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return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
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}
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#define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00
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#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4
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static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
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{
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return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
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}
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000
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#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12
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static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
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{
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return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
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}
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#define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01
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#define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0
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static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
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{
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return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
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}
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16
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static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
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{
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return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
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}
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#define REG_A2XX_SQ_DEBUG_MISC 0x00000d05
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@ -742,6 +805,24 @@ static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
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#define REG_A2XX_RB_BLEND_ALPHA 0x00002108
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#define REG_A2XX_RB_FOG_COLOR 0x00002109
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#define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff
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#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0
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static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
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{
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return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
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}
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#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00
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#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8
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static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
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{
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return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
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}
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#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000
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#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16
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static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
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{
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return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
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}
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#define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c
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#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
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@ -890,14 +971,146 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
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#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000
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#define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182
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#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff
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#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0
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static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
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{
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return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
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}
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#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000
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#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16
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static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
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{
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return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
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}
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#define REG_A2XX_SQ_WRAPPING_0 0x00002183
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
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}
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28
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static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
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}
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#define REG_A2XX_SQ_WRAPPING_1 0x00002184
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24
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static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
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{
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return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
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}
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000
|
||||
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28
|
||||
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_SQ_PS_PROGRAM 0x000021f6
|
||||
#define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff
|
||||
#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0
|
||||
static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
|
||||
}
|
||||
#define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000
|
||||
#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12
|
||||
static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
|
||||
#define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff
|
||||
#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0
|
||||
static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
|
||||
}
|
||||
#define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000
|
||||
#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12
|
||||
static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
|
||||
|
||||
@ -1304,6 +1517,14 @@ static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_a
|
||||
}
|
||||
|
||||
#define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293
|
||||
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001
|
||||
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e
|
||||
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1
|
||||
static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
|
||||
}
|
||||
#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100
|
||||
|
||||
#define REG_A2XX_VGT_ENHANCE 0x00002294
|
||||
|
||||
@ -1319,6 +1540,18 @@ static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
|
||||
#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400
|
||||
|
||||
#define REG_A2XX_PA_SC_AA_CONFIG 0x00002301
|
||||
#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007
|
||||
#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0
|
||||
static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
|
||||
}
|
||||
#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000
|
||||
#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13
|
||||
static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_PA_SU_VTX_CNTL 0x00002302
|
||||
#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001
|
||||
@ -1407,8 +1640,20 @@ static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
|
||||
#define REG_A2XX_PA_SC_AA_MASK 0x00002312
|
||||
|
||||
#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316
|
||||
#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007
|
||||
#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0
|
||||
static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317
|
||||
#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003
|
||||
#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0
|
||||
static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
|
||||
{
|
||||
return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
|
||||
}
|
||||
|
||||
#define REG_A2XX_RB_COPY_CONTROL 0x00002318
|
||||
#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007
|
||||
|
||||
@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@ -3010,11 +3010,11 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
|
||||
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
|
||||
|
||||
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
|
||||
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
|
||||
static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
|
||||
return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
|
||||
@ -3829,6 +3829,44 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
|
||||
|
||||
#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
|
||||
|
||||
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
|
||||
|
||||
#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
|
||||
|
||||
#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@ -421,6 +421,35 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
|
||||
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
|
||||
|
||||
#define REG_AXXX_CP_STAT 0x0000047f
|
||||
#define AXXX_CP_STAT_CP_BUSY 0x80000000
|
||||
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
|
||||
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
|
||||
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
|
||||
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
|
||||
#define AXXX_CP_STAT_ME_BUSY 0x04000000
|
||||
#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
|
||||
#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
|
||||
#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
|
||||
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
|
||||
#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
|
||||
#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
|
||||
#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
|
||||
#define AXXX_CP_STAT_PFP_BUSY 0x00020000
|
||||
#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
|
||||
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
|
||||
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
|
||||
#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
|
||||
#define AXXX_CP_STAT_CSF_BUSY 0x00000400
|
||||
#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
|
||||
#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
|
||||
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
|
||||
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
|
||||
#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
|
||||
#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
|
||||
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
|
||||
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
|
||||
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
|
||||
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
|
||||
|
||||
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
|
||||
|
||||
|
||||
@ -8,17 +8,17 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@ -67,10 +67,18 @@ enum vgt_event_type {
|
||||
PERFCOUNTER_STOP = 24,
|
||||
VS_FETCH_DONE = 27,
|
||||
FACENESS_FLUSH = 28,
|
||||
FLUSH_SO_0 = 17,
|
||||
FLUSH_SO_1 = 18,
|
||||
FLUSH_SO_2 = 19,
|
||||
FLUSH_SO_3 = 20,
|
||||
UNK_19 = 25,
|
||||
UNK_1C = 28,
|
||||
UNK_1D = 29,
|
||||
BLIT = 30,
|
||||
UNK_26 = 38,
|
||||
UNK_25 = 37,
|
||||
LRZ_FLUSH = 38,
|
||||
UNK_2C = 44,
|
||||
UNK_2D = 45,
|
||||
};
|
||||
|
||||
enum pc_di_primtype {
|
||||
@ -134,11 +142,13 @@ enum adreno_pm4_type3_packets {
|
||||
CP_WAIT_IB_PFD_COMPLETE = 93,
|
||||
CP_REG_RMW = 33,
|
||||
CP_SET_BIN_DATA = 47,
|
||||
CP_SET_BIN_DATA5 = 47,
|
||||
CP_REG_TO_MEM = 62,
|
||||
CP_MEM_WRITE = 61,
|
||||
CP_MEM_WRITE_CNTR = 79,
|
||||
CP_COND_EXEC = 68,
|
||||
CP_COND_WRITE = 69,
|
||||
CP_COND_WRITE5 = 69,
|
||||
CP_EVENT_WRITE = 70,
|
||||
CP_EVENT_WRITE_SHD = 88,
|
||||
CP_EVENT_WRITE_CFL = 89,
|
||||
@ -165,6 +175,7 @@ enum adreno_pm4_type3_packets {
|
||||
CP_SET_PROTECTED_MODE = 95,
|
||||
CP_BOOTSTRAP_UCODE = 111,
|
||||
CP_LOAD_STATE = 48,
|
||||
CP_LOAD_STATE4 = 48,
|
||||
CP_COND_INDIRECT_BUFFER_PFE = 58,
|
||||
CP_COND_INDIRECT_BUFFER_PFD = 50,
|
||||
CP_INDIRECT_BUFFER_PFE = 63,
|
||||
@ -204,6 +215,7 @@ enum adreno_pm4_type3_packets {
|
||||
CP_COMPUTE_CHECKPOINT = 110,
|
||||
CP_MEM_TO_MEM = 115,
|
||||
CP_BLIT = 44,
|
||||
CP_UNK_39 = 57,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
@ -239,21 +251,61 @@ enum adreno_state_src {
|
||||
SS_INDIRECT_STM = 6,
|
||||
};
|
||||
|
||||
enum a4xx_state_block {
|
||||
SB4_VS_TEX = 0,
|
||||
SB4_HS_TEX = 1,
|
||||
SB4_DS_TEX = 2,
|
||||
SB4_GS_TEX = 3,
|
||||
SB4_FS_TEX = 4,
|
||||
SB4_CS_TEX = 5,
|
||||
SB4_VS_SHADER = 8,
|
||||
SB4_HS_SHADER = 9,
|
||||
SB4_DS_SHADER = 10,
|
||||
SB4_GS_SHADER = 11,
|
||||
SB4_FS_SHADER = 12,
|
||||
SB4_CS_SHADER = 13,
|
||||
SB4_SSBO = 14,
|
||||
SB4_CS_SSBO = 15,
|
||||
};
|
||||
|
||||
enum a4xx_state_type {
|
||||
ST4_SHADER = 0,
|
||||
ST4_CONSTANTS = 1,
|
||||
};
|
||||
|
||||
enum a4xx_state_src {
|
||||
SS4_DIRECT = 0,
|
||||
SS4_INDIRECT = 2,
|
||||
};
|
||||
|
||||
enum a4xx_index_size {
|
||||
INDEX4_SIZE_8_BIT = 0,
|
||||
INDEX4_SIZE_16_BIT = 1,
|
||||
INDEX4_SIZE_32_BIT = 2,
|
||||
};
|
||||
|
||||
enum cp_cond_function {
|
||||
WRITE_ALWAYS = 0,
|
||||
WRITE_LT = 1,
|
||||
WRITE_LE = 2,
|
||||
WRITE_EQ = 3,
|
||||
WRITE_NE = 4,
|
||||
WRITE_GE = 5,
|
||||
WRITE_GT = 6,
|
||||
};
|
||||
|
||||
enum render_mode_cmd {
|
||||
BYPASS = 1,
|
||||
BINNING = 2,
|
||||
GMEM = 3,
|
||||
BLIT2D = 5,
|
||||
BLIT2DSCALE = 7,
|
||||
};
|
||||
|
||||
enum cp_blit_cmd {
|
||||
BLIT_OP_FILL = 0,
|
||||
BLIT_OP_BLIT = 1,
|
||||
BLIT_OP_COPY = 1,
|
||||
BLIT_OP_SCALE = 3,
|
||||
};
|
||||
|
||||
#define REG_CP_LOAD_STATE_0 0x00000000
|
||||
@ -296,12 +348,52 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
|
||||
return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE_2 0x00000002
|
||||
#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
|
||||
#define REG_CP_LOAD_STATE4_0 0x00000000
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x0000ffff
|
||||
#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
|
||||
return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
|
||||
#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
|
||||
static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
|
||||
#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
|
||||
static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
|
||||
#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
|
||||
static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE4_1 0x00000001
|
||||
#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
|
||||
#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
|
||||
}
|
||||
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
|
||||
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
|
||||
static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_LOAD_STATE4_2 0x00000002
|
||||
#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DRAW_INDX_0 0x00000000
|
||||
@ -570,6 +662,52 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
||||
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_0 0x00000000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
|
||||
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
|
||||
}
|
||||
#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
|
||||
#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
|
||||
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_1 0x00000001
|
||||
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_2 0x00000002
|
||||
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_3 0x00000003
|
||||
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_SET_BIN_DATA5_4 0x00000004
|
||||
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
|
||||
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
|
||||
static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
||||
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
||||
@ -594,6 +732,128 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
||||
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_MEM_TO_MEM_0 0x00000000
|
||||
#define CP_MEM_TO_MEM_0_NEG_A 0x00000001
|
||||
#define CP_MEM_TO_MEM_0_NEG_B 0x00000002
|
||||
#define CP_MEM_TO_MEM_0_NEG_C 0x00000004
|
||||
#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
|
||||
|
||||
#define REG_CP_COND_WRITE_0 0x00000000
|
||||
#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
|
||||
#define CP_COND_WRITE_0_FUNCTION__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
|
||||
}
|
||||
#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
|
||||
#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
|
||||
|
||||
#define REG_CP_COND_WRITE_1 0x00000001
|
||||
#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_2 0x00000002
|
||||
#define CP_COND_WRITE_2_REF__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_2_REF__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_3 0x00000003
|
||||
#define CP_COND_WRITE_3_MASK__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_3_MASK__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_4 0x00000004
|
||||
#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE_5 0x00000005
|
||||
#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
|
||||
#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_0 0x00000000
|
||||
#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
|
||||
#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
|
||||
}
|
||||
#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
|
||||
#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
|
||||
|
||||
#define REG_CP_COND_WRITE5_1 0x00000001
|
||||
#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_2 0x00000002
|
||||
#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_3 0x00000003
|
||||
#define CP_COND_WRITE5_3_REF__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_3_REF__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_4 0x00000004
|
||||
#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_4_MASK__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_5 0x00000005
|
||||
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_6 0x00000006
|
||||
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COND_WRITE5_7 0x00000007
|
||||
#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
|
||||
#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
|
||||
static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
|
||||
|
||||
#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
|
||||
@ -645,6 +905,7 @@ static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_CP_SET_RENDER_MODE_3 0x00000003
|
||||
#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
|
||||
#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
|
||||
|
||||
#define REG_CP_SET_RENDER_MODE_4 0x00000004
|
||||
@ -673,6 +934,50 @@ static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
|
||||
return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
|
||||
#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
|
||||
#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
|
||||
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
|
||||
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
|
||||
#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
|
||||
#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
|
||||
static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
|
||||
|
||||
#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
|
||||
@ -698,6 +1003,7 @@ static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
|
||||
{
|
||||
return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
|
||||
}
|
||||
#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
|
||||
|
||||
#define REG_CP_EVENT_WRITE_1 0x00000001
|
||||
#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
|
||||
@ -781,5 +1087,31 @@ static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
|
||||
return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_0 0x00000000
|
||||
|
||||
#define REG_CP_EXEC_CS_1 0x00000001
|
||||
#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_2 0x00000002
|
||||
#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_EXEC_CS_3 0x00000003
|
||||
#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
|
||||
#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
|
||||
static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* ADRENO_PM4_XML */
|
||||
|
||||
@ -8,8 +8,17 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-01-11 05:19:19)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
@ -111,6 +111,32 @@ static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
|
||||
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
|
||||
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
|
||||
|
||||
#define REG_HDMI_INFOFRAME_CTRL1 0x00000030
|
||||
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
|
||||
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
|
||||
}
|
||||
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
|
||||
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
|
||||
}
|
||||
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
|
||||
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
|
||||
}
|
||||
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
|
||||
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
|
||||
static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
|
||||
}
|
||||
|
||||
#define REG_HDMI_GEN_PKT_CTRL 0x00000034
|
||||
#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
|
||||
#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
|
||||
@ -463,7 +489,7 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
|
||||
#define REG_HDMI_CEC_RD_FILTER 0x000002b0
|
||||
|
||||
#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
|
||||
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
|
||||
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
|
||||
#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
|
||||
static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
|
||||
{
|
||||
@ -477,13 +503,13 @@ static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_HDMI_ACTIVE_VSYNC 0x000002b8
|
||||
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff
|
||||
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
|
||||
#define HDMI_ACTIVE_VSYNC_START__SHIFT 0
|
||||
static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
|
||||
}
|
||||
#define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000
|
||||
#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
|
||||
#define HDMI_ACTIVE_VSYNC_END__SHIFT 16
|
||||
static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
|
||||
{
|
||||
@ -491,13 +517,13 @@ static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
|
||||
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff
|
||||
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
|
||||
#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
|
||||
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
|
||||
}
|
||||
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000
|
||||
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
|
||||
#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
|
||||
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
|
||||
{
|
||||
@ -505,13 +531,13 @@ static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_HDMI_TOTAL 0x000002c0
|
||||
#define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff
|
||||
#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
|
||||
#define HDMI_TOTAL_H_TOTAL__SHIFT 0
|
||||
static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
|
||||
{
|
||||
return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
|
||||
}
|
||||
#define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000
|
||||
#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
|
||||
#define HDMI_TOTAL_V_TOTAL__SHIFT 16
|
||||
static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
|
||||
{
|
||||
@ -519,7 +545,7 @@ static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
|
||||
}
|
||||
|
||||
#define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
|
||||
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff
|
||||
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
|
||||
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
|
||||
static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
|
||||
{
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
@ -8,9 +8,17 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-01-11 05:19:19)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
|
||||
- /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
|
||||
@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
|
||||
git clone https://github.com/freedreno/envytools.git
|
||||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2017 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user