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Merge branches 'clk-cleanup', 'clk-aspeed', 'clk-dt', 'clk-renesas' and 'clk-skyworks' into clk-next
- Support for i3c clks on Aspeed ast2600 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators * clk-cleanup: clk: microchip: fix potential UAF in auxdev release callback clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: stm32h7: Remove an unused field in struct stm32_fractional_divider clk: tegra20: fix gcc-7 constant overflow warning clock: milbeaut: use devm_platform_get_and_ioremap_resource() clk: Print an info line before disabling unused clocks clk: ti: Use of_address_to_resource() clk: remove unnecessary (void*) conversions clk: at91: clk-sam9x60-pll: fix return value check clk: visconti: remove unused visconti_pll_provider::regmap * clk-aspeed: dt-bindings: clock: ast2600: Expand comment on reset definitions clk: ast2600: Add comment about combined clock + reset handling dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions clk: ast2600: Add full configs for I3C clocks dt-bindings: clock: ast2600: Add top-level I3C clock clk: ast2600: allow empty entries in aspeed_g6_gates * clk-dt: clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt() clk: Use of_property_present() for testing DT property presence * clk-renesas: clk: renesas: r8a77980: Add I2C5 clock clk: rs9: Add support for 9FGV0441 clk: rs9: Support device specific dif bit calculation dt-bindings: clk: rs9: Add 9FGV0441 clk: rs9: Check for vendor/device ID clk: renesas: Convert to platform remove callback returning void clk: renesas: r9a06g032: Improve clock tables clk: renesas: r9a06g032: Document structs clk: renesas: r9a06g032: Drop unused fields clk: renesas: r9a06g032: Improve readability clk: renesas: r8a77980: Add Z2 clock clk: renesas: r8a77970: Add Z2 clock clk: renesas: r8a77995: Fix VIN parent clock clk: renesas: r8a77980: Add VIN clocks clk: renesas: r8a779g0: Add VIN clocks clk: renesas: r8a779g0: Add ISPCS clocks clk: renesas: r8a779g0: Add CSI-2 clocks clk: renesas: r8a779g0: Add thermal clock clk: renesas: r8a779g0: Add Audio clocks clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H * clk-skyworks: clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators dt-bindings: clk: si521xx: Add Skyworks Si521xx I2C PCIe clock generators
This commit is contained in:
Stephen Boyd
commit
4ec6a2f957
@ -16,6 +16,11 @@ description: |
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- 9FGV0241:
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0 -- DIF0
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1 -- DIF1
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- 9FGV0441:
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0 -- DIF0
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1 -- DIF1
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2 -- DIF2
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3 -- DIF3
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maintainers:
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- Marek Vasut <marex@denx.de>
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@ -24,6 +29,7 @@ properties:
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compatible:
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enum:
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- renesas,9fgv0241
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- renesas,9fgv0441
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reg:
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description: I2C device address
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@ -0,0 +1,59 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/skyworks,si521xx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Skyworks Si521xx I2C PCIe clock generators
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description: |
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The Skyworks Si521xx are I2C PCIe clock generators providing
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from 4 to 9 output clocks.
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maintainers:
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- Marek Vasut <marex@denx.de>
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properties:
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compatible:
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enum:
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- skyworks,si52144
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- skyworks,si52146
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- skyworks,si52147
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reg:
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const: 0x6b
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: XTal input clock
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skyworks,out-amplitude-microvolt:
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enum: [ 300000, 400000, 500000, 600000, 700000, 800000, 900000, 1000000 ]
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description: Output clock signal amplitude
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-generator@6b {
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compatible = "skyworks,si52144";
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reg = <0x6b>;
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#clock-cells = <1>;
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clocks = <&ref25m>;
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};
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};
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...
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@ -367,6 +367,15 @@ config COMMON_CLK_RS9_PCIE
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This driver supports the Renesas 9-series PCIe clock generator
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models 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ.
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config COMMON_CLK_SI521XX
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tristate "Clock driver for SkyWorks Si521xx PCIe clock generators"
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depends on I2C
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depends on OF
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select REGMAP_I2C
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help
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This driver supports the SkyWorks Si521xx PCIe clock generator
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models Si52144/Si52146/Si52147.
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config COMMON_CLK_VC5
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tristate "Clock driver for IDT VersaClock 5,6 devices"
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depends on I2C
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@ -72,6 +72,7 @@ obj-$(CONFIG_COMMON_CLK_TPS68470) += clk-tps68470.o
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obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
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obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o
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obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
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obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
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obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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@ -668,7 +668,7 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
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ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
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parent_rate, true);
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if (ret <= 0) {
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if (ret < 0) {
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hw = ERR_PTR(ret);
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goto free;
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}
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@ -15,7 +15,11 @@
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#include "clk-aspeed.h"
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#define ASPEED_G6_NUM_CLKS 71
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/*
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* This includes the gates (configured from aspeed_g6_gates), plus the
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* explicitly-configured clocks (ASPEED_CLK_HPLL and up).
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*/
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#define ASPEED_G6_NUM_CLKS 72
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#define ASPEED_G6_SILICON_REV 0x014
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#define CHIP_REVISION_ID GENMASK(23, 16)
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@ -32,6 +36,20 @@
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#define ASPEED_G6_CLK_SELECTION1 0x300
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#define ASPEED_G6_CLK_SELECTION2 0x304
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#define ASPEED_G6_CLK_SELECTION4 0x310
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#define ASPEED_G6_CLK_SELECTION5 0x314
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#define I3C_CLK_SELECTION_SHIFT 31
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#define I3C_CLK_SELECTION BIT(31)
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#define I3C_CLK_SELECT_HCLK (0 << I3C_CLK_SELECTION_SHIFT)
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#define I3C_CLK_SELECT_APLL_DIV (1 << I3C_CLK_SELECTION_SHIFT)
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#define APLL_DIV_SELECTION_SHIFT 28
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#define APLL_DIV_SELECTION GENMASK(30, 28)
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#define APLL_DIV_2 (0b001 << APLL_DIV_SELECTION_SHIFT)
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#define APLL_DIV_3 (0b010 << APLL_DIV_SELECTION_SHIFT)
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#define APLL_DIV_4 (0b011 << APLL_DIV_SELECTION_SHIFT)
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#define APLL_DIV_5 (0b100 << APLL_DIV_SELECTION_SHIFT)
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#define APLL_DIV_6 (0b101 << APLL_DIV_SELECTION_SHIFT)
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#define APLL_DIV_7 (0b110 << APLL_DIV_SELECTION_SHIFT)
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#define APLL_DIV_8 (0b111 << APLL_DIV_SELECTION_SHIFT)
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#define ASPEED_HPLL_PARAM 0x200
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#define ASPEED_APLL_PARAM 0x210
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@ -55,6 +73,27 @@ static void __iomem *scu_g6_base;
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static u8 soc_rev;
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/*
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* The majority of the clocks in the system are gates paired with a reset
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* controller that holds the IP in reset; this is represented by the @reset_idx
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* member of entries here.
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*
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* This borrows from clk_hw_register_gate, but registers two 'gates', one
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* to control the clock enable register and the other to control the reset
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* IP. This allows us to enforce the ordering:
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*
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* 1. Place IP in reset
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* 2. Enable clock
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* 3. Delay
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* 4. Release reset
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*
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* Consequently, if reset_idx is set, reset control is implicit: the clock
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* consumer does not need its own reset handling, as enabling the clock will
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* also deassert reset.
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*
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* There are some gates that do not have an associated reset; these are
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* handled by using -1 as the index for the reset, and the consumer must
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* explictly assert/deassert reset lines as required.
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*
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* Clocks marked with CLK_IS_CRITICAL:
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*
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* ref0 and ref1 are essential for the SoC to operate
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@ -97,14 +136,13 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = {
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[ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
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/* Reserved 38 RSA: no longer used */
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/* Reserved 39 */
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[ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
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[ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
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[ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
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[ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
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[ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
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[ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
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[ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
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[ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
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[ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", "i3cclk", 0 }, /* I3C0 */
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[ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", "i3cclk", 0 }, /* I3C1 */
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[ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", "i3cclk", 0 }, /* I3C2 */
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[ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", "i3cclk", 0 }, /* I3C3 */
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[ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", "i3cclk", 0 }, /* I3C4 */
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[ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", "i3cclk", 0 }, /* I3C5 */
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/* Reserved: 46 & 47 */
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[ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
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[ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
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[ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
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@ -652,6 +690,9 @@ static int aspeed_g6_clk_probe(struct platform_device *pdev)
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const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
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u32 gate_flags;
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if (!gd->name)
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continue;
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/*
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* Special case: the USB port 1 clock (bit 14) is always
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* working the opposite way from the other ones.
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@ -772,6 +813,14 @@ static void __init aspeed_g6_cc(struct regmap *map)
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/* USB 2.0 port1 phy 40MHz clock */
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hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
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aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
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/* i3c clock: source from apll, divide by 8 */
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regmap_update_bits(map, ASPEED_G6_CLK_SELECTION5,
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I3C_CLK_SELECTION | APLL_DIV_SELECTION,
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I3C_CLK_SELECT_APLL_DIV | APLL_DIV_8);
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hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8);
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aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw;
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};
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static void __init aspeed_g6_cc_init(struct device_node *np)
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@ -560,14 +560,12 @@ static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors,
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static int m10v_clk_probe(struct platform_device *pdev)
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{
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int id;
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struct resource *res;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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void __iomem *base;
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const char *parent_name;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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if (IS_ERR(base))
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return PTR_ERR(base);
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@ -6,6 +6,7 @@
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* - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
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* Currently supported:
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* - 9FGV0241
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* - 9FGV0441
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*
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* Copyright (C) 2022 Marek Vasut <marex@denx.de>
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*/
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@ -18,7 +19,6 @@
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#include <linux/regmap.h>
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#define RS9_REG_OE 0x0
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#define RS9_REG_OE_DIF_OE(n) BIT((n) + 1)
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#define RS9_REG_SS 0x1
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#define RS9_REG_SS_AMP_0V6 0x0
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#define RS9_REG_SS_AMP_0V7 0x1
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@ -31,9 +31,6 @@
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#define RS9_REG_SS_SSC_MASK (3 << 3)
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#define RS9_REG_SS_SSC_LOCK BIT(5)
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#define RS9_REG_SR 0x2
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#define RS9_REG_SR_2V0_DIF(n) 0
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#define RS9_REG_SR_3V0_DIF(n) BIT((n) + 1)
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#define RS9_REG_SR_DIF_MASK(n) BIT((n) + 1)
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#define RS9_REG_REF 0x3
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#define RS9_REG_REF_OE BIT(4)
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#define RS9_REG_REF_OD BIT(5)
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@ -45,22 +42,31 @@
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#define RS9_REG_DID 0x6
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#define RS9_REG_BCP 0x7
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#define RS9_REG_VID_IDT 0x01
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#define RS9_REG_DID_TYPE_FGV (0x0 << RS9_REG_DID_TYPE_SHIFT)
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#define RS9_REG_DID_TYPE_DBV (0x1 << RS9_REG_DID_TYPE_SHIFT)
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#define RS9_REG_DID_TYPE_DMV (0x2 << RS9_REG_DID_TYPE_SHIFT)
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#define RS9_REG_DID_TYPE_SHIFT 0x6
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/* Supported Renesas 9-series models. */
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enum rs9_model {
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RENESAS_9FGV0241,
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RENESAS_9FGV0441,
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};
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/* Structure to describe features of a particular 9-series model */
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struct rs9_chip_info {
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const enum rs9_model model;
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unsigned int num_clks;
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u8 did;
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};
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struct rs9_driver_data {
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struct i2c_client *client;
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struct regmap *regmap;
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const struct rs9_chip_info *chip_info;
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struct clk_hw *clk_dif[2];
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struct clk_hw *clk_dif[4];
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u8 pll_amplitude;
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u8 pll_ssc;
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u8 clk_dif_sr;
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@ -151,17 +157,29 @@ static const struct regmap_config rs9_regmap_config = {
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.reg_read = rs9_regmap_i2c_read,
|
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};
|
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|
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static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx)
|
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{
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enum rs9_model model = rs9->chip_info->model;
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|
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if (model == RENESAS_9FGV0241)
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return BIT(idx) + 1;
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else if (model == RENESAS_9FGV0441)
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return BIT(idx);
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return 0;
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}
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static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
|
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{
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struct i2c_client *client = rs9->client;
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u8 dif = rs9_calc_dif(rs9, idx);
|
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unsigned char name[5] = "DIF0";
|
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struct device_node *np;
|
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int ret;
|
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u32 sr;
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/* Set defaults */
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rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
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rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx);
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rs9->clk_dif_sr |= dif;
|
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snprintf(name, 5, "DIF%d", idx);
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np = of_get_child_by_name(client->dev.of_node, name);
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@ -173,11 +191,9 @@ static int rs9_get_output_config(struct rs9_driver_data *rs9, int idx)
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of_node_put(np);
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if (!ret) {
|
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if (sr == 2000000) { /* 2V/ns */
|
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rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
|
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rs9->clk_dif_sr |= RS9_REG_SR_2V0_DIF(idx);
|
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rs9->clk_dif_sr &= ~dif;
|
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} else if (sr == 3000000) { /* 3V/ns (default) */
|
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rs9->clk_dif_sr &= ~RS9_REG_SR_DIF_MASK(idx);
|
||||
rs9->clk_dif_sr |= RS9_REG_SR_3V0_DIF(idx);
|
||||
rs9->clk_dif_sr |= dif;
|
||||
} else
|
||||
ret = dev_err_probe(&client->dev, -EINVAL,
|
||||
"Invalid renesas,slew-rate value\n");
|
||||
@ -248,11 +264,13 @@ static void rs9_update_config(struct rs9_driver_data *rs9)
|
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}
|
||||
|
||||
for (i = 0; i < rs9->chip_info->num_clks; i++) {
|
||||
if (rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i))
|
||||
u8 dif = rs9_calc_dif(rs9, i);
|
||||
|
||||
if (rs9->clk_dif_sr & dif)
|
||||
continue;
|
||||
|
||||
regmap_update_bits(rs9->regmap, RS9_REG_SR, RS9_REG_SR_3V0_DIF(i),
|
||||
rs9->clk_dif_sr & RS9_REG_SR_3V0_DIF(i));
|
||||
regmap_update_bits(rs9->regmap, RS9_REG_SR, dif,
|
||||
rs9->clk_dif_sr & dif);
|
||||
}
|
||||
}
|
||||
|
||||
@ -269,6 +287,7 @@ static int rs9_probe(struct i2c_client *client)
|
||||
{
|
||||
unsigned char name[5] = "DIF0";
|
||||
struct rs9_driver_data *rs9;
|
||||
unsigned int vid, did;
|
||||
struct clk_hw *hw;
|
||||
int i, ret;
|
||||
|
||||
@ -305,6 +324,20 @@ static int rs9_probe(struct i2c_client *client)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = regmap_read(rs9->regmap, RS9_REG_VID, &vid);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = regmap_read(rs9->regmap, RS9_REG_DID, &did);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (vid != RS9_REG_VID_IDT || did != rs9->chip_info->did)
|
||||
return dev_err_probe(&client->dev, -ENODEV,
|
||||
"Incorrect VID/DID: %#02x, %#02x. Expected %#02x, %#02x\n",
|
||||
vid, did, RS9_REG_VID_IDT,
|
||||
rs9->chip_info->did);
|
||||
|
||||
/* Register clock */
|
||||
for (i = 0; i < rs9->chip_info->num_clks; i++) {
|
||||
snprintf(name, 5, "DIF%d", i);
|
||||
@ -348,16 +381,25 @@ static int __maybe_unused rs9_resume(struct device *dev)
|
||||
static const struct rs9_chip_info renesas_9fgv0241_info = {
|
||||
.model = RENESAS_9FGV0241,
|
||||
.num_clks = 2,
|
||||
.did = RS9_REG_DID_TYPE_FGV | 0x02,
|
||||
};
|
||||
|
||||
static const struct rs9_chip_info renesas_9fgv0441_info = {
|
||||
.model = RENESAS_9FGV0441,
|
||||
.num_clks = 4,
|
||||
.did = RS9_REG_DID_TYPE_FGV | 0x04,
|
||||
};
|
||||
|
||||
static const struct i2c_device_id rs9_id[] = {
|
||||
{ "9fgv0241", .driver_data = RENESAS_9FGV0241 },
|
||||
{ "9fgv0441", .driver_data = RENESAS_9FGV0441 },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, rs9_id);
|
||||
|
||||
static const struct of_device_id clk_rs9_of_match[] = {
|
||||
{ .compatible = "renesas,9fgv0241", .data = &renesas_9fgv0241_info },
|
||||
{ .compatible = "renesas,9fgv0441", .data = &renesas_9fgv0441_info },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
|
||||
|
||||
395
drivers/clk/clk-si521xx.c
Normal file
395
drivers/clk/clk-si521xx.c
Normal file
@ -0,0 +1,395 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Driver for Skyworks Si521xx PCIe clock generator driver
|
||||
*
|
||||
* The following series can be supported:
|
||||
* - Si52144 - 4x DIFF
|
||||
* - Si52146 - 6x DIFF
|
||||
* - Si52147 - 9x DIFF
|
||||
* Currently tested:
|
||||
* - Si52144
|
||||
*
|
||||
* Copyright (C) 2022 Marek Vasut <marex@denx.de>
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bitrev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
/* OE1 and OE2 register */
|
||||
#define SI521XX_REG_OE(n) (((n) & 0x1) + 1)
|
||||
#define SI521XX_REG_ID 0x3
|
||||
#define SI521XX_REG_ID_PROG GENMASK(7, 4)
|
||||
#define SI521XX_REG_ID_VENDOR GENMASK(3, 0)
|
||||
#define SI521XX_REG_BC 0x4
|
||||
#define SI521XX_REG_DA 0x5
|
||||
#define SI521XX_REG_DA_AMP_SEL BIT(7)
|
||||
#define SI521XX_REG_DA_AMP_MASK GENMASK(6, 4)
|
||||
#define SI521XX_REG_DA_AMP_MIN 300000
|
||||
#define SI521XX_REG_DA_AMP_DEFAULT 800000
|
||||
#define SI521XX_REG_DA_AMP_MAX 1000000
|
||||
#define SI521XX_REG_DA_AMP_STEP 100000
|
||||
#define SI521XX_REG_DA_AMP(UV) \
|
||||
FIELD_PREP(SI521XX_REG_DA_AMP_MASK, \
|
||||
((UV) - SI521XX_REG_DA_AMP_MIN) / SI521XX_REG_DA_AMP_STEP)
|
||||
#define SI521XX_REG_DA_UNKNOWN BIT(3) /* Always set */
|
||||
|
||||
/* Count of populated OE bits in control register ref, 1 and 2 */
|
||||
#define SI521XX_OE_MAP(cr1, cr2) (((cr2) << 8) | (cr1))
|
||||
#define SI521XX_OE_MAP_GET_OE(oe, map) (((map) >> (((oe) - 1) * 8)) & 0xff)
|
||||
|
||||
#define SI521XX_DIFF_MULT 4
|
||||
#define SI521XX_DIFF_DIV 1
|
||||
|
||||
/* Supported Skyworks Si521xx models. */
|
||||
enum si521xx_model {
|
||||
SI52144 = 0x44,
|
||||
SI52146 = 0x46,
|
||||
SI52147 = 0x47,
|
||||
};
|
||||
|
||||
struct si521xx;
|
||||
|
||||
struct si_clk {
|
||||
struct clk_hw hw;
|
||||
struct si521xx *si;
|
||||
u8 reg;
|
||||
u8 bit;
|
||||
};
|
||||
|
||||
struct si521xx {
|
||||
struct i2c_client *client;
|
||||
struct regmap *regmap;
|
||||
struct si_clk clk_dif[9];
|
||||
u16 chip_info;
|
||||
u8 pll_amplitude;
|
||||
};
|
||||
|
||||
/*
|
||||
* Si521xx i2c regmap
|
||||
*/
|
||||
static const struct regmap_range si521xx_readable_ranges[] = {
|
||||
regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_DA),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table si521xx_readable_table = {
|
||||
.yes_ranges = si521xx_readable_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(si521xx_readable_ranges),
|
||||
};
|
||||
|
||||
static const struct regmap_range si521xx_writeable_ranges[] = {
|
||||
regmap_reg_range(SI521XX_REG_OE(0), SI521XX_REG_OE(1)),
|
||||
regmap_reg_range(SI521XX_REG_BC, SI521XX_REG_DA),
|
||||
};
|
||||
|
||||
static const struct regmap_access_table si521xx_writeable_table = {
|
||||
.yes_ranges = si521xx_writeable_ranges,
|
||||
.n_yes_ranges = ARRAY_SIZE(si521xx_writeable_ranges),
|
||||
};
|
||||
|
||||
static int si521xx_regmap_i2c_write(void *context, unsigned int reg,
|
||||
unsigned int val)
|
||||
{
|
||||
struct i2c_client *i2c = context;
|
||||
const u8 data[3] = { reg, 1, val };
|
||||
const int count = ARRAY_SIZE(data);
|
||||
int ret;
|
||||
|
||||
ret = i2c_master_send(i2c, data, count);
|
||||
if (ret == count)
|
||||
return 0;
|
||||
else if (ret < 0)
|
||||
return ret;
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static int si521xx_regmap_i2c_read(void *context, unsigned int reg,
|
||||
unsigned int *val)
|
||||
{
|
||||
struct i2c_client *i2c = context;
|
||||
struct i2c_msg xfer[2];
|
||||
u8 txdata = reg;
|
||||
u8 rxdata[2];
|
||||
int ret;
|
||||
|
||||
xfer[0].addr = i2c->addr;
|
||||
xfer[0].flags = 0;
|
||||
xfer[0].len = 1;
|
||||
xfer[0].buf = (void *)&txdata;
|
||||
|
||||
xfer[1].addr = i2c->addr;
|
||||
xfer[1].flags = I2C_M_RD;
|
||||
xfer[1].len = 2;
|
||||
xfer[1].buf = (void *)rxdata;
|
||||
|
||||
ret = i2c_transfer(i2c->adapter, xfer, 2);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (ret != 2)
|
||||
return -EIO;
|
||||
|
||||
/*
|
||||
* Byte 0 is transfer length, which is always 1 due
|
||||
* to BCP register programming to 1 in si521xx_probe(),
|
||||
* ignore it and use data from Byte 1.
|
||||
*/
|
||||
*val = rxdata[1];
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct regmap_config si521xx_regmap_config = {
|
||||
.reg_bits = 8,
|
||||
.val_bits = 8,
|
||||
.cache_type = REGCACHE_NONE,
|
||||
.max_register = SI521XX_REG_DA,
|
||||
.rd_table = &si521xx_readable_table,
|
||||
.wr_table = &si521xx_writeable_table,
|
||||
.reg_write = si521xx_regmap_i2c_write,
|
||||
.reg_read = si521xx_regmap_i2c_read,
|
||||
};
|
||||
|
||||
static unsigned long si521xx_diff_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
unsigned long long rate;
|
||||
|
||||
rate = (unsigned long long)parent_rate * SI521XX_DIFF_MULT;
|
||||
do_div(rate, SI521XX_DIFF_DIV);
|
||||
return (unsigned long)rate;
|
||||
}
|
||||
|
||||
static long si521xx_diff_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
unsigned long best_parent;
|
||||
|
||||
best_parent = (rate / SI521XX_DIFF_MULT) * SI521XX_DIFF_DIV;
|
||||
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
|
||||
|
||||
return (*prate / SI521XX_DIFF_DIV) * SI521XX_DIFF_MULT;
|
||||
}
|
||||
|
||||
static int si521xx_diff_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
/*
|
||||
* We must report success but we can do so unconditionally because
|
||||
* si521xx_diff_round_rate returns values that ensure this call is a
|
||||
* nop.
|
||||
*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define to_si521xx_clk(_hw) container_of(_hw, struct si_clk, hw)
|
||||
|
||||
static int si521xx_diff_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct si_clk *si_clk = to_si521xx_clk(hw);
|
||||
struct si521xx *si = si_clk->si;
|
||||
|
||||
regmap_set_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void si521xx_diff_unprepare(struct clk_hw *hw)
|
||||
{
|
||||
struct si_clk *si_clk = to_si521xx_clk(hw);
|
||||
struct si521xx *si = si_clk->si;
|
||||
|
||||
regmap_clear_bits(si->regmap, SI521XX_REG_OE(si_clk->reg), si_clk->bit);
|
||||
}
|
||||
|
||||
static const struct clk_ops si521xx_diff_clk_ops = {
|
||||
.round_rate = si521xx_diff_round_rate,
|
||||
.set_rate = si521xx_diff_set_rate,
|
||||
.recalc_rate = si521xx_diff_recalc_rate,
|
||||
.prepare = si521xx_diff_prepare,
|
||||
.unprepare = si521xx_diff_unprepare,
|
||||
};
|
||||
|
||||
static int si521xx_get_common_config(struct si521xx *si)
|
||||
{
|
||||
struct i2c_client *client = si->client;
|
||||
struct device_node *np = client->dev.of_node;
|
||||
unsigned int amp;
|
||||
int ret;
|
||||
|
||||
/* Set defaults */
|
||||
si->pll_amplitude = SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT);
|
||||
|
||||
/* Output clock amplitude */
|
||||
ret = of_property_read_u32(np, "skyworks,out-amplitude-microvolt",
|
||||
&);
|
||||
if (!ret) {
|
||||
if (amp < SI521XX_REG_DA_AMP_MIN || amp > SI521XX_REG_DA_AMP_MAX ||
|
||||
amp % SI521XX_REG_DA_AMP_STEP) {
|
||||
return dev_err_probe(&client->dev, -EINVAL,
|
||||
"Invalid skyworks,out-amplitude-microvolt value\n");
|
||||
}
|
||||
si->pll_amplitude = SI521XX_REG_DA_AMP(amp);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void si521xx_update_config(struct si521xx *si)
|
||||
{
|
||||
/* If amplitude is non-default, update it. */
|
||||
if (si->pll_amplitude == SI521XX_REG_DA_AMP(SI521XX_REG_DA_AMP_DEFAULT))
|
||||
return;
|
||||
|
||||
regmap_update_bits(si->regmap, SI521XX_REG_DA,
|
||||
SI521XX_REG_DA_AMP_MASK, si->pll_amplitude);
|
||||
}
|
||||
|
||||
static void si521xx_diff_idx_to_reg_bit(const u16 chip_info, const int idx,
|
||||
struct si_clk *clk)
|
||||
{
|
||||
unsigned long mask;
|
||||
int oe, b, ctr = 0;
|
||||
|
||||
for (oe = 1; oe <= 2; oe++) {
|
||||
mask = bitrev8(SI521XX_OE_MAP_GET_OE(oe, chip_info));
|
||||
for_each_set_bit(b, &mask, 8) {
|
||||
if (ctr++ != idx)
|
||||
continue;
|
||||
clk->reg = SI521XX_REG_OE(oe);
|
||||
clk->bit = 7 - b;
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct clk_hw *
|
||||
si521xx_of_clk_get(struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
struct si521xx *si = data;
|
||||
unsigned int idx = clkspec->args[0];
|
||||
|
||||
return &si->clk_dif[idx].hw;
|
||||
}
|
||||
|
||||
static int si521xx_probe(struct i2c_client *client)
|
||||
{
|
||||
const u16 chip_info = (u16)(uintptr_t)device_get_match_data(&client->dev);
|
||||
const struct clk_parent_data clk_parent_data = { .index = 0 };
|
||||
struct si521xx *si;
|
||||
unsigned char name[6] = "DIFF0";
|
||||
struct clk_init_data init = {};
|
||||
int i, ret;
|
||||
|
||||
if (!chip_info)
|
||||
return -EINVAL;
|
||||
|
||||
si = devm_kzalloc(&client->dev, sizeof(*si), GFP_KERNEL);
|
||||
if (!si)
|
||||
return -ENOMEM;
|
||||
|
||||
i2c_set_clientdata(client, si);
|
||||
si->client = client;
|
||||
|
||||
/* Fetch common configuration from DT (if specified) */
|
||||
ret = si521xx_get_common_config(si);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
si->regmap = devm_regmap_init(&client->dev, NULL, client,
|
||||
&si521xx_regmap_config);
|
||||
if (IS_ERR(si->regmap))
|
||||
return dev_err_probe(&client->dev, PTR_ERR(si->regmap),
|
||||
"Failed to allocate register map\n");
|
||||
|
||||
/* Always read back 1 Byte via I2C */
|
||||
ret = regmap_write(si->regmap, SI521XX_REG_BC, 1);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Register clock */
|
||||
for (i = 0; i < hweight16(chip_info); i++) {
|
||||
memset(&init, 0, sizeof(init));
|
||||
snprintf(name, 6, "DIFF%d", i);
|
||||
init.name = name;
|
||||
init.ops = &si521xx_diff_clk_ops;
|
||||
init.parent_data = &clk_parent_data;
|
||||
init.num_parents = 1;
|
||||
init.flags = CLK_SET_RATE_PARENT;
|
||||
|
||||
si->clk_dif[i].hw.init = &init;
|
||||
si->clk_dif[i].si = si;
|
||||
|
||||
si521xx_diff_idx_to_reg_bit(chip_info, i, &si->clk_dif[i]);
|
||||
|
||||
ret = devm_clk_hw_register(&client->dev, &si->clk_dif[i].hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(&client->dev, si521xx_of_clk_get, si);
|
||||
if (!ret)
|
||||
si521xx_update_config(si);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __maybe_unused si521xx_suspend(struct device *dev)
|
||||
{
|
||||
struct si521xx *si = dev_get_drvdata(dev);
|
||||
|
||||
regcache_cache_only(si->regmap, true);
|
||||
regcache_mark_dirty(si->regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused si521xx_resume(struct device *dev)
|
||||
{
|
||||
struct si521xx *si = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
regcache_cache_only(si->regmap, false);
|
||||
ret = regcache_sync(si->regmap);
|
||||
if (ret)
|
||||
dev_err(dev, "Failed to restore register map: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id si521xx_id[] = {
|
||||
{ "si52144", .driver_data = SI521XX_OE_MAP(0x5, 0xc0) },
|
||||
{ "si52146", .driver_data = SI521XX_OE_MAP(0x15, 0xe0) },
|
||||
{ "si52147", .driver_data = SI521XX_OE_MAP(0x17, 0xf8) },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, si521xx_id);
|
||||
|
||||
static const struct of_device_id clk_si521xx_of_match[] = {
|
||||
{ .compatible = "skyworks,si52144", .data = (void *)SI521XX_OE_MAP(0x5, 0xc0) },
|
||||
{ .compatible = "skyworks,si52146", .data = (void *)SI521XX_OE_MAP(0x15, 0xe0) },
|
||||
{ .compatible = "skyworks,si52147", .data = (void *)SI521XX_OE_MAP(0x15, 0xf8) },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, clk_si521xx_of_match);
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(si521xx_pm_ops, si521xx_suspend, si521xx_resume);
|
||||
|
||||
static struct i2c_driver si521xx_driver = {
|
||||
.driver = {
|
||||
.name = "clk-si521xx",
|
||||
.pm = &si521xx_pm_ops,
|
||||
.of_match_table = clk_si521xx_of_match,
|
||||
},
|
||||
.probe_new = si521xx_probe,
|
||||
.id_table = si521xx_id,
|
||||
};
|
||||
module_i2c_driver(si521xx_driver);
|
||||
|
||||
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
|
||||
MODULE_DESCRIPTION("Skyworks Si521xx PCIe clock generator driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -667,7 +667,6 @@ struct stm32_fractional_divider {
|
||||
void __iomem *mreg;
|
||||
u8 mshift;
|
||||
u8 mwidth;
|
||||
u32 mmask;
|
||||
|
||||
void __iomem *nreg;
|
||||
u8 nshift;
|
||||
|
||||
@ -1406,6 +1406,8 @@ static int __init clk_disable_unused(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
pr_info("clk: Disabling unused clocks\n");
|
||||
|
||||
clk_prepare_lock();
|
||||
|
||||
hlist_for_each_entry(core, &clk_root_list, child_node)
|
||||
@ -3194,7 +3196,7 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
|
||||
static int clk_summary_show(struct seq_file *s, void *data)
|
||||
{
|
||||
struct clk_core *c;
|
||||
struct hlist_head **lists = (struct hlist_head **)s->private;
|
||||
struct hlist_head **lists = s->private;
|
||||
|
||||
seq_puts(s, " enable prepare protect duty hardware\n");
|
||||
seq_puts(s, " clock count count count rate accuracy phase cycle enable\n");
|
||||
@ -3253,7 +3255,7 @@ static int clk_dump_show(struct seq_file *s, void *data)
|
||||
{
|
||||
struct clk_core *c;
|
||||
bool first_node = true;
|
||||
struct hlist_head **lists = (struct hlist_head **)s->private;
|
||||
struct hlist_head **lists = s->private;
|
||||
|
||||
seq_putc(s, '{');
|
||||
clk_prepare_lock();
|
||||
@ -4880,8 +4882,8 @@ static struct device_node *get_clk_provider_node(struct device *dev)
|
||||
np = dev->of_node;
|
||||
parent_np = dev->parent ? dev->parent->of_node : NULL;
|
||||
|
||||
if (!of_find_property(np, "#clock-cells", NULL))
|
||||
if (of_find_property(parent_np, "#clock-cells", NULL))
|
||||
if (!of_property_present(np, "#clock-cells"))
|
||||
if (of_property_present(parent_np, "#clock-cells"))
|
||||
np = parent_np;
|
||||
|
||||
return np;
|
||||
|
||||
@ -75,13 +75,13 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
|
||||
base = of_iomap(node, 0);
|
||||
if (!base) {
|
||||
pr_err("%s(): ioremap failed\n", __func__);
|
||||
return;
|
||||
goto out_node_put;
|
||||
}
|
||||
|
||||
num_clocks = of_clk_get_parent_count(node);
|
||||
if (!num_clocks) {
|
||||
pr_err("%s(): failed to get clocks property\n", __func__);
|
||||
return;
|
||||
goto err;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_clocks; i++) {
|
||||
@ -102,6 +102,13 @@ void fhctl_parse_dt(const u8 *compatible_node, struct mtk_pllfh_data *pllfhs,
|
||||
pllfh->state.ssc_rate = ssc_rate;
|
||||
pllfh->state.base = base;
|
||||
}
|
||||
|
||||
out_node_put:
|
||||
of_node_put(node);
|
||||
return;
|
||||
err:
|
||||
iounmap(base);
|
||||
goto out_node_put;
|
||||
}
|
||||
|
||||
static void pllfh_init(struct mtk_fh *fh, struct mtk_pllfh_data *pllfh_data)
|
||||
|
||||
@ -374,14 +374,13 @@ static void mpfs_reset_unregister_adev(void *_adev)
|
||||
struct auxiliary_device *adev = _adev;
|
||||
|
||||
auxiliary_device_delete(adev);
|
||||
auxiliary_device_uninit(adev);
|
||||
}
|
||||
|
||||
static void mpfs_reset_adev_release(struct device *dev)
|
||||
{
|
||||
struct auxiliary_device *adev = to_auxiliary_dev(dev);
|
||||
|
||||
auxiliary_device_uninit(adev);
|
||||
|
||||
kfree(adev);
|
||||
}
|
||||
|
||||
|
||||
@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
|
||||
@ -72,6 +72,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
|
||||
DEF_RATE(".oco", CLK_OCO, 32768),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1),
|
||||
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
@ -150,11 +151,27 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
||||
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
|
||||
DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("vin15", 604, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin14", 605, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin13", 608, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin12", 612, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin11", 618, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
|
||||
DEF_MOD("vin10", 625, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin9", 627, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin8", 628, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
|
||||
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin6", 805, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin5", 806, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin4", 807, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin3", 808, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin2", 809, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin1", 810, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("vin0", 811, R8A77980_CLK_S2D1),
|
||||
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
|
||||
@ -173,6 +190,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
|
||||
DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
|
||||
DEF_MOD("can-fd", 914, R8A77980_CLK_S3D2),
|
||||
DEF_MOD("rpc-if", 917, R8A77980_CLK_RPCD2),
|
||||
DEF_MOD("i2c5", 919, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
|
||||
|
||||
@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
|
||||
|
||||
@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
|
||||
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
|
||||
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
|
||||
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
|
||||
DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
|
||||
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
|
||||
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
|
||||
|
||||
@ -165,6 +166,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
|
||||
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
|
||||
DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
|
||||
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
|
||||
@ -181,6 +184,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
|
||||
DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
|
||||
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
|
||||
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
|
||||
@ -202,6 +207,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
|
||||
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
|
||||
DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
|
||||
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
|
||||
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
|
||||
@ -213,6 +234,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
|
||||
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
|
||||
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
|
||||
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@ -29,69 +29,189 @@
|
||||
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
|
||||
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
|
||||
|
||||
struct r9a06g032_gate {
|
||||
u16 gate, reset, ready, midle,
|
||||
scon, mirack, mistat;
|
||||
/**
|
||||
* struct regbit - describe one bit in a register
|
||||
* @reg: offset of register relative to base address,
|
||||
* expressed in units of 32-bit words (not bytes),
|
||||
* @bit: which bit (0 to 31) in the register
|
||||
*
|
||||
* This structure is used to compactly encode the location
|
||||
* of a single bit in a register. Five bits are needed to
|
||||
* encode the bit number. With uint16_t data type, this
|
||||
* leaves 11 bits to encode a register offset up to 2047.
|
||||
*
|
||||
* Since registers are aligned on 32-bit boundaries, the
|
||||
* offset will be specified in 32-bit words rather than bytes.
|
||||
* This allows encoding an offset up to 0x1FFC (8188) bytes.
|
||||
*
|
||||
* Helper macro RB() takes care of converting the register
|
||||
* offset from bytes to 32-bit words.
|
||||
*/
|
||||
struct regbit {
|
||||
u16 bit:5;
|
||||
u16 reg:11;
|
||||
};
|
||||
|
||||
/* This is used to describe a clock for instantiation */
|
||||
#define RB(_reg, _bit) ((struct regbit) { \
|
||||
.reg = (_reg) / 4, \
|
||||
.bit = (_bit) \
|
||||
})
|
||||
|
||||
/**
|
||||
* struct r9a06g032_gate - clock-related control bits
|
||||
* @gate: clock enable/disable
|
||||
* @reset: clock module reset (active low)
|
||||
* @ready: enables NoC forwarding of read/write requests to device,
|
||||
* (eg. device is ready to handle read/write requests)
|
||||
* @midle: request to idle the NoC interconnect
|
||||
*
|
||||
* Each of these fields describes a single bit in a register,
|
||||
* which controls some aspect of clock gating. The @gate field
|
||||
* is mandatory, this one enables/disables the clock. The
|
||||
* other fields are optional, with zero indicating "not used".
|
||||
*
|
||||
* In most cases there is a @reset bit which needs to be
|
||||
* de-asserted to bring the module out of reset.
|
||||
*
|
||||
* Modules may also need to signal when they are @ready to
|
||||
* handle requests (read/writes) from the NoC interconnect.
|
||||
*
|
||||
* Similarly, the @midle bit is used to idle the master.
|
||||
*/
|
||||
struct r9a06g032_gate {
|
||||
struct regbit gate, reset, ready, midle;
|
||||
/* Unused fields omitted to save space */
|
||||
/* struct regbit scon, mirack, mistat */;
|
||||
};
|
||||
|
||||
enum gate_type {
|
||||
K_GATE = 0, /* gate which enable/disable */
|
||||
K_FFC, /* fixed factor clock */
|
||||
K_DIV, /* divisor */
|
||||
K_BITSEL, /* special for UARTs */
|
||||
K_DUALGATE /* special for UARTs */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct r9a06g032_clkdesc - describe a single clock
|
||||
* @name: string describing this clock
|
||||
* @managed: boolean indicating if this clock should be
|
||||
* started/stopped as part of power management
|
||||
* @type: see enum @gate_type
|
||||
* @index: the ID of this clock element
|
||||
* @source: the ID+1 of the parent clock element.
|
||||
* Root clock uses ID of ~0 (PARENT_ID);
|
||||
* @gate: clock enable/disable
|
||||
* @div_min: smallest permitted clock divider
|
||||
* @div_max: largest permitted clock divider
|
||||
* @reg: clock divider register offset, in 32-bit words
|
||||
* @div_table: optional list of fixed clock divider values;
|
||||
* must be in ascending order, zero for unused
|
||||
* @div: divisor for fixed-factor clock
|
||||
* @mul: multiplier for fixed-factor clock
|
||||
* @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7
|
||||
* @sel: select either g1/r1 or g2/r2 as clock source
|
||||
* @g1: 1st source gate (clock enable/disable)
|
||||
* @r1: 1st source reset (module reset)
|
||||
* @g2: 2nd source gate (clock enable/disable)
|
||||
* @r2: 2nd source reset (module reset)
|
||||
*
|
||||
* Describes a single element in the clock tree hierarchy.
|
||||
* As there are quite a large number of clock elements, this
|
||||
* structure is packed tightly to conserve space.
|
||||
*/
|
||||
struct r9a06g032_clkdesc {
|
||||
const char *name;
|
||||
uint32_t managed: 1;
|
||||
uint32_t type: 3;
|
||||
uint32_t index: 8;
|
||||
uint32_t source : 8; /* source index + 1 (0 == none) */
|
||||
/* these are used to populate the bitsel struct */
|
||||
uint32_t managed:1;
|
||||
enum gate_type type:3;
|
||||
uint32_t index:8;
|
||||
uint32_t source:8; /* source index + 1 (0 == none) */
|
||||
union {
|
||||
/* type = K_GATE */
|
||||
struct r9a06g032_gate gate;
|
||||
/* for dividers */
|
||||
/* type = K_DIV */
|
||||
struct {
|
||||
unsigned int div_min : 10, div_max : 10, reg: 10;
|
||||
unsigned int div_min:10, div_max:10, reg:10;
|
||||
u16 div_table[4];
|
||||
};
|
||||
/* For fixed-factor ones */
|
||||
/* type = K_FFC */
|
||||
struct {
|
||||
u16 div, mul;
|
||||
};
|
||||
/* for dual gate */
|
||||
/* type = K_DUALGATE */
|
||||
struct {
|
||||
uint16_t group : 1;
|
||||
u16 sel, g1, r1, g2, r2;
|
||||
uint16_t group:1;
|
||||
struct regbit sel, g1, r1, g2, r2;
|
||||
} dual;
|
||||
};
|
||||
};
|
||||
|
||||
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
|
||||
{ .gate = _clk, .reset = _rst, \
|
||||
.ready = _rdy, .midle = _midle, \
|
||||
.scon = _scon, .mirack = _mirack, .mistat = _mistat }
|
||||
#define D_GATE(_idx, _n, _src, ...) \
|
||||
{ .type = K_GATE, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.gate = I_GATE(__VA_ARGS__) }
|
||||
#define D_MODULE(_idx, _n, _src, ...) \
|
||||
{ .type = K_GATE, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.managed = 1, .gate = I_GATE(__VA_ARGS__) }
|
||||
#define D_ROOT(_idx, _n, _mul, _div) \
|
||||
{ .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
|
||||
.div = _div, .mul = _mul }
|
||||
#define D_FFC(_idx, _n, _src, _div) \
|
||||
{ .type = K_FFC, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.div = _div, .mul = 1}
|
||||
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
|
||||
{ .type = K_DIV, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.reg = _reg, .div_min = _min, .div_max = _max, \
|
||||
.div_table = { __VA_ARGS__ } }
|
||||
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
|
||||
{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, .name = _n, \
|
||||
.dual = { .group = _g, \
|
||||
.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
|
||||
|
||||
enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
|
||||
/*
|
||||
* The last three arguments are not currently used,
|
||||
* but are kept in the r9a06g032_clocks table below.
|
||||
*/
|
||||
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
|
||||
.gate = _clk, \
|
||||
.reset = _rst, \
|
||||
.ready = _rdy, \
|
||||
.midle = _midle, \
|
||||
/* .scon = _scon, */ \
|
||||
/* .mirack = _mirack, */ \
|
||||
/* .mistat = _mistat */ \
|
||||
}
|
||||
#define D_GATE(_idx, _n, _src, ...) { \
|
||||
.type = K_GATE, \
|
||||
.index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, \
|
||||
.name = _n, \
|
||||
.gate = I_GATE(__VA_ARGS__) \
|
||||
}
|
||||
#define D_MODULE(_idx, _n, _src, ...) { \
|
||||
.type = K_GATE, \
|
||||
.index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, \
|
||||
.name = _n, \
|
||||
.managed = 1, \
|
||||
.gate = I_GATE(__VA_ARGS__) \
|
||||
}
|
||||
#define D_ROOT(_idx, _n, _mul, _div) { \
|
||||
.type = K_FFC, \
|
||||
.index = R9A06G032_##_idx, \
|
||||
.name = _n, \
|
||||
.div = _div, \
|
||||
.mul = _mul \
|
||||
}
|
||||
#define D_FFC(_idx, _n, _src, _div) { \
|
||||
.type = K_FFC, \
|
||||
.index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, \
|
||||
.name = _n, \
|
||||
.div = _div, \
|
||||
.mul = 1 \
|
||||
}
|
||||
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
|
||||
.type = K_DIV, \
|
||||
.index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, \
|
||||
.name = _n, \
|
||||
.reg = _reg, \
|
||||
.div_min = _min, \
|
||||
.div_max = _max, \
|
||||
.div_table = { __VA_ARGS__ } \
|
||||
}
|
||||
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
|
||||
.type = K_DUALGATE, \
|
||||
.index = R9A06G032_##_idx, \
|
||||
.source = 1 + R9A06G032_##_src, \
|
||||
.name = _n, \
|
||||
.dual = { \
|
||||
.group = _g, \
|
||||
.g1 = _g1, \
|
||||
.r1 = _r1, \
|
||||
.g2 = _g2, \
|
||||
.r2 = _r2 \
|
||||
}, \
|
||||
}
|
||||
|
||||
/* Internal clock IDs */
|
||||
#define R9A06G032_CLKOUT 0
|
||||
@ -160,58 +280,160 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
||||
D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
|
||||
D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
|
||||
D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
|
||||
D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
|
||||
D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
|
||||
D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
|
||||
D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
|
||||
D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
|
||||
D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
|
||||
D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
|
||||
D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
|
||||
D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
|
||||
D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),
|
||||
RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),
|
||||
RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),
|
||||
RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),
|
||||
RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),
|
||||
RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),
|
||||
RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),
|
||||
RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),
|
||||
RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),
|
||||
RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),
|
||||
RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),
|
||||
RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
|
||||
RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
|
||||
RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),
|
||||
RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),
|
||||
RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),
|
||||
RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),
|
||||
RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),
|
||||
RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),
|
||||
RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),
|
||||
RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),
|
||||
RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),
|
||||
RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),
|
||||
RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),
|
||||
RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),
|
||||
RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),
|
||||
RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),
|
||||
RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),
|
||||
RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),
|
||||
RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),
|
||||
RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),
|
||||
RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
|
||||
RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
|
||||
RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),
|
||||
RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),
|
||||
RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),
|
||||
RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),
|
||||
RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),
|
||||
RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
|
||||
D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
|
||||
D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
|
||||
D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
|
||||
D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
|
||||
D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
|
||||
D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
|
||||
D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
|
||||
D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
|
||||
D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
|
||||
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
|
||||
D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),
|
||||
RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),
|
||||
RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),
|
||||
D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),
|
||||
RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),
|
||||
RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),
|
||||
RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),
|
||||
RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),
|
||||
D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),
|
||||
RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),
|
||||
RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),
|
||||
RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),
|
||||
RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),
|
||||
RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),
|
||||
RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),
|
||||
RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),
|
||||
RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),
|
||||
RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),
|
||||
RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),
|
||||
RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),
|
||||
D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),
|
||||
RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),
|
||||
RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),
|
||||
D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
|
||||
RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),
|
||||
RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),
|
||||
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
|
||||
RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),
|
||||
RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
|
||||
D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
|
||||
D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
|
||||
@ -219,67 +441,187 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
||||
D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
|
||||
D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
|
||||
D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
|
||||
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
|
||||
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
|
||||
D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
|
||||
RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),
|
||||
RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
|
||||
RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),
|
||||
RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),
|
||||
RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),
|
||||
RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
|
||||
RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),
|
||||
RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),
|
||||
RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),
|
||||
RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
|
||||
D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
|
||||
D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
|
||||
D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
|
||||
D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
|
||||
D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
|
||||
D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
|
||||
D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
|
||||
D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
|
||||
D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
|
||||
D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
|
||||
D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
|
||||
D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
|
||||
D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
|
||||
D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
|
||||
D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
|
||||
D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
|
||||
D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
|
||||
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
|
||||
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
|
||||
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
|
||||
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0),
|
||||
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
|
||||
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
|
||||
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
|
||||
D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
|
||||
D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
|
||||
D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),
|
||||
RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),
|
||||
RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),
|
||||
D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),
|
||||
RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),
|
||||
RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),
|
||||
RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),
|
||||
RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),
|
||||
RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),
|
||||
RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),
|
||||
RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),
|
||||
RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),
|
||||
RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),
|
||||
RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),
|
||||
RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),
|
||||
D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),
|
||||
RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),
|
||||
RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),
|
||||
D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),
|
||||
RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),
|
||||
RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),
|
||||
D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),
|
||||
RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),
|
||||
RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),
|
||||
D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),
|
||||
RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),
|
||||
RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),
|
||||
D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),
|
||||
RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),
|
||||
RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),
|
||||
D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),
|
||||
RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),
|
||||
RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),
|
||||
RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),
|
||||
RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),
|
||||
RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),
|
||||
D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),
|
||||
RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),
|
||||
RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),
|
||||
RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),
|
||||
RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),
|
||||
RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),
|
||||
RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),
|
||||
RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),
|
||||
RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),
|
||||
D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),
|
||||
RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),
|
||||
RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),
|
||||
D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),
|
||||
RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),
|
||||
RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),
|
||||
D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),
|
||||
RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),
|
||||
RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),
|
||||
RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),
|
||||
RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),
|
||||
RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),
|
||||
RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),
|
||||
RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),
|
||||
RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),
|
||||
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),
|
||||
RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),
|
||||
RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),
|
||||
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),
|
||||
RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),
|
||||
RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),
|
||||
RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
|
||||
RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),
|
||||
RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),
|
||||
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
|
||||
RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),
|
||||
RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),
|
||||
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),
|
||||
RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),
|
||||
RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),
|
||||
RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),
|
||||
RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),
|
||||
RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),
|
||||
RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),
|
||||
RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),
|
||||
RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),
|
||||
RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),
|
||||
RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),
|
||||
RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),
|
||||
RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),
|
||||
RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),
|
||||
RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),
|
||||
RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),
|
||||
RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),
|
||||
RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),
|
||||
RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),
|
||||
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
|
||||
/*
|
||||
* These are not hardware clocks, but are needed to handle the special
|
||||
* case where we have a 'selector bit' that doesn't just change the
|
||||
@ -291,7 +633,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
||||
.type = K_BITSEL,
|
||||
.source = 1 + R9A06G032_DIV_UART,
|
||||
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
|
||||
.dual.sel = ((0x34 / 4) << 5) | 30,
|
||||
.dual.sel = RB(0x34, 30),
|
||||
.dual.group = 0,
|
||||
},
|
||||
{
|
||||
@ -300,17 +642,25 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
|
||||
.type = K_BITSEL,
|
||||
.source = 1 + R9A06G032_DIV_P2_PG,
|
||||
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
|
||||
.dual.sel = ((0xec / 4) << 5) | 24,
|
||||
.dual.sel = RB(0xec, 24),
|
||||
.dual.group = 1,
|
||||
},
|
||||
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
|
||||
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
|
||||
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
|
||||
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
|
||||
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
|
||||
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
|
||||
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
|
||||
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
|
||||
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0,
|
||||
RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),
|
||||
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0,
|
||||
RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),
|
||||
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0,
|
||||
RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),
|
||||
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1,
|
||||
RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),
|
||||
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1,
|
||||
RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),
|
||||
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1,
|
||||
RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),
|
||||
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1,
|
||||
RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),
|
||||
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1,
|
||||
RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),
|
||||
};
|
||||
|
||||
struct r9a06g032_priv {
|
||||
@ -343,26 +693,26 @@ int r9a06g032_sysctrl_set_dmamux(u32 mask, u32 val)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
|
||||
|
||||
/* register/bit pairs are encoded as an uint16_t */
|
||||
static void
|
||||
clk_rdesc_set(struct r9a06g032_priv *clocks,
|
||||
u16 one, unsigned int on)
|
||||
static void clk_rdesc_set(struct r9a06g032_priv *clocks,
|
||||
struct regbit rb, unsigned int on)
|
||||
{
|
||||
u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
|
||||
u32 val = readl(reg);
|
||||
u32 __iomem *reg = clocks->reg + (rb.reg * 4);
|
||||
u32 val;
|
||||
|
||||
val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
|
||||
if (!rb.reg && !rb.bit)
|
||||
return;
|
||||
|
||||
val = readl(reg);
|
||||
val = (val & ~BIT(rb.bit)) | ((!!on) << rb.bit);
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
static int
|
||||
clk_rdesc_get(struct r9a06g032_priv *clocks,
|
||||
uint16_t one)
|
||||
static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb)
|
||||
{
|
||||
u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
|
||||
u32 __iomem *reg = clocks->reg + (rb.reg * 4);
|
||||
u32 val = readl(reg);
|
||||
|
||||
return !!(val & (1U << (one & 0x1f)));
|
||||
return !!(val & BIT(rb.bit));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -464,13 +814,12 @@ r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
WARN_ON(!g->gate);
|
||||
WARN_ON(!g->gate.reg && !g->gate.bit);
|
||||
|
||||
spin_lock_irqsave(&clocks->lock, flags);
|
||||
clk_rdesc_set(clocks, g->gate, on);
|
||||
/* De-assert reset */
|
||||
if (g->reset)
|
||||
clk_rdesc_set(clocks, g->reset, 1);
|
||||
clk_rdesc_set(clocks, g->reset, 1);
|
||||
spin_unlock_irqrestore(&clocks->lock, flags);
|
||||
|
||||
/* Hardware manual recommends 5us delay after enabling clock & reset */
|
||||
@ -480,15 +829,12 @@ r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
|
||||
* associated SLVRDY bit in the System Controller that needs to be set
|
||||
* so that the FlexWAY bus fabric passes on the read/write requests.
|
||||
*/
|
||||
if (g->ready || g->midle) {
|
||||
spin_lock_irqsave(&clocks->lock, flags);
|
||||
if (g->ready)
|
||||
clk_rdesc_set(clocks, g->ready, on);
|
||||
/* Clear 'Master Idle Request' bit */
|
||||
if (g->midle)
|
||||
clk_rdesc_set(clocks, g->midle, !on);
|
||||
spin_unlock_irqrestore(&clocks->lock, flags);
|
||||
}
|
||||
spin_lock_irqsave(&clocks->lock, flags);
|
||||
clk_rdesc_set(clocks, g->ready, on);
|
||||
/* Clear 'Master Idle Request' bit */
|
||||
clk_rdesc_set(clocks, g->midle, !on);
|
||||
spin_unlock_irqrestore(&clocks->lock, flags);
|
||||
|
||||
/* Note: We don't wait for FlexWAY Socket Connection signal */
|
||||
}
|
||||
|
||||
@ -512,7 +858,7 @@ static int r9a06g032_clk_gate_is_enabled(struct clk_hw *hw)
|
||||
struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
|
||||
|
||||
/* if clock is in reset, the gate might be on, and still not 'be' on */
|
||||
if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
|
||||
if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
|
||||
return 0;
|
||||
|
||||
return clk_rdesc_get(g->clocks, g->gate.gate);
|
||||
@ -751,7 +1097,7 @@ struct r9a06g032_clk_bitsel {
|
||||
struct clk_hw hw;
|
||||
struct r9a06g032_priv *clocks;
|
||||
u16 index;
|
||||
u16 selector; /* selector register + bit */
|
||||
struct regbit selector; /* selector register + bit */
|
||||
};
|
||||
|
||||
#define to_clk_bitselect(_hw) \
|
||||
@ -820,7 +1166,7 @@ struct r9a06g032_clk_dualgate {
|
||||
struct clk_hw hw;
|
||||
struct r9a06g032_priv *clocks;
|
||||
u16 index;
|
||||
u16 selector; /* selector register + bit */
|
||||
struct regbit selector; /* selector register + bit */
|
||||
struct r9a06g032_gate gate[2];
|
||||
};
|
||||
|
||||
@ -873,7 +1219,7 @@ static struct clk *
|
||||
r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
|
||||
const char *parent_name,
|
||||
const struct r9a06g032_clkdesc *desc,
|
||||
uint16_t sel)
|
||||
struct regbit sel)
|
||||
{
|
||||
struct r9a06g032_clk_dualgate *g;
|
||||
struct clk *clk;
|
||||
@ -951,7 +1297,7 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
|
||||
struct clk **clks;
|
||||
struct clk *mclk;
|
||||
unsigned int i;
|
||||
u16 uart_group_sel[2];
|
||||
struct regbit uart_group_sel[2];
|
||||
int error;
|
||||
|
||||
clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
|
||||
|
||||
@ -125,15 +125,13 @@ static int rcar_usb2_clock_sel_resume(struct device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
|
||||
static void rcar_usb2_clock_sel_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
of_clk_del_provider(dev->of_node);
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
||||
@ -215,7 +213,7 @@ static struct platform_driver rcar_usb2_clock_sel_driver = {
|
||||
.pm = &rcar_usb2_clock_sel_pm_ops,
|
||||
},
|
||||
.probe = rcar_usb2_clock_sel_probe,
|
||||
.remove = rcar_usb2_clock_sel_remove,
|
||||
.remove_new = rcar_usb2_clock_sel_remove,
|
||||
};
|
||||
builtin_platform_driver(rcar_usb2_clock_sel_driver);
|
||||
|
||||
|
||||
@ -61,7 +61,7 @@ static const u16 mstpsr_for_gen4[] = {
|
||||
0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
|
||||
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
|
||||
0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
|
||||
0x2E60, 0x2E64, 0x2E68, 0x2E6C,
|
||||
0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -77,7 +77,7 @@ static const u16 mstpcr_for_gen4[] = {
|
||||
0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
|
||||
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
|
||||
0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
|
||||
0x2D60, 0x2D64, 0x2D68, 0x2D6C,
|
||||
0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -103,7 +103,7 @@ static const u16 srcr_for_gen4[] = {
|
||||
0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
|
||||
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
|
||||
0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
|
||||
0x2C60, 0x2C64, 0x2C68, 0x2C6C,
|
||||
0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -119,7 +119,7 @@ static const u16 srstclr_for_gen4[] = {
|
||||
0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
|
||||
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
|
||||
0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
|
||||
0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
|
||||
0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4,
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
|
||||
menuconfig CLK_SIFIVE
|
||||
bool "SiFive SoC driver support"
|
||||
depends on SOC_SIFIVE || COMPILE_TEST
|
||||
default SOC_SIFIVE
|
||||
depends on ARCH_SIFIVE || COMPILE_TEST
|
||||
default ARCH_SIFIVE
|
||||
help
|
||||
SoC drivers for SiFive Linux-capable SoCs.
|
||||
|
||||
@ -11,7 +11,7 @@ if CLK_SIFIVE
|
||||
|
||||
config CLK_SIFIVE_PRCI
|
||||
bool "PRCI driver for SiFive SoCs"
|
||||
default SOC_SIFIVE
|
||||
default ARCH_SIFIVE
|
||||
select RESET_CONTROLLER
|
||||
select RESET_SIMPLE
|
||||
select CLK_ANALOGBITS_WRPLL_CLN28HPC
|
||||
|
||||
@ -44,7 +44,7 @@ int sprd_clk_regmap_init(struct platform_device *pdev,
|
||||
struct device_node *node = dev->of_node, *np;
|
||||
struct regmap *regmap;
|
||||
|
||||
if (of_find_property(node, "sprd,syscon", NULL)) {
|
||||
if (of_property_present(node, "sprd,syscon")) {
|
||||
regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon");
|
||||
if (IS_ERR(regmap)) {
|
||||
pr_err("%s: failed to get syscon regmap\n", __func__);
|
||||
|
||||
@ -21,24 +21,24 @@
|
||||
#define MISC_CLK_ENB 0x48
|
||||
|
||||
#define OSC_CTRL 0x50
|
||||
#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
|
||||
#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
|
||||
#define OSC_CTRL_OSC_FREQ_MASK (3u<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30)
|
||||
#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30)
|
||||
#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK)
|
||||
|
||||
#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28)
|
||||
#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28)
|
||||
|
||||
#define OSC_FREQ_DET 0x58
|
||||
#define OSC_FREQ_DET_TRIG (1<<31)
|
||||
#define OSC_FREQ_DET_TRIG (1u<<31)
|
||||
|
||||
#define OSC_FREQ_DET_STATUS 0x5c
|
||||
#define OSC_FREQ_DET_BUSY (1<<31)
|
||||
#define OSC_FREQ_DET_CNT_MASK 0xFFFF
|
||||
#define OSC_FREQ_DET_BUSYu (1<<31)
|
||||
#define OSC_FREQ_DET_CNT_MASK 0xFFFFu
|
||||
|
||||
#define TEGRA20_CLK_PERIPH_BANKS 3
|
||||
|
||||
|
||||
@ -512,16 +512,16 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
|
||||
struct clk_hw_omap *hw;
|
||||
struct clk *clk;
|
||||
struct omap_clkctrl_clk *clkctrl_clk = NULL;
|
||||
const __be32 *addrp;
|
||||
bool legacy_naming;
|
||||
const char *clkctrl_name;
|
||||
u32 addr;
|
||||
int ret;
|
||||
char *c;
|
||||
u16 soc_mask = 0;
|
||||
struct resource res;
|
||||
|
||||
addrp = of_get_address(node, 0, NULL, NULL);
|
||||
addr = (u32)of_translate_address(node, addrp);
|
||||
of_address_to_resource(node, 0, &res);
|
||||
addr = (u32)res.start;
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP4
|
||||
if (of_machine_is_compatible("ti,omap4"))
|
||||
|
||||
@ -15,7 +15,6 @@
|
||||
|
||||
struct visconti_pll_provider {
|
||||
void __iomem *reg_base;
|
||||
struct regmap *regmap;
|
||||
struct clk_hw_onecell_data clk_data;
|
||||
struct device_node *node;
|
||||
};
|
||||
|
||||
@ -57,8 +57,6 @@
|
||||
#define ASPEED_CLK_GATE_I3C3CLK 40
|
||||
#define ASPEED_CLK_GATE_I3C4CLK 41
|
||||
#define ASPEED_CLK_GATE_I3C5CLK 42
|
||||
#define ASPEED_CLK_GATE_I3C6CLK 43
|
||||
#define ASPEED_CLK_GATE_I3C7CLK 44
|
||||
|
||||
#define ASPEED_CLK_GATE_FSICLK 45
|
||||
|
||||
@ -87,8 +85,9 @@
|
||||
#define ASPEED_CLK_MAC2RCLK 68
|
||||
#define ASPEED_CLK_MAC3RCLK 69
|
||||
#define ASPEED_CLK_MAC4RCLK 70
|
||||
#define ASPEED_CLK_I3C 71
|
||||
|
||||
/* Only list resets here that are not part of a gate */
|
||||
/* Only list resets here that are not part of a clock gate + reset pair */
|
||||
#define ASPEED_RESET_ADC 55
|
||||
#define ASPEED_RESET_JTAG_MASTER2 54
|
||||
#define ASPEED_RESET_I3C_DMA 39
|
||||
|
||||
Loading…
Reference in New Issue
Block a user