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x86: Move the AMD64 specific parts out of setup_64.c
Create a separate amd_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
This commit is contained in:
Dave Jones
H. Peter Anvin
parent
d364319b98
commit
4d28587856
@ -7,6 +7,7 @@ obj-y += proc.o feature_names.o
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obj-$(CONFIG_X86_32) += common.o bugs.o
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obj-$(CONFIG_X86_32) += amd.o
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obj-$(CONFIG_X86_64) += amd_64.o
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obj-$(CONFIG_X86_32) += cyrix.o
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obj-$(CONFIG_X86_32) += centaur.o
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obj-$(CONFIG_X86_32) += transmeta.o
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235
arch/x86/kernel/cpu/amd_64.c
Normal file
235
arch/x86/kernel/cpu/amd_64.c
Normal file
@ -0,0 +1,235 @@
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/numa_64.h>
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#include <asm/mmconfig.h>
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#include <asm/cacheflush.h>
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#include <mach_apic.h>
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extern int __cpuinit get_model_name(struct cpuinfo_x86 *c);
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extern void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c);
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int force_mwait __cpuinitdata;
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#ifdef CONFIG_NUMA
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static int __cpuinit nearby_node(int apicid)
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{
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int i, node;
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for (i = apicid - 1; i >= 0; i--) {
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node = apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
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node = apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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return first_node(node_online_map); /* Shouldn't happen */
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}
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#endif
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/*
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* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
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* Assumes number of cores is a power of two.
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*/
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static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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unsigned bits;
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#ifdef CONFIG_NUMA
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int cpu = smp_processor_id();
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int node = 0;
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unsigned apicid = hard_smp_processor_id();
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#endif
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bits = c->x86_coreid_bits;
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/* Low order bits define the core id (index of core in socket) */
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c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
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/* Convert the initial APIC ID into the socket ID */
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c->phys_proc_id = c->initial_apicid >> bits;
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#ifdef CONFIG_NUMA
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node = c->phys_proc_id;
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if (apicid_to_node[apicid] != NUMA_NO_NODE)
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node = apicid_to_node[apicid];
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if (!node_online(node)) {
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/* Two possibilities here:
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- The CPU is missing memory and no node was created.
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In that case try picking one from a nearby CPU
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- The APIC IDs differ from the HyperTransport node IDs
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which the K8 northbridge parsing fills in.
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Assume they are all increased by a constant offset,
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but in the same order as the HT nodeids.
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If that doesn't result in a usable node fall back to the
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path for the previous case. */
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int ht_nodeid = c->initial_apicid;
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if (ht_nodeid >= 0 &&
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apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
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node = apicid_to_node[ht_nodeid];
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/* Pick a nearby node */
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if (!node_online(node))
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node = nearby_node(apicid);
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}
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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#endif
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}
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static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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unsigned bits, ecx;
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/* Multi core CPU? */
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if (c->extended_cpuid_level < 0x80000008)
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return;
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ecx = cpuid_ecx(0x80000008);
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c->x86_max_cores = (ecx & 0xff) + 1;
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/* CPU telling us the core id bits shift? */
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bits = (ecx >> 12) & 0xF;
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/* Otherwise recompute */
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->x86_coreid_bits = bits;
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#endif
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}
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#define ENABLE_C1E_MASK 0x18000000
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#define CPUID_PROCESSOR_SIGNATURE 1
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#define CPUID_XFAM 0x0ff00000
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#define CPUID_XFAM_K8 0x00000000
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#define CPUID_XFAM_10H 0x00100000
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#define CPUID_XFAM_11H 0x00200000
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#define CPUID_XMOD 0x000f0000
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#define CPUID_XMOD_REV_F 0x00040000
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/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
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static __cpuinit int amd_apic_timer_broken(void)
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{
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u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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switch (eax & CPUID_XFAM) {
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case CPUID_XFAM_K8:
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if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
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break;
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case CPUID_XFAM_10H:
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case CPUID_XFAM_11H:
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rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
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if (lo & ENABLE_C1E_MASK)
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return 1;
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break;
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default:
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/* err on the side of caution */
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return 1;
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}
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return 0;
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}
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void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd_mc(c);
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/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
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if (c->x86_power & (1<<8))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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unsigned level;
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#ifdef CONFIG_SMP
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unsigned long value;
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/*
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* Disable TLB flush filter by setting HWCR.FFDIS on K8
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* bit 6 of msr C001_0015
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*
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* Errata 63 for SH-B3 steppings
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* Errata 122 for all steppings (F+ have it disabled by default)
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*/
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if (c->x86 == 15) {
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rdmsrl(MSR_K8_HWCR, value);
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value |= 1 << 6;
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wrmsrl(MSR_K8_HWCR, value);
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}
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#endif
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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clear_cpu_cap(c, 0*32+31);
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/* On C+ stepping K8 rep microcode works well for copy/memset */
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level = cpuid_eax(1);
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if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
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level >= 0x0f58))
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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if (c->x86 == 0x10 || c->x86 == 0x11)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/* Enable workaround for FXSAVE leak */
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if (c->x86 >= 6)
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set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
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level = get_model_name(c);
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if (!level) {
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switch (c->x86) {
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case 15:
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/* Should distinguish Models here, but this is only
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a fallback anyways. */
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strcpy(c->x86_model_id, "Hammer");
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break;
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}
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}
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display_cacheinfo(c);
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/* Multi core CPU? */
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if (c->extended_cpuid_level >= 0x80000008)
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amd_detect_cmp(c);
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if (c->extended_cpuid_level >= 0x80000006 &&
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(cpuid_edx(0x80000006) & 0xf000))
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num_cache_leaves = 4;
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else
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num_cache_leaves = 3;
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if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
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set_cpu_cap(c, X86_FEATURE_K8);
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/* MFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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if (c->x86 == 0x10)
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fam10h_check_enable_mmcfg();
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if (amd_apic_timer_broken())
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disable_apic_timer = 1;
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if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
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unsigned long long tseg;
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/*
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* Split up direct mapping around the TSEG SMM area.
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* Don't do it for gbpages because there seems very little
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* benefit in doing so.
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*/
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if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
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(tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
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set_memory_4k((unsigned long)__va(tseg), 1);
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}
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}
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@ -96,8 +96,6 @@ int bootloader_type;
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unsigned long saved_video_mode;
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int force_mwait __cpuinitdata;
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/*
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* Early DMI memory
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*/
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@ -526,7 +524,7 @@ void __init setup_arch(char **cmdline_p)
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check_enable_amd_mmconf_dmi();
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}
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static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
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unsigned int *v;
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@ -542,7 +540,7 @@ static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
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}
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static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int n, dummy, eax, ebx, ecx, edx;
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@ -574,228 +572,6 @@ static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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}
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}
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#ifdef CONFIG_NUMA
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static int __cpuinit nearby_node(int apicid)
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{
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int i, node;
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for (i = apicid - 1; i >= 0; i--) {
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node = apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
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node = apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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return first_node(node_online_map); /* Shouldn't happen */
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}
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#endif
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/*
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* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
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* Assumes number of cores is a power of two.
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*/
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static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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unsigned bits;
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#ifdef CONFIG_NUMA
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int cpu = smp_processor_id();
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int node = 0;
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unsigned apicid = hard_smp_processor_id();
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#endif
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bits = c->x86_coreid_bits;
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/* Low order bits define the core id (index of core in socket) */
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c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
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/* Convert the initial APIC ID into the socket ID */
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c->phys_proc_id = c->initial_apicid >> bits;
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#ifdef CONFIG_NUMA
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node = c->phys_proc_id;
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if (apicid_to_node[apicid] != NUMA_NO_NODE)
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node = apicid_to_node[apicid];
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if (!node_online(node)) {
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/* Two possibilities here:
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- The CPU is missing memory and no node was created.
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In that case try picking one from a nearby CPU
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- The APIC IDs differ from the HyperTransport node IDs
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which the K8 northbridge parsing fills in.
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Assume they are all increased by a constant offset,
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but in the same order as the HT nodeids.
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If that doesn't result in a usable node fall back to the
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path for the previous case. */
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int ht_nodeid = c->initial_apicid;
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if (ht_nodeid >= 0 &&
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apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
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node = apicid_to_node[ht_nodeid];
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/* Pick a nearby node */
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if (!node_online(node))
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node = nearby_node(apicid);
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}
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numa_set_node(cpu, node);
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printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
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#endif
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#endif
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}
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static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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unsigned bits, ecx;
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/* Multi core CPU? */
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if (c->extended_cpuid_level < 0x80000008)
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return;
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ecx = cpuid_ecx(0x80000008);
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c->x86_max_cores = (ecx & 0xff) + 1;
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/* CPU telling us the core id bits shift? */
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bits = (ecx >> 12) & 0xF;
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/* Otherwise recompute */
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->x86_coreid_bits = bits;
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#endif
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}
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#define ENABLE_C1E_MASK 0x18000000
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#define CPUID_PROCESSOR_SIGNATURE 1
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#define CPUID_XFAM 0x0ff00000
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#define CPUID_XFAM_K8 0x00000000
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#define CPUID_XFAM_10H 0x00100000
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#define CPUID_XFAM_11H 0x00200000
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#define CPUID_XMOD 0x000f0000
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#define CPUID_XMOD_REV_F 0x00040000
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/* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
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static __cpuinit int amd_apic_timer_broken(void)
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{
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u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
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switch (eax & CPUID_XFAM) {
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case CPUID_XFAM_K8:
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if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
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break;
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case CPUID_XFAM_10H:
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case CPUID_XFAM_11H:
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rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
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if (lo & ENABLE_C1E_MASK)
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return 1;
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break;
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default:
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/* err on the side of caution */
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return 1;
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}
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return 0;
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}
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static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd_mc(c);
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/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
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if (c->x86_power & (1<<8))
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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}
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static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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{
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unsigned level;
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#ifdef CONFIG_SMP
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unsigned long value;
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|
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/*
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* Disable TLB flush filter by setting HWCR.FFDIS on K8
|
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* bit 6 of msr C001_0015
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*
|
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* Errata 63 for SH-B3 steppings
|
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* Errata 122 for all steppings (F+ have it disabled by default)
|
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*/
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if (c->x86 == 15) {
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rdmsrl(MSR_K8_HWCR, value);
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value |= 1 << 6;
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wrmsrl(MSR_K8_HWCR, value);
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}
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#endif
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/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
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clear_cpu_cap(c, 0*32+31);
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/* On C+ stepping K8 rep microcode works well for copy/memset */
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level = cpuid_eax(1);
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if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
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level >= 0x0f58))
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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if (c->x86 == 0x10 || c->x86 == 0x11)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/* Enable workaround for FXSAVE leak */
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if (c->x86 >= 6)
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set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
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level = get_model_name(c);
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if (!level) {
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switch (c->x86) {
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case 15:
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/* Should distinguish Models here, but this is only
|
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a fallback anyways. */
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strcpy(c->x86_model_id, "Hammer");
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break;
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}
|
||||
}
|
||||
display_cacheinfo(c);
|
||||
|
||||
/* Multi core CPU? */
|
||||
if (c->extended_cpuid_level >= 0x80000008)
|
||||
amd_detect_cmp(c);
|
||||
|
||||
if (c->extended_cpuid_level >= 0x80000006 &&
|
||||
(cpuid_edx(0x80000006) & 0xf000))
|
||||
num_cache_leaves = 4;
|
||||
else
|
||||
num_cache_leaves = 3;
|
||||
|
||||
if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
|
||||
set_cpu_cap(c, X86_FEATURE_K8);
|
||||
|
||||
/* MFENCE stops RDTSC speculation */
|
||||
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
||||
|
||||
if (c->x86 == 0x10)
|
||||
fam10h_check_enable_mmcfg();
|
||||
|
||||
if (amd_apic_timer_broken())
|
||||
disable_apic_timer = 1;
|
||||
|
||||
if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
|
||||
unsigned long long tseg;
|
||||
|
||||
/*
|
||||
* Split up direct mapping around the TSEG SMM area.
|
||||
* Don't do it for gbpages because there seems very little
|
||||
* benefit in doing so.
|
||||
*/
|
||||
if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
|
||||
(tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
|
||||
set_memory_4k((unsigned long)__va(tseg), 1);
|
||||
}
|
||||
}
|
||||
|
||||
void __cpuinit detect_ht(struct cpuinfo_x86 *c)
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
@ -977,6 +753,10 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
|
||||
c->x86_vendor = X86_VENDOR_UNKNOWN;
|
||||
}
|
||||
|
||||
// FIXME: Needs to use cpu_vendor_dev_register
|
||||
extern void __cpuinit early_init_amd(struct cpuinfo_x86 *c);
|
||||
extern void __cpuinit init_amd(struct cpuinfo_x86 *c);
|
||||
|
||||
/* Do some early cpuid on the boot CPU to get some parameter that are
|
||||
needed before check_bugs. Everything advanced is in identify_cpu
|
||||
below. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user