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staging/rdma/hfi1: Fix block comments
Fix block comments with proper formatting to fix checkpatch warnings: WARNING: Block comments use * on subsequent lines WARNING: Block comments use a trailing */ on a separate line Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Jubin John
Doug Ledford
parent
6a14c5ea38
commit
4d114fdd90
@ -6392,14 +6392,18 @@ static void dc_shutdown(struct hfi1_devdata *dd)
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spin_unlock_irqrestore(&dd->dc8051_lock, flags);
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/* Shutdown the LCB */
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lcb_shutdown(dd, 1);
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/* Going to OFFLINE would have causes the 8051 to put the
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/*
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* Going to OFFLINE would have causes the 8051 to put the
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* SerDes into reset already. Just need to shut down the 8051,
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* itself. */
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* itself.
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*/
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write_csr(dd, DC_DC8051_CFG_RST, 0x1);
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}
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/* Calling this after the DC has been brought out of reset should not
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* do any damage. */
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/*
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* Calling this after the DC has been brought out of reset should not
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* do any damage.
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*/
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static void dc_start(struct hfi1_devdata *dd)
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{
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unsigned long flags;
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@ -6525,8 +6529,10 @@ void handle_sma_message(struct work_struct *work)
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u64 msg;
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int ret;
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/* msg is bytes 1-4 of the 40-bit idle message - the command code
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is stripped off */
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/*
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* msg is bytes 1-4 of the 40-bit idle message - the command code
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* is stripped off
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*/
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ret = read_idle_sma(dd, &msg);
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if (ret)
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return;
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@ -6815,8 +6821,10 @@ void handle_link_up(struct work_struct *work)
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}
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}
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/* Several pieces of LNI information were cached for SMA in ppd.
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* Reset these on link down */
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/*
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* Several pieces of LNI information were cached for SMA in ppd.
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* Reset these on link down
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*/
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static void reset_neighbor_info(struct hfi1_pportdata *ppd)
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{
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ppd->neighbor_guid = 0;
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@ -6862,8 +6870,10 @@ void handle_link_down(struct work_struct *work)
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/* disable the port */
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clear_rcvctrl(ppd->dd, RCV_CTRL_RCV_PORT_ENABLE_SMASK);
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/* If there is no cable attached, turn the DC off. Otherwise,
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* start the link bring up. */
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/*
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* If there is no cable attached, turn the DC off. Otherwise,
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* start the link bring up.
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*/
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if (!qsfp_mod_present(ppd)) {
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dc_shutdown(ppd->dd);
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} else {
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@ -7564,8 +7574,10 @@ static void handle_8051_interrupt(struct hfi1_devdata *dd, u32 unused, u64 reg)
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}
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if (queue_link_down) {
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/* if the link is already going down or disabled, do not
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* queue another */
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/*
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* if the link is already going down or disabled, do not
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* queue another
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*/
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if ((ppd->host_link_state &
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(HLS_GOING_OFFLINE | HLS_LINK_COOLDOWN)) ||
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ppd->link_enabled == 0) {
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@ -7712,8 +7724,10 @@ static void handle_dcc_err(struct hfi1_devdata *dd, u32 unused, u64 reg)
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/* set status bit */
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dd->err_info_rcvport.status_and_code |=
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OPA_EI_STATUS_SMASK;
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/* save first 2 flits in the packet that caused
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* the error */
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/*
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* save first 2 flits in the packet that caused
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* the error
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*/
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dd->err_info_rcvport.packet_flit1 = hdr0;
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dd->err_info_rcvport.packet_flit2 = hdr1;
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}
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@ -7913,8 +7927,10 @@ static void is_reserved_int(struct hfi1_devdata *dd, unsigned int source)
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}
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static const struct is_table is_table[] = {
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/* start end
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name func interrupt func */
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/*
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* start end
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* name func interrupt func
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*/
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{ IS_GENERAL_ERR_START, IS_GENERAL_ERR_END,
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is_misc_err_name, is_misc_err_int },
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{ IS_SDMAENG_ERR_START, IS_SDMAENG_ERR_END,
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@ -10763,8 +10779,10 @@ int set_buffer_control(struct hfi1_pportdata *ppd,
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*/
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memset(changing, 0, sizeof(changing));
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memset(lowering_dedicated, 0, sizeof(lowering_dedicated));
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/* NOTE: Assumes that the individual VL bits are adjacent and in
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increasing order */
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/*
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* NOTE: Assumes that the individual VL bits are adjacent and in
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* increasing order
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*/
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stat_mask =
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SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK;
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changing_mask = 0;
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@ -11129,8 +11147,10 @@ static void adjust_rcv_timeout(struct hfi1_ctxtdata *rcd, u32 npkts)
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}
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rcd->rcvavail_timeout = timeout;
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/* timeout cannot be larger than rcv_intr_timeout_csr which has already
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been verified to be in range */
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/*
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* timeout cannot be larger than rcv_intr_timeout_csr which has already
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* been verified to be in range
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*/
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write_kctxt_csr(dd, rcd->ctxt, RCV_AVAIL_TIME_OUT,
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(u64)timeout << RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT);
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}
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@ -11323,8 +11343,10 @@ void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt)
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if (op & HFI1_RCVCTRL_TIDFLOW_DIS)
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rcvctrl &= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK;
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if (op & HFI1_RCVCTRL_ONE_PKT_EGR_ENB) {
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/* In one-packet-per-eager mode, the size comes from
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the RcvArray entry. */
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/*
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* In one-packet-per-eager mode, the size comes from
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* the RcvArray entry.
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*/
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rcvctrl &= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK;
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rcvctrl |= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK;
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}
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@ -12524,7 +12546,8 @@ static int request_msix_irqs(struct hfi1_devdata *dd)
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me->type = IRQ_RCVCTXT;
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} else {
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/* not in our expected range - complain, then
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ignore it */
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* ignore it
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*/
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dd_dev_err(dd,
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"Unexpected extra MSI-X interrupt %d\n", i);
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continue;
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@ -12830,8 +12853,10 @@ static void write_uninitialized_csrs_and_memories(struct hfi1_devdata *dd)
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/* PIO Send buffers */
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/* SDMA Send buffers */
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/* These are not normally read, and (presently) have no method
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to be read, so are not pre-initialized */
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/*
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* These are not normally read, and (presently) have no method
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* to be read, so are not pre-initialized
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*/
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/* RcvHdrAddr */
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/* RcvHdrTailAddr */
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@ -13026,8 +13051,10 @@ static void reset_misc_csrs(struct hfi1_devdata *dd)
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write_csr(dd, MISC_CFG_RSA_SIGNATURE + (8 * i), 0);
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write_csr(dd, MISC_CFG_RSA_MODULUS + (8 * i), 0);
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}
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/* MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
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only be written 128-byte chunks */
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/*
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* MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
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* only be written 128-byte chunks
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*/
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/* init RSA engine to clear lingering errors */
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write_csr(dd, MISC_CFG_RSA_CMD, 1);
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write_csr(dd, MISC_CFG_RSA_MU, 0);
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@ -14045,8 +14072,10 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
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dd->minrev = (dd->revision >> CCE_REVISION_CHIP_REV_MINOR_SHIFT)
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& CCE_REVISION_CHIP_REV_MINOR_MASK;
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/* obtain the hardware ID - NOT related to unit, which is a
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software enumeration */
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/*
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* obtain the hardware ID - NOT related to unit, which is a
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* software enumeration
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*/
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reg = read_csr(dd, CCE_REVISION2);
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dd->hfi1_id = (reg >> CCE_REVISION2_HFI_ID_SHIFT)
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& CCE_REVISION2_HFI_ID_MASK;
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@ -79,8 +79,10 @@
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#define PIO_CMASK 0x7ff /* counter mask for free and fill counters */
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#define MAX_EAGER_ENTRIES 2048 /* max receive eager entries */
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#define MAX_TID_PAIR_ENTRIES 1024 /* max receive expected pairs */
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/* Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed
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at 64 bytes for all generation one devices */
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/*
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* Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed
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* at 64 bytes for all generation one devices
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*/
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#define CM_VAU 3
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/* HFI link credit count, AKA receive buffer depth (RBUF_DEPTH) */
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#define CM_GLOBAL_CREDITS 0x940
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@ -518,8 +520,10 @@ enum {
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#define LCB_CRC_48B 0x2 /* 48b CRC */
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#define LCB_CRC_12B_16B_PER_LANE 0x3 /* 12b-16b per lane CRC */
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/* the following enum is (almost) a copy/paste of the definition
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* in the OPA spec, section 20.2.2.6.8 (PortInfo) */
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/*
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* the following enum is (almost) a copy/paste of the definition
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* in the OPA spec, section 20.2.2.6.8 (PortInfo)
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*/
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enum {
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PORT_LTP_CRC_MODE_NONE = 0,
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PORT_LTP_CRC_MODE_14 = 1, /* 14-bit LTP CRC mode (optional) */
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@ -388,8 +388,10 @@ static ssize_t hfi1_file_write(struct file *fp, const char __user *data,
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break;
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}
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if (dd->flags & HFI1_FORCED_FREEZE) {
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/* Don't allow context reset if we are into
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* forced freeze */
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/*
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* Don't allow context reset if we are into
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* forced freeze
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*/
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ret = -ENODEV;
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break;
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}
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@ -1294,8 +1294,10 @@ static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
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/* step 3: enable XDMEM access */
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sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40);
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/* step 4: load firmware into SBus Master XDMEM */
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/* NOTE: the dmem address, write_en, and wdata are all pre-packed,
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we only need to pick up the bytes and write them */
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/*
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* NOTE: the dmem address, write_en, and wdata are all pre-packed,
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* we only need to pick up the bytes and write them
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*/
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for (i = 0; i < fdet->firmware_len; i += 4) {
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sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
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*(u32 *)&fdet->firmware_ptr[i]);
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@ -1305,8 +1307,10 @@ static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
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/* step 6: allow SBus Spico to run */
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sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000);
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/* steps 7-11: run RSA, if it succeeds, firmware is available to
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be swapped */
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/*
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* steps 7-11: run RSA, if it succeeds, firmware is available to
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* be swapped
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*/
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return run_rsa(dd, "PCIe serdes", fdet->signature);
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}
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@ -1744,8 +1748,10 @@ int get_platform_config_field(struct hfi1_devdata *dd,
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src_ptr = (u32 *)((u8 *)src_ptr + seek);
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/* We expect the field to be byte aligned and whole byte
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* lengths if we are here */
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/*
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* We expect the field to be byte aligned and whole byte
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* lengths if we are here
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*/
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memcpy(data, src_ptr, wlen);
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return 0;
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}
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@ -718,8 +718,10 @@ struct hfi1_pportdata {
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/* CA's max number of 64 entry units in the congestion control table */
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u8 cc_max_table_entries;
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/* begin congestion log related entries
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* cc_log_lock protects all congestion log related data */
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/*
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* begin congestion log related entries
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* cc_log_lock protects all congestion log related data
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*/
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spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
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u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
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u16 threshold_event_counter;
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@ -790,8 +790,10 @@ done:
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for (pidx = 0; pidx < dd->num_pports; ++pidx) {
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ppd = dd->pport + pidx;
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/* start the serdes - must be after interrupts are
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enabled so we are notified when the link goes up */
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/*
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* start the serdes - must be after interrupts are
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* enabled so we are notified when the link goes up
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*/
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lastfail = bringup_serdes(ppd);
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if (lastfail)
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dd_dev_info(dd,
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@ -1188,8 +1190,10 @@ static int __init hfi1_mod_init(void)
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user_credit_return_threshold = 100;
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compute_krcvqs();
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/* sanitize receive interrupt count, time must wait until after
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the hardware type is known */
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/*
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* sanitize receive interrupt count, time must wait until after
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* the hardware type is known
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*/
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if (rcv_intr_count > RCV_HDR_HEAD_COUNTER_MASK)
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rcv_intr_count = RCV_HDR_HEAD_COUNTER_MASK;
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/* reject invalid combinations */
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@ -696,8 +696,10 @@ static int __subn_get_opa_portinfo(struct opa_smp *smp, u32 am, u8 *data,
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/* read the cached value of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
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read_lcb_cache(DC_LCB_STS_ROUND_TRIP_LTP_CNT, &tmp);
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/* this counter is 16 bits wide, but the replay_depth.wire
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* variable is only 8 bits */
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/*
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* this counter is 16 bits wide, but the replay_depth.wire
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* variable is only 8 bits
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*/
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if (tmp > 0xff)
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tmp = 0xff;
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pi->replay_depth.wire = tmp;
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@ -1621,8 +1623,10 @@ static int __subn_set_opa_sc_to_vlt(struct opa_smp *smp, u32 am, u8 *data,
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/* IB numbers ports from 1, hw from 0 */
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ppd = dd->pport + (port - 1);
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lstate = driver_lstate(ppd);
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/* it's known that async_update is 0 by this point, but include
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* the explicit check for clarity */
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/*
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* it's known that async_update is 0 by this point, but include
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* the explicit check for clarity
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*/
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if (!async_update &&
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(lstate == IB_PORT_ARMED || lstate == IB_PORT_ACTIVE)) {
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smp->status |= IB_SMP_INVALID_FIELD;
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@ -1797,8 +1801,10 @@ static int __subn_get_opa_cable_info(struct opa_smp *smp, u32 am, u8 *data,
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#define __CI_PAGE_MASK ~(__CI_PAGE_SIZE - 1)
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#define __CI_PAGE_NUM(a) ((a) & __CI_PAGE_MASK)
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/* check that addr is within spec, and
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* addr and (addr + len - 1) are on the same "page" */
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/*
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* check that addr is within spec, and
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* addr and (addr + len - 1) are on the same "page"
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*/
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if (addr >= 4096 ||
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(__CI_PAGE_NUM(addr) != __CI_PAGE_NUM(addr + len - 1))) {
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smp->status |= IB_SMP_INVALID_FIELD;
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@ -1935,8 +1941,10 @@ static int __subn_set_opa_vl_arb(struct opa_smp *smp, u32 am, u8 *data,
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case OPA_VLARB_HIGH_ELEMENTS:
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(void)fm_set_table(ppd, FM_TBL_VL_HIGH_ARB, p);
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break;
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/* neither OPA_VLARB_PREEMPT_ELEMENTS, or OPA_VLARB_PREEMPT_MATRIX
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* can be changed from the default values */
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/*
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* neither OPA_VLARB_PREEMPT_ELEMENTS, or OPA_VLARB_PREEMPT_MATRIX
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* can be changed from the default values
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*/
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case OPA_VLARB_PREEMPT_ELEMENTS:
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/* FALLTHROUGH */
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case OPA_VLARB_PREEMPT_MATRIX:
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@ -2148,8 +2156,10 @@ struct opa_port_data_counters_msg {
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};
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struct opa_port_error_counters64_msg {
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/* Request contains first two fields, response contains the
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* whole magilla */
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/*
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* Request contains first two fields, response contains the
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* whole magilla
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*/
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__be64 port_select_mask[4];
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__be32 vl_select_mask;
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@ -2673,11 +2683,12 @@ static int pma_get_opa_datacounters(struct opa_pma_mad *pmp,
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/* rsp->port_vl_xmit_time_cong is 0 for HFIs */
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/* rsp->port_vl_xmit_wasted_bw ??? */
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/* port_vl_xmit_wait_data - TXE (table 13-9 HFI spec) ???
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* does this differ from rsp->vls[vfi].port_vl_xmit_wait */
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* does this differ from rsp->vls[vfi].port_vl_xmit_wait
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*/
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/*rsp->vls[vfi].port_vl_mark_fecn =
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cpu_to_be64(read_csr(dd, DCC_PRF_PORT_VL_MARK_FECN_CNT
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+ offset));
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*/
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* cpu_to_be64(read_csr(dd, DCC_PRF_PORT_VL_MARK_FECN_CNT
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* + offset));
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*/
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vlinfo++;
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vfi++;
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}
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@ -2996,8 +3007,10 @@ static int pma_get_opa_errorinfo(struct opa_pma_mad *pmp,
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/* ExcessiverBufferOverrunInfo */
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reg = read_csr(dd, RCV_ERR_INFO);
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if (reg & RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK) {
|
||||
/* if the RcvExcessBufferOverrun bit is set, save SC of
|
||||
* first pkt that encountered an excess buffer overrun */
|
||||
/*
|
||||
* if the RcvExcessBufferOverrun bit is set, save SC of
|
||||
* first pkt that encountered an excess buffer overrun
|
||||
*/
|
||||
u8 tmp = (u8)reg;
|
||||
|
||||
tmp &= RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SC_SMASK;
|
||||
@ -3093,8 +3106,9 @@ static int pma_set_opa_portstatus(struct opa_pma_mad *pmp,
|
||||
write_dev_cntr(dd, C_DC_RCV_BBL, CNTR_INVALID_VL, 0);
|
||||
|
||||
/* Only applicable for switch */
|
||||
/*if (counter_select & CS_PORT_MARK_FECN)
|
||||
write_csr(dd, DCC_PRF_PORT_MARK_FECN_CNT, 0);*/
|
||||
/* if (counter_select & CS_PORT_MARK_FECN)
|
||||
* write_csr(dd, DCC_PRF_PORT_MARK_FECN_CNT, 0);
|
||||
*/
|
||||
|
||||
if (counter_select & CS_PORT_RCV_CONSTRAINT_ERRORS)
|
||||
write_port_cntr(ppd, C_SW_RCV_CSTR_ERR, CNTR_INVALID_VL, 0);
|
||||
@ -3167,9 +3181,9 @@ static int pma_set_opa_portstatus(struct opa_pma_mad *pmp,
|
||||
if (counter_select & CS_PORT_RCV_BUBBLE)
|
||||
write_dev_cntr(dd, C_DC_RCV_BBL_VL, idx_from_vl(vl), 0);
|
||||
|
||||
/*if (counter_select & CS_PORT_MARK_FECN)
|
||||
write_csr(dd, DCC_PRF_PORT_VL_MARK_FECN_CNT + offset, 0);
|
||||
*/
|
||||
/* if (counter_select & CS_PORT_MARK_FECN)
|
||||
* write_csr(dd, DCC_PRF_PORT_VL_MARK_FECN_CNT + offset, 0);
|
||||
*/
|
||||
/* port_vl_xmit_discards ??? */
|
||||
}
|
||||
|
||||
@ -3226,8 +3240,10 @@ static int pma_set_opa_errorinfo(struct opa_pma_mad *pmp,
|
||||
|
||||
/* ExcessiverBufferOverrunInfo */
|
||||
if (error_info_select & ES_EXCESSIVE_BUFFER_OVERRUN_INFO)
|
||||
/* status bit is essentially kept in the h/w - bit 5 of
|
||||
* RCV_ERR_INFO */
|
||||
/*
|
||||
* status bit is essentially kept in the h/w - bit 5 of
|
||||
* RCV_ERR_INFO
|
||||
*/
|
||||
write_csr(dd, RCV_ERR_INFO,
|
||||
RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK);
|
||||
|
||||
|
||||
@ -51,8 +51,10 @@
|
||||
#define _HFI1_MAD_H
|
||||
|
||||
#include <rdma/ib_pma.h>
|
||||
#define USE_PI_LED_ENABLE 1 /* use led enabled bit in struct
|
||||
* opa_port_states, if available */
|
||||
#define USE_PI_LED_ENABLE 1 /*
|
||||
* use led enabled bit in struct
|
||||
* opa_port_states, if available
|
||||
*/
|
||||
#include <rdma/opa_smi.h>
|
||||
#include <rdma/opa_port_info.h>
|
||||
#ifndef PI_LED_ENABLE_SUP
|
||||
|
||||
@ -284,9 +284,11 @@ static void msix_setup(struct hfi1_devdata *dd, int pos, u32 *msixcnt,
|
||||
struct msix_entry *msix_entry;
|
||||
int i;
|
||||
|
||||
/* We can't pass hfi1_msix_entry array to msix_setup
|
||||
/*
|
||||
* We can't pass hfi1_msix_entry array to msix_setup
|
||||
* so use a dummy msix_entry array and copy the allocated
|
||||
* irq back to the hfi1_msix_entry array. */
|
||||
* irq back to the hfi1_msix_entry array.
|
||||
*/
|
||||
msix_entry = kmalloc_array(nvec, sizeof(*msix_entry), GFP_KERNEL);
|
||||
if (!msix_entry) {
|
||||
ret = -ENOMEM;
|
||||
|
||||
@ -177,8 +177,10 @@ static struct mem_pool_config sc_mem_pool_config[NUM_SC_POOLS] = {
|
||||
|
||||
/* memory pool information, used when calculating final sizes */
|
||||
struct mem_pool_info {
|
||||
int centipercent; /* 100th of 1% of memory to use, -1 if blocks
|
||||
already set */
|
||||
int centipercent; /*
|
||||
* 100th of 1% of memory to use, -1 if blocks
|
||||
* already set
|
||||
*/
|
||||
int count; /* count of contexts in the pool */
|
||||
int blocks; /* block size of the pool */
|
||||
int size; /* context size, in blocks */
|
||||
@ -1429,8 +1431,10 @@ retry:
|
||||
next = head + 1;
|
||||
if (next >= sc->sr_size)
|
||||
next = 0;
|
||||
/* update the head - must be last! - the releaser can look at fields
|
||||
in pbuf once we move the head */
|
||||
/*
|
||||
* update the head - must be last! - the releaser can look at fields
|
||||
* in pbuf once we move the head
|
||||
*/
|
||||
smp_wmb();
|
||||
sc->sr_head = next;
|
||||
spin_unlock_irqrestore(&sc->alloc_lock, flags);
|
||||
|
||||
@ -86,8 +86,10 @@ void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
|
||||
dend = dest + ((count >> 1) * sizeof(u64));
|
||||
|
||||
if (dend < send) {
|
||||
/* all QWORD data is within the SOP block, does *not*
|
||||
reach the end of the SOP block */
|
||||
/*
|
||||
* all QWORD data is within the SOP block, does *not*
|
||||
* reach the end of the SOP block
|
||||
*/
|
||||
|
||||
while (dest < dend) {
|
||||
writeq(*(u64 *)from, dest);
|
||||
@ -152,8 +154,10 @@ void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc,
|
||||
writeq(val.val64, dest);
|
||||
dest += sizeof(u64);
|
||||
}
|
||||
/* fill in rest of block, no need to check pbuf->end
|
||||
as we only wrap on a block boundary */
|
||||
/*
|
||||
* fill in rest of block, no need to check pbuf->end
|
||||
* as we only wrap on a block boundary
|
||||
*/
|
||||
while (((unsigned long)dest & PIO_BLOCK_MASK) != 0) {
|
||||
writeq(0, dest);
|
||||
dest += sizeof(u64);
|
||||
@ -466,8 +470,10 @@ void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc,
|
||||
dend = dest + ((nbytes >> 3) * sizeof(u64));
|
||||
|
||||
if (dend < send) {
|
||||
/* all QWORD data is within the SOP block, does *not*
|
||||
reach the end of the SOP block */
|
||||
/*
|
||||
* all QWORD data is within the SOP block, does *not*
|
||||
* reach the end of the SOP block
|
||||
*/
|
||||
|
||||
while (dest < dend) {
|
||||
writeq(*(u64 *)from, dest);
|
||||
@ -562,8 +568,10 @@ static void mid_copy_mix(struct pio_buf *pbuf, const void *from, size_t nbytes)
|
||||
void __iomem *send; /* SOP end */
|
||||
void __iomem *xend;
|
||||
|
||||
/* calculate the end of data or end of block, whichever
|
||||
comes first */
|
||||
/*
|
||||
* calculate the end of data or end of block, whichever
|
||||
* comes first
|
||||
*/
|
||||
send = pbuf->start + PIO_BLOCK_SIZE;
|
||||
xend = send < dend ? send : dend;
|
||||
|
||||
@ -656,8 +664,10 @@ static void mid_copy_straight(struct pio_buf *pbuf,
|
||||
void __iomem *send; /* SOP end */
|
||||
void __iomem *xend;
|
||||
|
||||
/* calculate the end of data or end of block, whichever
|
||||
comes first */
|
||||
/*
|
||||
* calculate the end of data or end of block, whichever
|
||||
* comes first
|
||||
*/
|
||||
send = pbuf->start + PIO_BLOCK_SIZE;
|
||||
xend = send < dend ? send : dend;
|
||||
|
||||
|
||||
@ -186,9 +186,9 @@ static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
|
||||
*/
|
||||
|
||||
/*
|
||||
*=====================================================
|
||||
* =====================================================
|
||||
* System table encodings
|
||||
*====================================================
|
||||
* =====================================================
|
||||
*/
|
||||
#define PLATFORM_CONFIG_MAGIC_NUM 0x3d4f5041
|
||||
#define PLATFORM_CONFIG_MAGIC_NUMBER_LEN 4
|
||||
@ -208,9 +208,9 @@ enum platform_config_qsfp_power_class_encoding {
|
||||
};
|
||||
|
||||
/*
|
||||
*=====================================================
|
||||
* ====================================================
|
||||
* Port table encodings
|
||||
*====================================================
|
||||
* ====================================================
|
||||
*/
|
||||
enum platform_config_port_type_encoding {
|
||||
PORT_TYPE_UNKNOWN,
|
||||
|
||||
@ -2219,7 +2219,8 @@ static void __sdma_process_event(struct sdma_engine *sde,
|
||||
* of link up, then we need to start up.
|
||||
* This can happen when hw down is requested while
|
||||
* bringing the link up with traffic active on
|
||||
* 7220, e.g. */
|
||||
* 7220, e.g.
|
||||
*/
|
||||
ss->go_s99_running = 1;
|
||||
/* fall through and start dma engine */
|
||||
case sdma_event_e10_go_hw_start:
|
||||
|
||||
@ -179,8 +179,10 @@ struct user_sdma_iovec {
|
||||
unsigned npages;
|
||||
/* array of pinned pages for this vector */
|
||||
struct page **pages;
|
||||
/* offset into the virtual address space of the vector at
|
||||
* which we last left off. */
|
||||
/*
|
||||
* offset into the virtual address space of the vector at
|
||||
* which we last left off.
|
||||
*/
|
||||
u64 offset;
|
||||
};
|
||||
|
||||
@ -596,8 +598,10 @@ int hfi1_user_sdma_process_request(struct file *fp, struct iovec *iovec,
|
||||
}
|
||||
|
||||
req->koffset = le32_to_cpu(req->hdr.kdeth.swdata[6]);
|
||||
/* Calculate the initial TID offset based on the values of
|
||||
KDETH.OFFSET and KDETH.OM that are passed in. */
|
||||
/*
|
||||
* Calculate the initial TID offset based on the values of
|
||||
* KDETH.OFFSET and KDETH.OM that are passed in.
|
||||
*/
|
||||
req->tidoffset = KDETH_GET(req->hdr.kdeth.ver_tid_offset, OFFSET) *
|
||||
(KDETH_GET(req->hdr.kdeth.ver_tid_offset, OM) ?
|
||||
KDETH_OM_LARGE : KDETH_OM_SMALL);
|
||||
@ -742,8 +746,10 @@ static inline u32 compute_data_length(struct user_sdma_request *req,
|
||||
} else if (req_opcode(req->info.ctrl) == EXPECTED) {
|
||||
u32 tidlen = EXP_TID_GET(req->tids[req->tididx], LEN) *
|
||||
PAGE_SIZE;
|
||||
/* Get the data length based on the remaining space in the
|
||||
* TID pair. */
|
||||
/*
|
||||
* Get the data length based on the remaining space in the
|
||||
* TID pair.
|
||||
*/
|
||||
len = min(tidlen - req->tidoffset, (u32)req->info.fragsize);
|
||||
/* If we've filled up the TID pair, move to the next one. */
|
||||
if (unlikely(!len) && ++req->tididx < req->n_tids &&
|
||||
@ -753,9 +759,11 @@ static inline u32 compute_data_length(struct user_sdma_request *req,
|
||||
req->tidoffset = 0;
|
||||
len = min_t(u32, tidlen, req->info.fragsize);
|
||||
}
|
||||
/* Since the TID pairs map entire pages, make sure that we
|
||||
/*
|
||||
* Since the TID pairs map entire pages, make sure that we
|
||||
* are not going to try to send more data that we have
|
||||
* remaining. */
|
||||
* remaining.
|
||||
*/
|
||||
len = min(len, req->data_len - req->sent);
|
||||
} else
|
||||
len = min(req->data_len - req->sent, (u32)req->info.fragsize);
|
||||
@ -979,8 +987,10 @@ static int user_sdma_send_pkts(struct user_sdma_request *req, unsigned maxpkts)
|
||||
req->sent += data_sent;
|
||||
if (req->data_len) {
|
||||
tx->iovecs[tx->idx].vec->offset += iov_offset;
|
||||
/* If we've reached the end of the io vector, mark it
|
||||
* so the callback can unpin the pages and free it. */
|
||||
/*
|
||||
* If we've reached the end of the io vector, mark it
|
||||
* so the callback can unpin the pages and free it.
|
||||
*/
|
||||
if (tx->iovecs[tx->idx].vec->offset ==
|
||||
tx->iovecs[tx->idx].vec->iov.iov_len)
|
||||
tx->iovecs[tx->idx].flags |=
|
||||
@ -1216,8 +1226,10 @@ static int set_txreq_header(struct user_sdma_request *req,
|
||||
if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) *
|
||||
PAGE_SIZE)) {
|
||||
req->tidoffset = 0;
|
||||
/* Since we don't copy all the TIDs, all at once,
|
||||
* we have to check again. */
|
||||
/*
|
||||
* Since we don't copy all the TIDs, all at once,
|
||||
* we have to check again.
|
||||
*/
|
||||
if (++req->tididx > req->n_tids - 1 ||
|
||||
!req->tids[req->tididx]) {
|
||||
return -EINVAL;
|
||||
@ -1298,8 +1310,10 @@ static int set_txreq_header_ahg(struct user_sdma_request *req,
|
||||
if ((req->tidoffset) == (EXP_TID_GET(tidval, LEN) *
|
||||
PAGE_SIZE)) {
|
||||
req->tidoffset = 0;
|
||||
/* Since we don't copy all the TIDs, all at once,
|
||||
* we have to check again. */
|
||||
/*
|
||||
* Since we don't copy all the TIDs, all at once,
|
||||
* we have to check again.
|
||||
*/
|
||||
if (++req->tididx > req->n_tids - 1 ||
|
||||
!req->tids[req->tididx]) {
|
||||
return -EINVAL;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user