mirror of
https://github.com/torvalds/linux.git
synced 2024-09-21 15:33:19 +00:00
SH/R-Mobile updates for 3.3 merge window.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.15 (GNU/Linux) iEYEABECAAYFAk8Obj8ACgkQGkmNcg7/o7hzngCfS5az4ZP3D+e/cvatHZm/nAzn 0mIAoKbYyXpLXGkEN+yDkd5YZAYwQjVR =kryV -----END PGP SIGNATURE----- Merge tag 'rmobile-for-linus' of git://github.com/pmundt/linux-sh SH/R-Mobile updates for 3.3 merge window. * tag 'rmobile-for-linus' of git://github.com/pmundt/linux-sh: (32 commits) arm: mach-shmobile: add a resource name for shdma ARM: mach-shmobile: r8a7779 SMP support V3 ARM: mach-shmobile: Add kota2 defconfig. ARM: mach-shmobile: Add marzen defconfig. ARM: mach-shmobile: r8a7779 power domain support V2 ARM: mach-shmobile: Fix up marzen build for recent GIC changes. ARM: mach-shmobile: r8a7779 PFC function support ARM: mach-shmobile: Flush caches in platform_cpu_die() ARM: mach-shmobile: Allow SoC specific CPU kill code ARM: mach-shmobile: Fix headsmp.S code to use CPUINIT ARM: mach-shmobile: clock-r8a7779: clkz/clkzs support ARM: mach-shmobile: clock-r8a7779: add DIV4 clock support ARM: mach-shmobile: Marzen LAN89218 support ARM: mach-shmobile: Marzen SCIF2/SCIF4 support ARM: mach-shmobile: r8a7779 PFC GPIO-only support V2 ARM: mach-shmobile: r8a7779 and Marzen base support V2 sh: pfc: Unlock register support sh: pfc: Variable bitfield width config register support sh: pfc: Add config_reg_helper() function sh: pfc: Convert index to field and value pair ...
This commit is contained in:
Linus Torvalds
commit
4c4d285ad5
72
arch/arm/configs/bonito_defconfig
Normal file
72
arch/arm/configs/bonito_defconfig
Normal file
|
|
@ -0,0 +1,72 @@
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|||
CONFIG_EXPERIMENTAL=y
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||||
CONFIG_SYSVIPC=y
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||||
CONFIG_IKCONFIG=y
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||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
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||||
CONFIG_ARCH_SHMOBILE=y
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CONFIG_ARCH_R8A7740=y
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||||
CONFIG_MACH_BONITO=y
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||||
# CONFIG_SH_TIMER_TMU is not set
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CONFIG_AEABI=y
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||||
# CONFIG_OABI_COMPAT is not set
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||||
CONFIG_FORCE_MAX_ZONEORDER=12
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CONFIG_ZBOOT_ROM_TEXT=0x0
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||||
CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
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||||
CONFIG_KEXEC=y
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||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_PM_RUNTIME=y
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||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
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||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_ARM_INTEGRATOR=y
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||||
CONFIG_MTD_BLOCK2MTD=y
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||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
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||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
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||||
# CONFIG_LEGACY_PTYS is not set
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||||
CONFIG_SERIAL_SH_SCI=y
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||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
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||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
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||||
# CONFIG_HW_RANDOM is not set
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||||
CONFIG_I2C=y
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||||
CONFIG_I2C_CHARDEV=y
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||||
CONFIG_I2C_SH_MOBILE=y
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CONFIG_GPIO_SYSFS=y
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||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_MFD_SUPPORT is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
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||||
CONFIG_UIO=y
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||||
CONFIG_UIO_PDRV=y
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||||
CONFIG_UIO_PDRV_GENIRQ=y
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||||
# CONFIG_DNOTIFY is not set
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||||
# CONFIG_INOTIFY_USER is not set
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||||
CONFIG_TMPFS=y
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||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
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||||
# CONFIG_ENABLE_MUST_CHECK is not set
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||||
# CONFIG_ARM_UNWIND is not set
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||||
122
arch/arm/configs/kota2_defconfig
Normal file
122
arch/arm/configs/kota2_defconfig
Normal file
|
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@ -0,0 +1,122 @@
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# CONFIG_ARM_PATCH_PHYS_VIRT is not set
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_CGROUPS=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_NAMESPACES=y
|
||||
# CONFIG_UTS_NS is not set
|
||||
# CONFIG_IPC_NS is not set
|
||||
# CONFIG_USER_NS is not set
|
||||
# CONFIG_PID_NS is not set
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
CONFIG_ARCH_SHMOBILE=y
|
||||
CONFIG_KEYBOARD_GPIO_POLLED=y
|
||||
CONFIG_ARCH_SH73A0=y
|
||||
CONFIG_MACH_KOTA2=y
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||||
CONFIG_MEMORY_SIZE=0x1e0000000
|
||||
# CONFIG_SH_TIMER_TMU is not set
|
||||
# CONFIG_SWP_EMULATE is not set
|
||||
CONFIG_CPU_BPREDICT_DISABLE=y
|
||||
CONFIG_ARM_ERRATA_460075=y
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||||
CONFIG_ARM_ERRATA_742230=y
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||||
CONFIG_ARM_ERRATA_742231=y
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||||
CONFIG_PL310_ERRATA_588369=y
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CONFIG_ARM_ERRATA_720789=y
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CONFIG_PL310_ERRATA_727915=y
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||||
CONFIG_ARM_ERRATA_743622=y
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CONFIG_ARM_ERRATA_751472=y
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CONFIG_PL310_ERRATA_753970=y
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||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_PL310_ERRATA_769419=y
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||||
CONFIG_NO_HZ=y
|
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CONFIG_SMP=y
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
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||||
CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
|
||||
CONFIG_CMDLINE_FORCE=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_WIRELESS_EXT_SYSFS=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_BLK_DEV is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
CONFIG_SMSC911X=y
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||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
CONFIG_B43=y
|
||||
CONFIG_B43_PHY_N=y
|
||||
CONFIG_B43_DEBUG=y
|
||||
CONFIG_INPUT_SPARSEKMAP=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KEYBOARD_SH_KEYSC=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
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||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C_SH_MOBILE=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_BCMA=y
|
||||
CONFIG_BCMA_DEBUG=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_SH_MOBILE_LCDC=y
|
||||
CONFIG_LCD_PLATFORM=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SDHI=y
|
||||
CONFIG_MMC_SH_MMCIF=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_RENESAS_TPU=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_INFO_REDUCED=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
87
arch/arm/configs/marzen_defconfig
Normal file
87
arch/arm/configs/marzen_defconfig
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_KERNEL_LZMA=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_BLOCK is not set
|
||||
CONFIG_ARCH_SHMOBILE=y
|
||||
CONFIG_ARCH_R8A7779=y
|
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CONFIG_MACH_MARZEN=y
|
||||
CONFIG_MEMORY_START=0x60000000
|
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CONFIG_MEMORY_SIZE=0x10000000
|
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CONFIG_SHMOBILE_TIMER_HZ=1024
|
||||
# CONFIG_SH_TIMER_CMT is not set
|
||||
# CONFIG_SWP_EMULATE is not set
|
||||
CONFIG_ARM_ERRATA_430973=y
|
||||
CONFIG_ARM_ERRATA_458693=y
|
||||
CONFIG_ARM_ERRATA_460075=y
|
||||
CONFIG_ARM_ERRATA_743622=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_ARM_CPU_TOPOLOGY is not set
|
||||
CONFIG_AEABI=y
|
||||
# CONFIG_OABI_COMPAT is not set
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
|
||||
CONFIG_CMDLINE_FORCE=y
|
||||
CONFIG_KEXEC=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_PM_RUNTIME=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_FARADAY is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=6
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_SSB=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_UIO=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_FILE_LOCKING is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_INOTIFY_USER is not set
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_INFO_REDUCED=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_AVERAGE=y
|
||||
|
|
@ -28,6 +28,19 @@ config ARCH_SH73A0
|
|||
select ARM_GIC
|
||||
select I2C
|
||||
|
||||
config ARCH_R8A7740
|
||||
bool "R-Mobile A1 (R8A77400)"
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
|
||||
config ARCH_R8A7779
|
||||
bool "R-Car H1 (R8A77790)"
|
||||
select CPU_V7
|
||||
select SH_CLK_CPG
|
||||
select ARM_GIC
|
||||
select ARCH_WANT_OPTIONAL_GPIOLIB
|
||||
|
||||
comment "SH-Mobile Board Type"
|
||||
|
||||
config MACH_G3EVM
|
||||
|
|
@ -75,6 +88,16 @@ config MACH_KOTA2
|
|||
select ARCH_REQUIRE_GPIOLIB
|
||||
depends on ARCH_SH73A0
|
||||
|
||||
config MACH_BONITO
|
||||
bool "bonito board"
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
depends on ARCH_R8A7740
|
||||
|
||||
config MACH_MARZEN
|
||||
bool "MARZEN board"
|
||||
depends on ARCH_R8A7779
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
|
||||
comment "SH-Mobile System Configuration"
|
||||
|
||||
menu "Memory configuration"
|
||||
|
|
@ -83,7 +106,7 @@ config MEMORY_START
|
|||
hex "Physical memory start address"
|
||||
default "0x50000000" if MACH_G3EVM
|
||||
default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
|
||||
MACH_MACKEREL
|
||||
MACH_MACKEREL || MACH_BONITO
|
||||
default "0x41000000" if MACH_KOTA2
|
||||
default "0x00000000"
|
||||
---help---
|
||||
|
|
@ -95,7 +118,7 @@ config MEMORY_SIZE
|
|||
hex "Physical memory size"
|
||||
default "0x08000000" if MACH_G3EVM
|
||||
default "0x08000000" if MACH_G4EVM
|
||||
default "0x20000000" if MACH_AG5EVM
|
||||
default "0x20000000" if MACH_AG5EVM || MACH_BONITO
|
||||
default "0x1e000000" if MACH_KOTA2
|
||||
default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
|
||||
default "0x04000000"
|
||||
|
|
|
|||
|
|
@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
|
|||
obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
|
||||
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
|
||||
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
|
||||
|
||||
# SMP objects
|
||||
smp-y := platsmp.o headsmp.o
|
||||
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o
|
||||
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o
|
||||
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
|
||||
|
||||
# Pinmux setup
|
||||
pfc-y :=
|
||||
|
|
@ -23,16 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
|
|||
pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
|
||||
pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
|
||||
pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
|
||||
pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
|
||||
pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
|
||||
|
||||
# IRQ objects
|
||||
obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
|
||||
obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
|
||||
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
|
||||
obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
|
||||
|
||||
# PM objects
|
||||
obj-$(CONFIG_SUSPEND) += suspend.o
|
||||
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
|
||||
obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
|
||||
obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
|
||||
|
||||
# Board objects
|
||||
obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
|
||||
|
|
@ -41,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
|
|||
obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
|
||||
obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
|
||||
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
|
||||
obj-$(CONFIG_MACH_BONITO) += board-bonito.o
|
||||
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
|
||||
|
||||
# Framework support
|
||||
obj-$(CONFIG_SMP) += $(smp-y)
|
||||
|
|
|
|||
522
arch/arm/mach-shmobile/board-bonito.c
Normal file
522
arch/arm/mach-shmobile/board-bonito.c
Normal file
|
|
@ -0,0 +1,522 @@
|
|||
/*
|
||||
* bonito board support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <mach/r8a7740.h>
|
||||
#include <video/sh_mobile_lcdc.h>
|
||||
|
||||
/*
|
||||
* CS Address device note
|
||||
*----------------------------------------------------------------
|
||||
* 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
|
||||
* 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
|
||||
* 4 -
|
||||
* 5A -
|
||||
* 5B 0x1600_0000 SRAM (8MB)
|
||||
* 6 0x1800_0000 FPGA (64K)
|
||||
* 0x1801_0000 Ether (4KB)
|
||||
* 0x1801_1000 USB (4KB)
|
||||
*/
|
||||
|
||||
/*
|
||||
* SW12
|
||||
*
|
||||
* bit1 bit2 bit3
|
||||
*----------------------------------------------------------------------------
|
||||
* ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
|
||||
* OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
|
||||
*/
|
||||
|
||||
/*
|
||||
* SCIFA5 (CN42)
|
||||
*
|
||||
* S38.3 = ON
|
||||
* S39.6 = ON
|
||||
* S43.1 = ON
|
||||
*/
|
||||
|
||||
/*
|
||||
* LCDC0 (CN3/CN4/CN7)
|
||||
*
|
||||
* S38.1 = OFF
|
||||
* S38.2 = OFF
|
||||
*/
|
||||
|
||||
/*
|
||||
* FPGA
|
||||
*/
|
||||
#define IRQSR0 0x0020
|
||||
#define IRQSR1 0x0022
|
||||
#define IRQMR0 0x0030
|
||||
#define IRQMR1 0x0032
|
||||
#define BUSSWMR1 0x0070
|
||||
#define BUSSWMR2 0x0072
|
||||
#define BUSSWMR3 0x0074
|
||||
#define BUSSWMR4 0x0076
|
||||
|
||||
#define LCDCR 0x10B4
|
||||
#define DEVRSTCR1 0x10D0
|
||||
#define DEVRSTCR2 0x10D2
|
||||
#define A1MDSR 0x10E0
|
||||
#define BVERR 0x1100
|
||||
|
||||
/* FPGA IRQ */
|
||||
#define FPGA_IRQ_BASE (512)
|
||||
#define FPGA_IRQ0 (FPGA_IRQ_BASE)
|
||||
#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
|
||||
#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
|
||||
static u16 bonito_fpga_read(u32 offset)
|
||||
{
|
||||
return __raw_readw(0xf0003000 + offset);
|
||||
}
|
||||
|
||||
static void bonito_fpga_write(u32 offset, u16 val)
|
||||
{
|
||||
__raw_writew(val, 0xf0003000 + offset);
|
||||
}
|
||||
|
||||
static void bonito_fpga_irq_disable(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
|
||||
int shift = irq % 16;
|
||||
|
||||
bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
|
||||
}
|
||||
|
||||
static void bonito_fpga_irq_enable(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
|
||||
int shift = irq % 16;
|
||||
|
||||
bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
|
||||
}
|
||||
|
||||
static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
|
||||
.name = "bonito FPGA",
|
||||
.irq_mask = bonito_fpga_irq_disable,
|
||||
.irq_unmask = bonito_fpga_irq_enable,
|
||||
};
|
||||
|
||||
static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 val = bonito_fpga_read(IRQSR1) << 16 |
|
||||
bonito_fpga_read(IRQSR0);
|
||||
u32 mask = bonito_fpga_read(IRQMR1) << 16 |
|
||||
bonito_fpga_read(IRQMR0);
|
||||
|
||||
int i;
|
||||
|
||||
val &= ~mask;
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (!(val & (1 << i)))
|
||||
continue;
|
||||
|
||||
generic_handle_irq(FPGA_IRQ_BASE + i);
|
||||
}
|
||||
}
|
||||
|
||||
static void bonito_fpga_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
|
||||
bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
|
||||
|
||||
/* Device reset */
|
||||
bonito_fpga_write(DEVRSTCR1,
|
||||
(1 << 2)); /* Eth */
|
||||
|
||||
/* FPGA irq require special handling */
|
||||
for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
|
||||
irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_flags(i, IRQF_VALID); /* yuck */
|
||||
}
|
||||
|
||||
irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
|
||||
irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
|
||||
}
|
||||
|
||||
/*
|
||||
* PMIC settings
|
||||
*
|
||||
* FIXME
|
||||
*
|
||||
* bonito board needs some settings by pmic which use i2c access.
|
||||
* pmic settings use device_initcall() here for use it.
|
||||
*/
|
||||
static __u8 *pmic_settings = NULL;
|
||||
static __u8 pmic_do_2A[] = {
|
||||
0x1C, 0x09,
|
||||
0x1A, 0x80,
|
||||
0xff, 0xff,
|
||||
};
|
||||
|
||||
static int __init pmic_init(void)
|
||||
{
|
||||
struct i2c_adapter *a = i2c_get_adapter(0);
|
||||
struct i2c_msg msg;
|
||||
__u8 buf[2];
|
||||
int i, ret;
|
||||
|
||||
if (!pmic_settings)
|
||||
return 0;
|
||||
if (!a)
|
||||
return 0;
|
||||
|
||||
msg.addr = 0x46;
|
||||
msg.buf = buf;
|
||||
msg.len = 2;
|
||||
msg.flags = 0;
|
||||
|
||||
for (i = 0; ; i += 2) {
|
||||
buf[0] = pmic_settings[i + 0];
|
||||
buf[1] = pmic_settings[i + 1];
|
||||
|
||||
if ((0xff == buf[0]) && (0xff == buf[1]))
|
||||
break;
|
||||
|
||||
ret = i2c_transfer(a, &msg, 1);
|
||||
if (ret < 0) {
|
||||
pr_err("i2c transfer fail\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(pmic_init);
|
||||
|
||||
/*
|
||||
* LCDC0
|
||||
*/
|
||||
static const struct fb_videomode lcdc0_mode = {
|
||||
.name = "WVGA Panel",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.left_margin = 88,
|
||||
.right_margin = 40,
|
||||
.hsync_len = 128,
|
||||
.upper_margin = 20,
|
||||
.lower_margin = 5,
|
||||
.vsync_len = 5,
|
||||
.sync = 0,
|
||||
};
|
||||
|
||||
static struct sh_mobile_lcdc_info lcdc0_info = {
|
||||
.clock_source = LCDC_CLK_BUS,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
.bpp = 16,
|
||||
.interface_type = RGB24,
|
||||
.clock_divider = 5,
|
||||
.flags = 0,
|
||||
.lcd_cfg = &lcdc0_mode,
|
||||
.num_cfg = 1,
|
||||
.lcd_size_cfg = {
|
||||
.width = 152,
|
||||
.height = 91,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource lcdc0_resources[] = {
|
||||
[0] = {
|
||||
.name = "LCDC0",
|
||||
.start = 0xfe940000,
|
||||
.end = 0xfe943fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x0580),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device lcdc0_device = {
|
||||
.name = "sh_mobile_lcdc_fb",
|
||||
.id = 0,
|
||||
.resource = lcdc0_resources,
|
||||
.num_resources = ARRAY_SIZE(lcdc0_resources),
|
||||
.dev = {
|
||||
.platform_data = &lcdc0_info,
|
||||
.coherent_dma_mask = ~0,
|
||||
},
|
||||
};
|
||||
|
||||
/*
|
||||
* SMSC 9221
|
||||
*/
|
||||
static struct resource smsc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x18010000,
|
||||
.end = 0x18011000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = FPGA_ETH_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc_platdata = {
|
||||
.flags = SMSC911X_USE_16BIT,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
};
|
||||
|
||||
static struct platform_device smsc_device = {
|
||||
.name = "smsc911x",
|
||||
.dev = {
|
||||
.platform_data = &smsc_platdata,
|
||||
},
|
||||
.resource = smsc_resources,
|
||||
.num_resources = ARRAY_SIZE(smsc_resources),
|
||||
};
|
||||
|
||||
/*
|
||||
* core board devices
|
||||
*/
|
||||
static struct platform_device *bonito_core_devices[] __initdata = {
|
||||
};
|
||||
|
||||
/*
|
||||
* base board devices
|
||||
*/
|
||||
static struct platform_device *bonito_base_devices[] __initdata = {
|
||||
&lcdc0_device,
|
||||
&smsc_device,
|
||||
};
|
||||
|
||||
/*
|
||||
* map I/O
|
||||
*/
|
||||
static struct map_desc bonito_io_desc[] __initdata = {
|
||||
/*
|
||||
* for CPGA/INTC/PFC
|
||||
* 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
|
||||
*/
|
||||
{
|
||||
.virtual = 0xe6000000,
|
||||
.pfn = __phys_to_pfn(0xe6000000),
|
||||
.length = 160 << 20,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/*
|
||||
* for l2x0_init()
|
||||
* 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
|
||||
*/
|
||||
{
|
||||
.virtual = 0xf0002000,
|
||||
.pfn = __phys_to_pfn(0xf0100000),
|
||||
.length = PAGE_SIZE,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
#endif
|
||||
/*
|
||||
* for FPGA (0x1800000-0x19ffffff)
|
||||
* 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
|
||||
*/
|
||||
{
|
||||
.virtual = 0xf0003000,
|
||||
.pfn = __phys_to_pfn(0x18000000),
|
||||
.length = PAGE_SIZE * 2,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
}
|
||||
};
|
||||
|
||||
static void __init bonito_map_io(void)
|
||||
{
|
||||
iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
|
||||
|
||||
/* setup early devices and console here as well */
|
||||
r8a7740_add_early_devices();
|
||||
shmobile_setup_console();
|
||||
}
|
||||
|
||||
/*
|
||||
* board init
|
||||
*/
|
||||
#define BIT_ON(sw, bit) (sw & (1 << bit))
|
||||
#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
|
||||
|
||||
#define VCCQ1CR 0xE6058140
|
||||
#define VCCQ1LCDCR 0xE6058186
|
||||
|
||||
static void __init bonito_init(void)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
r8a7740_pinmux_init();
|
||||
bonito_fpga_init();
|
||||
|
||||
pmic_settings = pmic_do_2A;
|
||||
|
||||
/*
|
||||
* core board settings
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Early BRESP enable, Shared attribute override enable, 32K*8way */
|
||||
l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
|
||||
#endif
|
||||
|
||||
r8a7740_add_standard_devices();
|
||||
|
||||
platform_add_devices(bonito_core_devices,
|
||||
ARRAY_SIZE(bonito_core_devices));
|
||||
|
||||
/*
|
||||
* base board settings
|
||||
*/
|
||||
gpio_request(GPIO_PORT176, NULL);
|
||||
gpio_direction_input(GPIO_PORT176);
|
||||
if (!gpio_get_value(GPIO_PORT176)) {
|
||||
u16 bsw2;
|
||||
u16 bsw3;
|
||||
u16 bsw4;
|
||||
|
||||
/*
|
||||
* FPGA
|
||||
*/
|
||||
gpio_request(GPIO_FN_CS5B, NULL);
|
||||
gpio_request(GPIO_FN_CS6A, NULL);
|
||||
gpio_request(GPIO_FN_CS5A_PORT105, NULL);
|
||||
gpio_request(GPIO_FN_IRQ10, NULL);
|
||||
|
||||
val = bonito_fpga_read(BVERR);
|
||||
pr_info("bonito version: cpu %02x, base %02x\n",
|
||||
((val >> 8) & 0xFF),
|
||||
((val >> 0) & 0xFF));
|
||||
|
||||
bsw2 = bonito_fpga_read(BUSSWMR2);
|
||||
bsw3 = bonito_fpga_read(BUSSWMR3);
|
||||
bsw4 = bonito_fpga_read(BUSSWMR4);
|
||||
|
||||
/*
|
||||
* SCIFA5 (CN42)
|
||||
*/
|
||||
if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
|
||||
BIT_OFF(bsw3, 9) && /* S39.6 = ON */
|
||||
BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
|
||||
gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
|
||||
gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* LCDC0 (CN3)
|
||||
*/
|
||||
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
|
||||
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
|
||||
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D0, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D1, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D2, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D3, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D4, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D5, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D6, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D7, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D8, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D9, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D10, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D11, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D12, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D13, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D14, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D15, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D16, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D17, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_DCK, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_VSYN, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_HSYN, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_DISP, NULL);
|
||||
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
|
||||
|
||||
gpio_request(GPIO_PORT61, NULL); /* LCDDON */
|
||||
gpio_direction_output(GPIO_PORT61, 1);
|
||||
|
||||
/* backlight on */
|
||||
bonito_fpga_write(LCDCR, 1);
|
||||
|
||||
/* drivability Max */
|
||||
__raw_writew(0x00FF , VCCQ1LCDCR);
|
||||
__raw_writew(0xFFFF , VCCQ1CR);
|
||||
}
|
||||
|
||||
platform_add_devices(bonito_base_devices,
|
||||
ARRAY_SIZE(bonito_base_devices));
|
||||
}
|
||||
}
|
||||
|
||||
static void __init bonito_timer_init(void)
|
||||
{
|
||||
u16 val;
|
||||
u8 md_ck = 0;
|
||||
|
||||
/* read MD_CK value */
|
||||
val = bonito_fpga_read(A1MDSR);
|
||||
if (val & (1 << 10))
|
||||
md_ck |= MD_CK2;
|
||||
if (val & (1 << 9))
|
||||
md_ck |= MD_CK1;
|
||||
if (val & (1 << 8))
|
||||
md_ck |= MD_CK0;
|
||||
|
||||
r8a7740_clock_init(md_ck);
|
||||
shmobile_timer.init();
|
||||
}
|
||||
|
||||
struct sys_timer bonito_timer = {
|
||||
.init = bonito_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(BONITO, "bonito")
|
||||
.map_io = bonito_map_io,
|
||||
.init_irq = r8a7740_init_irq,
|
||||
.handle_irq = shmobile_handle_irq_intc,
|
||||
.init_machine = bonito_init,
|
||||
.timer = &bonito_timer,
|
||||
MACHINE_END
|
||||
157
arch/arm/mach-shmobile/board-marzen.c
Normal file
157
arch/arm/mach-shmobile/board-marzen.c
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* marzen board support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/traps.h>
|
||||
|
||||
/* SMSC LAN89218 */
|
||||
static struct resource smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x18000000, /* ExCS0 */
|
||||
.end = 0x180000ff, /* A1->A7 */
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(28), /* IRQ 1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc911x_platdata = {
|
||||
.flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
};
|
||||
|
||||
static struct platform_device eth_device = {
|
||||
.name = "smsc911x",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &smsc911x_platdata,
|
||||
},
|
||||
.resource = smsc911x_resources,
|
||||
.num_resources = ARRAY_SIZE(smsc911x_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *marzen_devices[] __initdata = {
|
||||
ð_device,
|
||||
};
|
||||
|
||||
static struct map_desc marzen_io_desc[] __initdata = {
|
||||
/* 2M entity map for 0xf0000000 (MPCORE) */
|
||||
{
|
||||
.virtual = 0xf0000000,
|
||||
.pfn = __phys_to_pfn(0xf0000000),
|
||||
.length = SZ_2M,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
/* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
|
||||
{
|
||||
.virtual = 0xfe000000,
|
||||
.pfn = __phys_to_pfn(0xfe000000),
|
||||
.length = SZ_16M,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
},
|
||||
};
|
||||
|
||||
static void __init marzen_map_io(void)
|
||||
{
|
||||
iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
|
||||
}
|
||||
|
||||
static void __init marzen_init_early(void)
|
||||
{
|
||||
r8a7779_add_early_devices();
|
||||
|
||||
/* Early serial console setup is not included here due to
|
||||
* memory map collisions. The SCIF serial ports in r8a7779
|
||||
* are difficult to entity map 1:1 due to collision with the
|
||||
* virtual memory range used by the coherent DMA code on ARM.
|
||||
*
|
||||
* Anyone wanting to debug early can remove UPF_IOREMAP from
|
||||
* the sh-sci serial console platform data, adjust mapbase
|
||||
* to a static M:N virt:phys mapping that needs to be added to
|
||||
* the mappings passed with iotable_init() above.
|
||||
*
|
||||
* Then add a call to shmobile_setup_console() from this function.
|
||||
*
|
||||
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
|
||||
* command line.
|
||||
*/
|
||||
}
|
||||
|
||||
static void __init marzen_init(void)
|
||||
{
|
||||
r8a7779_pinmux_init();
|
||||
|
||||
/* SCIF2 (CN18: DEBUG0) */
|
||||
gpio_request(GPIO_FN_TX2_C, NULL);
|
||||
gpio_request(GPIO_FN_RX2_C, NULL);
|
||||
|
||||
/* SCIF4 (CN19: DEBUG1) */
|
||||
gpio_request(GPIO_FN_TX4, NULL);
|
||||
gpio_request(GPIO_FN_RX4, NULL);
|
||||
|
||||
/* LAN89218 */
|
||||
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
|
||||
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
|
||||
|
||||
r8a7779_add_standard_devices();
|
||||
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
|
||||
}
|
||||
|
||||
static void __init marzen_timer_init(void)
|
||||
{
|
||||
r8a7779_clock_init();
|
||||
shmobile_timer.init();
|
||||
return;
|
||||
}
|
||||
|
||||
struct sys_timer marzen_timer = {
|
||||
.init = marzen_timer_init,
|
||||
};
|
||||
|
||||
MACHINE_START(MARZEN, "marzen")
|
||||
.map_io = marzen_map_io,
|
||||
.init_early = marzen_init_early,
|
||||
.nr_irqs = NR_IRQS_LEGACY,
|
||||
.init_irq = r8a7779_init_irq,
|
||||
.handle_irq = gic_handle_irq,
|
||||
.init_machine = marzen_init,
|
||||
.timer = &marzen_timer,
|
||||
MACHINE_END
|
||||
382
arch/arm/mach-shmobile/clock-r8a7740.c
Normal file
382
arch/arm/mach-shmobile/clock-r8a7740.c
Normal file
|
|
@ -0,0 +1,382 @@
|
|||
/*
|
||||
* R8A7740 processor support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7740.h>
|
||||
|
||||
/*
|
||||
* | MDx | XTAL1/EXTAL1 | System | EXTALR |
|
||||
* Clock |-------+-----------------+ clock | 32.768 | RCLK
|
||||
* Mode | 2/1/0 | src MHz | source | KHz | source
|
||||
* -------+-------+-----------------+-----------+--------+----------
|
||||
* 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
|
||||
* 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
|
||||
* 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
|
||||
* 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
|
||||
* 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
|
||||
* 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
|
||||
* 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
|
||||
* 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
|
||||
*/
|
||||
|
||||
/* CPG registers */
|
||||
#define FRQCRA 0xe6150000
|
||||
#define FRQCRB 0xe6150004
|
||||
#define FRQCRC 0xe61500e0
|
||||
#define PLLC01CR 0xe6150028
|
||||
|
||||
#define SUBCKCR 0xe6150080
|
||||
|
||||
#define MSTPSR0 0xe6150030
|
||||
#define MSTPSR1 0xe6150038
|
||||
#define MSTPSR2 0xe6150040
|
||||
#define MSTPSR3 0xe6150048
|
||||
#define MSTPSR4 0xe615004c
|
||||
#define SMSTPCR0 0xe6150130
|
||||
#define SMSTPCR1 0xe6150134
|
||||
#define SMSTPCR2 0xe6150138
|
||||
#define SMSTPCR3 0xe615013c
|
||||
#define SMSTPCR4 0xe6150140
|
||||
|
||||
/* Fixed 32 KHz root clock from EXTALR pin */
|
||||
static struct clk extalr_clk = {
|
||||
.rate = 32768,
|
||||
};
|
||||
|
||||
/*
|
||||
* 25MHz default rate for the EXTAL1 root input clock.
|
||||
* If needed, reset this with clk_set_rate() from the platform code.
|
||||
*/
|
||||
static struct clk extal1_clk = {
|
||||
.rate = 25000000,
|
||||
};
|
||||
|
||||
/*
|
||||
* 48MHz default rate for the EXTAL2 root input clock.
|
||||
* If needed, reset this with clk_set_rate() from the platform code.
|
||||
*/
|
||||
static struct clk extal2_clk = {
|
||||
.rate = 48000000,
|
||||
};
|
||||
|
||||
/*
|
||||
* 27MHz default rate for the DV_CLKI root input clock.
|
||||
* If needed, reset this with clk_set_rate() from the platform code.
|
||||
*/
|
||||
static struct clk dv_clk = {
|
||||
.rate = 27000000,
|
||||
};
|
||||
|
||||
static unsigned long div_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate / (int)(clk->priv);
|
||||
}
|
||||
|
||||
static struct clk_ops div_clk_ops = {
|
||||
.recalc = div_recalc,
|
||||
};
|
||||
|
||||
/* extal1 / 2 */
|
||||
static struct clk extal1_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &extal1_clk,
|
||||
};
|
||||
|
||||
/* extal1 / 1024 */
|
||||
static struct clk extal1_div1024_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)1024,
|
||||
.parent = &extal1_clk,
|
||||
};
|
||||
|
||||
/* extal1 / 2 / 1024 */
|
||||
static struct clk extal1_div2048_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)1024,
|
||||
.parent = &extal1_div2_clk,
|
||||
};
|
||||
|
||||
/* extal2 / 2 */
|
||||
static struct clk extal2_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &extal2_clk,
|
||||
};
|
||||
|
||||
static struct clk_ops followparent_clk_ops = {
|
||||
.recalc = followparent_recalc,
|
||||
};
|
||||
|
||||
/* Main clock */
|
||||
static struct clk system_clk = {
|
||||
.ops = &followparent_clk_ops,
|
||||
};
|
||||
|
||||
static struct clk system_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &system_clk,
|
||||
};
|
||||
|
||||
/* r_clk */
|
||||
static struct clk r_clk = {
|
||||
.ops = &followparent_clk_ops,
|
||||
};
|
||||
|
||||
/* PLLC0/PLLC1 */
|
||||
static unsigned long pllc01_recalc(struct clk *clk)
|
||||
{
|
||||
unsigned long mult = 1;
|
||||
|
||||
if (__raw_readl(PLLC01CR) & (1 << 14))
|
||||
mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
|
||||
|
||||
return clk->parent->rate * mult;
|
||||
}
|
||||
|
||||
static struct clk_ops pllc01_clk_ops = {
|
||||
.recalc = pllc01_recalc,
|
||||
};
|
||||
|
||||
static struct clk pllc0_clk = {
|
||||
.ops = &pllc01_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.parent = &system_clk,
|
||||
.enable_reg = (void __iomem *)FRQCRC,
|
||||
};
|
||||
|
||||
static struct clk pllc1_clk = {
|
||||
.ops = &pllc01_clk_ops,
|
||||
.flags = CLK_ENABLE_ON_INIT,
|
||||
.parent = &system_div2_clk,
|
||||
.enable_reg = (void __iomem *)FRQCRA,
|
||||
};
|
||||
|
||||
/* PLLC1 / 2 */
|
||||
static struct clk pllc1_div2_clk = {
|
||||
.ops = &div_clk_ops,
|
||||
.priv = (void *)2,
|
||||
.parent = &pllc1_clk,
|
||||
};
|
||||
|
||||
struct clk *main_clks[] = {
|
||||
&extalr_clk,
|
||||
&extal1_clk,
|
||||
&extal2_clk,
|
||||
&extal1_div2_clk,
|
||||
&extal1_div1024_clk,
|
||||
&extal1_div2048_clk,
|
||||
&extal2_div2_clk,
|
||||
&dv_clk,
|
||||
&system_clk,
|
||||
&system_div2_clk,
|
||||
&r_clk,
|
||||
&pllc0_clk,
|
||||
&pllc1_clk,
|
||||
&pllc1_div2_clk,
|
||||
};
|
||||
|
||||
static void div4_kick(struct clk *clk)
|
||||
{
|
||||
unsigned long value;
|
||||
|
||||
/* set KICK bit in FRQCRB to update hardware setting */
|
||||
value = __raw_readl(FRQCRB);
|
||||
value |= (1 << 31);
|
||||
__raw_writel(value, FRQCRB);
|
||||
}
|
||||
|
||||
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
|
||||
24, 32, 36, 48, 0, 72, 96, 0 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
.kick = div4_kick,
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
|
||||
DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
|
||||
DIV4_NR
|
||||
};
|
||||
|
||||
struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
|
||||
[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
|
||||
[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
|
||||
[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
|
||||
[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
|
||||
[DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
DIV6_SUB,
|
||||
DIV6_NR
|
||||
};
|
||||
|
||||
static struct clk div6_clks[DIV6_NR] = {
|
||||
[DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
|
||||
};
|
||||
|
||||
enum {
|
||||
MSTP125,
|
||||
MSTP116, MSTP111, MSTP100, MSTP117,
|
||||
|
||||
MSTP230,
|
||||
MSTP222,
|
||||
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
|
||||
|
||||
MSTP329, MSTP323,
|
||||
|
||||
MSTP_NR
|
||||
};
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
|
||||
[MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
|
||||
[MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
|
||||
[MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
|
||||
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
|
||||
|
||||
[MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
|
||||
[MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
|
||||
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
|
||||
[MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
|
||||
[MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
|
||||
[MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
|
||||
[MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
|
||||
[MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
|
||||
[MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
|
||||
|
||||
[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
|
||||
[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("extalr", &extalr_clk),
|
||||
CLKDEV_CON_ID("extal1", &extal1_clk),
|
||||
CLKDEV_CON_ID("extal2", &extal2_clk),
|
||||
CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
|
||||
CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
|
||||
CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
|
||||
CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
|
||||
CLKDEV_CON_ID("dv_clk", &dv_clk),
|
||||
CLKDEV_CON_ID("system_clk", &system_clk),
|
||||
CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
|
||||
CLKDEV_CON_ID("r_clk", &r_clk),
|
||||
CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
|
||||
CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
|
||||
CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
|
||||
CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
|
||||
CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
|
||||
CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
|
||||
CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
|
||||
CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
|
||||
CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
|
||||
CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
|
||||
CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
|
||||
CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
|
||||
|
||||
/* DIV6 clocks */
|
||||
CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
|
||||
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
|
||||
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
|
||||
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
|
||||
|
||||
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
|
||||
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
|
||||
|
||||
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
|
||||
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
|
||||
};
|
||||
|
||||
void __init r8a7740_clock_init(u8 md_ck)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
/* detect system clock parent */
|
||||
if (md_ck & MD_CK1)
|
||||
system_clk.parent = &extal1_div2_clk;
|
||||
else
|
||||
system_clk.parent = &extal1_clk;
|
||||
|
||||
/* detect RCLK parent */
|
||||
switch (md_ck & (MD_CK2 | MD_CK1)) {
|
||||
case MD_CK2 | MD_CK1:
|
||||
r_clk.parent = &extal1_div2048_clk;
|
||||
break;
|
||||
case MD_CK2:
|
||||
r_clk.parent = &extal1_div1024_clk;
|
||||
break;
|
||||
case MD_CK1:
|
||||
default:
|
||||
r_clk.parent = &extalr_clk;
|
||||
break;
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7740 clocks\n");
|
||||
}
|
||||
176
arch/arm/mach-shmobile/clock-r8a7779.c
Normal file
176
arch/arm/mach-shmobile/clock-r8a7779.c
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* r8a7779 clock framework support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <mach/common.h>
|
||||
|
||||
#define FRQMR 0xffc80014
|
||||
#define MSTPCR0 0xffc80030
|
||||
#define MSTPCR1 0xffc80034
|
||||
#define MSTPCR3 0xffc8003c
|
||||
#define MSTPSR1 0xffc80044
|
||||
#define MSTPSR4 0xffc80048
|
||||
#define MSTPSR6 0xffc8004c
|
||||
#define MSTPCR4 0xffc80050
|
||||
#define MSTPCR5 0xffc80054
|
||||
#define MSTPCR6 0xffc80058
|
||||
#define MSTPCR7 0xffc80040
|
||||
|
||||
/* ioremap() through clock mapping mandatory to avoid
|
||||
* collision with ARM coherent DMA virtual memory range.
|
||||
*/
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = 0xffc80000,
|
||||
.len = 0x80,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk plla_clk = {
|
||||
.rate = 1500000000,
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&plla_clk,
|
||||
};
|
||||
|
||||
static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
|
||||
|
||||
static struct clk_div_mult_table div4_div_mult_table = {
|
||||
.divisors = divisors,
|
||||
.nr_divisors = ARRAY_SIZE(divisors),
|
||||
};
|
||||
|
||||
static struct clk_div4_table div4_table = {
|
||||
.div_mult_table = &div4_div_mult_table,
|
||||
};
|
||||
|
||||
enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
|
||||
|
||||
static struct clk div4_clks[DIV4_NR] = {
|
||||
[DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
|
||||
0x0018, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
|
||||
0x0700, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
|
||||
0x0040, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
|
||||
0x0010, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
|
||||
0x0060, CLK_ENABLE_ON_INIT),
|
||||
[DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
|
||||
0x0300, CLK_ENABLE_ON_INIT),
|
||||
};
|
||||
|
||||
enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
|
||||
MSTP016, MSTP015, MSTP014,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
|
||||
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
|
||||
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
|
||||
[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
|
||||
[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
|
||||
[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
|
||||
[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
|
||||
[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
|
||||
[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
|
||||
};
|
||||
|
||||
static unsigned long mul4_recalc(struct clk *clk)
|
||||
{
|
||||
return clk->parent->rate * 4;
|
||||
}
|
||||
|
||||
static struct clk_ops mul4_clk_ops = {
|
||||
.recalc = mul4_recalc,
|
||||
};
|
||||
|
||||
struct clk clkz_clk = {
|
||||
.ops = &mul4_clk_ops,
|
||||
.parent = &div4_clks[DIV4_S],
|
||||
};
|
||||
|
||||
struct clk clkzs_clk = {
|
||||
/* clks x 4 / 4 = clks */
|
||||
.parent = &div4_clks[DIV4_S],
|
||||
};
|
||||
|
||||
static struct clk *late_main_clks[] = {
|
||||
&clkz_clk,
|
||||
&clkzs_clk,
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("plla_clk", &plla_clk),
|
||||
CLKDEV_CON_ID("clkz_clk", &clkz_clk),
|
||||
CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
|
||||
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
|
||||
CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
|
||||
CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
|
||||
CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
|
||||
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
|
||||
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
|
||||
};
|
||||
|
||||
void __init r8a7779_clock_init(void)
|
||||
{
|
||||
int k, ret = 0;
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
|
||||
ret = clk_register(late_main_clks[k]);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7779 clocks\n");
|
||||
}
|
||||
|
|
@ -14,7 +14,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <asm/memory.h>
|
||||
|
||||
__INIT
|
||||
__CPUINIT
|
||||
|
||||
/*
|
||||
* Reset vector for secondary CPUs.
|
||||
|
|
|
|||
|
|
@ -12,14 +12,43 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/delay.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
static cpumask_t dead_cpus;
|
||||
|
||||
int platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
return 1;
|
||||
int k;
|
||||
|
||||
/* this function is running on another CPU than the offline target,
|
||||
* here we need wait for shutdown code in platform_cpu_die() to
|
||||
* finish before asking SoC-specific code to power off the CPU core.
|
||||
*/
|
||||
for (k = 0; k < 1000; k++) {
|
||||
if (cpumask_test_cpu(cpu, &dead_cpus))
|
||||
return shmobile_platform_cpu_kill(cpu);
|
||||
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void platform_cpu_die(unsigned int cpu)
|
||||
{
|
||||
/* hardware shutdown code running on the CPU that is being offlined */
|
||||
flush_cache_all();
|
||||
dsb();
|
||||
|
||||
/* notify platform_cpu_kill() that hardware shutdown is finished */
|
||||
cpumask_set_cpu(cpu, &dead_cpus);
|
||||
|
||||
/* wait for SoC code in platform_cpu_kill() to shut off CPU core
|
||||
* power. CPU bring up starts from the reset vector.
|
||||
*/
|
||||
while (1) {
|
||||
/*
|
||||
* here's the WFI
|
||||
|
|
@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu)
|
|||
|
||||
int platform_cpu_disable(unsigned int cpu)
|
||||
{
|
||||
cpumask_clear_cpu(cpu, &dead_cpus);
|
||||
/*
|
||||
* we don't allow CPU 0 to be shutdown (it is still too special
|
||||
* e.g. clock tick interrupts)
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
extern struct sys_timer shmobile_timer;
|
||||
extern void shmobile_setup_console(void);
|
||||
extern void shmobile_secondary_vector(void);
|
||||
extern int shmobile_platform_cpu_kill(unsigned int cpu);
|
||||
struct clk;
|
||||
extern int clk_init(void);
|
||||
extern void shmobile_handle_irq_intc(struct pt_regs *);
|
||||
|
|
@ -54,4 +55,23 @@ extern void sh73a0_secondary_init(unsigned int cpu);
|
|||
extern int sh73a0_boot_secondary(unsigned int cpu);
|
||||
extern void sh73a0_smp_prepare_cpus(void);
|
||||
|
||||
extern void r8a7740_init_irq(void);
|
||||
extern void r8a7740_add_early_devices(void);
|
||||
extern void r8a7740_add_standard_devices(void);
|
||||
extern void r8a7740_clock_init(u8 md_ck);
|
||||
extern void r8a7740_pinmux_init(void);
|
||||
|
||||
extern void r8a7779_init_irq(void);
|
||||
extern void r8a7779_add_early_devices(void);
|
||||
extern void r8a7779_add_standard_devices(void);
|
||||
extern void r8a7779_clock_init(void);
|
||||
extern void r8a7779_pinmux_init(void);
|
||||
extern void r8a7779_pm_init(void);
|
||||
|
||||
extern unsigned int r8a7779_get_core_count(void);
|
||||
extern int r8a7779_platform_cpu_kill(unsigned int cpu);
|
||||
extern void r8a7779_secondary_init(unsigned int cpu);
|
||||
extern int r8a7779_boot_secondary(unsigned int cpu);
|
||||
extern void r8a7779_smp_prepare_cpus(void);
|
||||
|
||||
#endif /* __ARCH_MACH_COMMON_H */
|
||||
|
|
|
|||
584
arch/arm/mach-shmobile/include/mach/r8a7740.h
Normal file
584
arch/arm/mach-shmobile/include/mach/r8a7740.h
Normal file
|
|
@ -0,0 +1,584 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_R8A7740_H__
|
||||
#define __ASM_R8A7740_H__
|
||||
|
||||
/*
|
||||
* MD_CKx pin
|
||||
*/
|
||||
#define MD_CK2 (1 << 2)
|
||||
#define MD_CK1 (1 << 1)
|
||||
#define MD_CK0 (1 << 0)
|
||||
|
||||
/*
|
||||
* Pin Function Controller:
|
||||
* GPIO_FN_xx - GPIO used to select pin function
|
||||
* GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
|
||||
*/
|
||||
enum {
|
||||
/* PORT */
|
||||
GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
|
||||
GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
|
||||
|
||||
GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
|
||||
GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
|
||||
|
||||
GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
|
||||
GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
|
||||
|
||||
GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
|
||||
GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
|
||||
|
||||
GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
|
||||
GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
|
||||
|
||||
GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
|
||||
GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
|
||||
|
||||
GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
|
||||
GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
|
||||
|
||||
GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
|
||||
GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
|
||||
|
||||
GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
|
||||
GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
|
||||
|
||||
GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
|
||||
GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
|
||||
|
||||
GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
|
||||
GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
|
||||
|
||||
GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
|
||||
GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
|
||||
|
||||
GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
|
||||
GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
|
||||
|
||||
GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
|
||||
GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
|
||||
|
||||
GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
|
||||
GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
|
||||
|
||||
GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
|
||||
GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
|
||||
|
||||
GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
|
||||
GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
|
||||
|
||||
GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
|
||||
GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
|
||||
|
||||
GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
|
||||
GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
|
||||
|
||||
GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
|
||||
GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
|
||||
|
||||
GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
|
||||
GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
|
||||
|
||||
GPIO_PORT210, GPIO_PORT211,
|
||||
|
||||
/* IRQ */
|
||||
GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
|
||||
GPIO_FN_IRQ1,
|
||||
GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
|
||||
GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
|
||||
GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
|
||||
GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
|
||||
GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
|
||||
GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
|
||||
GPIO_FN_IRQ8,
|
||||
GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
|
||||
GPIO_FN_IRQ10,
|
||||
GPIO_FN_IRQ11,
|
||||
GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
|
||||
GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
|
||||
GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
|
||||
GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
|
||||
GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
|
||||
GPIO_FN_IRQ17,
|
||||
GPIO_FN_IRQ18,
|
||||
GPIO_FN_IRQ19,
|
||||
GPIO_FN_IRQ20,
|
||||
GPIO_FN_IRQ21,
|
||||
GPIO_FN_IRQ22,
|
||||
GPIO_FN_IRQ23,
|
||||
GPIO_FN_IRQ24,
|
||||
GPIO_FN_IRQ25,
|
||||
GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
|
||||
GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
|
||||
GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
|
||||
GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
|
||||
GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
|
||||
GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
|
||||
|
||||
/* Function */
|
||||
|
||||
/* DBGT */
|
||||
GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
|
||||
GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
|
||||
GPIO_FN_DBGMD21,
|
||||
|
||||
/* FSI */
|
||||
GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
|
||||
GPIO_FN_FSIAISLD_PORT5,
|
||||
GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
|
||||
GPIO_FN_FSIASPDIF_PORT18,
|
||||
GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
|
||||
GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
|
||||
GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
|
||||
GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
|
||||
GPIO_FN_FSIAIBT,
|
||||
|
||||
/* FMSI */
|
||||
GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
|
||||
GPIO_FN_FMSISLD_PORT6,
|
||||
GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
|
||||
GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
|
||||
GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
|
||||
GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
|
||||
GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
|
||||
GPIO_FN_FMSOCK,
|
||||
|
||||
/* SCIFA0 */
|
||||
GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
|
||||
GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
|
||||
GPIO_FN_SCIFA0_TXD,
|
||||
|
||||
/* SCIFA1 */
|
||||
GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
|
||||
GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
|
||||
GPIO_FN_SCIFA1_RTS,
|
||||
|
||||
/* SCIFA2 */
|
||||
GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
|
||||
GPIO_FN_SCIFA2_SCK_PORT199,
|
||||
GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
|
||||
GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
|
||||
|
||||
/* SCIFA3 */
|
||||
GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
|
||||
GPIO_FN_SCIFA3_SCK_PORT116,
|
||||
GPIO_FN_SCIFA3_CTS_PORT117,
|
||||
GPIO_FN_SCIFA3_RXD_PORT174,
|
||||
GPIO_FN_SCIFA3_TXD_PORT175,
|
||||
|
||||
GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
|
||||
GPIO_FN_SCIFA3_SCK_PORT158,
|
||||
GPIO_FN_SCIFA3_CTS_PORT162,
|
||||
GPIO_FN_SCIFA3_RXD_PORT159,
|
||||
GPIO_FN_SCIFA3_TXD_PORT160,
|
||||
|
||||
/* SCIFA4 */
|
||||
GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
|
||||
GPIO_FN_SCIFA4_TXD_PORT13,
|
||||
|
||||
GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
|
||||
GPIO_FN_SCIFA4_TXD_PORT203,
|
||||
|
||||
GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
|
||||
GPIO_FN_SCIFA4_TXD_PORT93,
|
||||
|
||||
GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
|
||||
GPIO_FN_SCIFA4_SCK_PORT205,
|
||||
|
||||
/* SCIFA5 */
|
||||
GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
|
||||
GPIO_FN_SCIFA5_RXD_PORT10,
|
||||
|
||||
GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
|
||||
GPIO_FN_SCIFA5_TXD_PORT208,
|
||||
|
||||
GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
|
||||
GPIO_FN_SCIFA5_RXD_PORT92,
|
||||
|
||||
GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
|
||||
GPIO_FN_SCIFA5_SCK_PORT206,
|
||||
|
||||
/* SCIFA6 */
|
||||
GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
|
||||
|
||||
/* SCIFA7 */
|
||||
GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
|
||||
|
||||
/* SCIFAB */
|
||||
GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
|
||||
GPIO_FN_SCIFB_RXD_PORT191,
|
||||
GPIO_FN_SCIFB_TXD_PORT192,
|
||||
GPIO_FN_SCIFB_RTS_PORT186,
|
||||
GPIO_FN_SCIFB_CTS_PORT187,
|
||||
|
||||
GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
|
||||
GPIO_FN_SCIFB_RXD_PORT3,
|
||||
GPIO_FN_SCIFB_TXD_PORT4,
|
||||
GPIO_FN_SCIFB_RTS_PORT172,
|
||||
GPIO_FN_SCIFB_CTS_PORT173,
|
||||
|
||||
/* LCD0 */
|
||||
GPIO_FN_LCDC0_SELECT,
|
||||
GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
|
||||
GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
|
||||
GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
|
||||
GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
|
||||
GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
|
||||
GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
|
||||
GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
|
||||
|
||||
GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
|
||||
GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
|
||||
|
||||
GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
|
||||
GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
|
||||
|
||||
GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
|
||||
GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
|
||||
GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
|
||||
GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
|
||||
|
||||
GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
|
||||
GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
|
||||
GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
|
||||
GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
|
||||
|
||||
/* LCD1 */
|
||||
GPIO_FN_LCDC1_SELECT,
|
||||
GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
|
||||
GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
|
||||
GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
|
||||
GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
|
||||
GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
|
||||
GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
|
||||
GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
|
||||
GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
|
||||
GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
|
||||
GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
|
||||
|
||||
GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
|
||||
GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
|
||||
|
||||
GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
|
||||
GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
|
||||
|
||||
/* RSPI */
|
||||
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
|
||||
GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
|
||||
GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
|
||||
GPIO_FN_RSPI_CK_A,
|
||||
|
||||
/* VIO CKO */
|
||||
GPIO_FN_VIO_CKO1,
|
||||
GPIO_FN_VIO_CKO2,
|
||||
GPIO_FN_VIO_CKO_1,
|
||||
GPIO_FN_VIO_CKO,
|
||||
|
||||
/* VIO0 */
|
||||
GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
|
||||
GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
|
||||
GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
|
||||
GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
|
||||
GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
|
||||
GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
|
||||
|
||||
GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
|
||||
GPIO_FN_VIO0_D14_PORT25,
|
||||
GPIO_FN_VIO0_D15_PORT24,
|
||||
|
||||
GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
|
||||
GPIO_FN_VIO0_D14_PORT95,
|
||||
GPIO_FN_VIO0_D15_PORT96,
|
||||
|
||||
/* VIO1 */
|
||||
GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
|
||||
GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
|
||||
GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
|
||||
GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
|
||||
|
||||
/* TPU0 */
|
||||
GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
|
||||
GPIO_FN_TPU0TO3,
|
||||
GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
|
||||
GPIO_FN_TPU0TO2_PORT202,
|
||||
|
||||
/* SSP1 0 */
|
||||
GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
|
||||
GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
|
||||
GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
|
||||
GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
|
||||
|
||||
/* SSP1 1 */
|
||||
GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
|
||||
GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
|
||||
GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
|
||||
|
||||
GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
|
||||
GPIO_FN_STP1_IPEN_PORT187,
|
||||
|
||||
GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
|
||||
GPIO_FN_STP1_IPEN_PORT193,
|
||||
|
||||
/* SIM */
|
||||
GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
|
||||
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
|
||||
GPIO_FN_SIM_D_PORT199,
|
||||
|
||||
/* SDHI0 */
|
||||
GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
|
||||
GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
|
||||
GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
|
||||
|
||||
/* SDHI1 */
|
||||
GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
|
||||
GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
|
||||
GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
|
||||
|
||||
/* SDHI2 */
|
||||
GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
|
||||
GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
|
||||
|
||||
GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
|
||||
GPIO_FN_SDHI2_WP_PORT25,
|
||||
|
||||
GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
|
||||
GPIO_FN_SDHI2_CD_PORT202,
|
||||
|
||||
/* MSIOF2 */
|
||||
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
|
||||
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
|
||||
GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
|
||||
GPIO_FN_MSIOF2_RSCK,
|
||||
|
||||
/* KEYSC */
|
||||
GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
|
||||
GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
|
||||
GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
|
||||
GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
|
||||
GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
|
||||
|
||||
GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
|
||||
GPIO_FN_KEYIN1_PORT44,
|
||||
GPIO_FN_KEYIN2_PORT45,
|
||||
GPIO_FN_KEYIN3_PORT46,
|
||||
|
||||
GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
|
||||
GPIO_FN_KEYIN1_PORT57,
|
||||
GPIO_FN_KEYIN2_PORT56,
|
||||
GPIO_FN_KEYIN3_PORT55,
|
||||
|
||||
/* VOU */
|
||||
GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
|
||||
GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
|
||||
GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
|
||||
GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
|
||||
GPIO_FN_DV_CLK,
|
||||
GPIO_FN_DV_VSYNC,
|
||||
GPIO_FN_DV_HSYNC,
|
||||
|
||||
/* MEMC */
|
||||
GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
|
||||
GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
|
||||
GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
|
||||
GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
|
||||
GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
|
||||
GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
|
||||
GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
|
||||
|
||||
GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
|
||||
GPIO_FN_MEMC_ADV,
|
||||
GPIO_FN_MEMC_WAIT,
|
||||
GPIO_FN_MEMC_BUSCLK,
|
||||
|
||||
GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
|
||||
GPIO_FN_MEMC_DREQ0,
|
||||
GPIO_FN_MEMC_DREQ1,
|
||||
GPIO_FN_MEMC_A0,
|
||||
|
||||
/* MMC */
|
||||
GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
|
||||
GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
|
||||
GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
|
||||
GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
|
||||
GPIO_FN_MMC0_CLK_PORT66,
|
||||
GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
|
||||
|
||||
GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
|
||||
GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
|
||||
GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
|
||||
GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
|
||||
GPIO_FN_MMC1_CLK_PORT103,
|
||||
GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
|
||||
|
||||
/* MSIOF0 */
|
||||
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
|
||||
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
|
||||
GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
|
||||
GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
|
||||
GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
|
||||
|
||||
/* MSIOF1 */
|
||||
GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
|
||||
GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
|
||||
|
||||
GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
|
||||
GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
|
||||
GPIO_FN_MSIOF1_TSYNC_PORT120,
|
||||
GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
|
||||
|
||||
GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
|
||||
GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
|
||||
GPIO_FN_MSIOF1_RXD_PORT75,
|
||||
GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
|
||||
|
||||
/* GPIO */
|
||||
GPIO_FN_GPO0, GPIO_FN_GPI0,
|
||||
GPIO_FN_GPO1, GPIO_FN_GPI1,
|
||||
|
||||
/* USB0 */
|
||||
GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
|
||||
|
||||
/* USB1 */
|
||||
GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
|
||||
|
||||
/* BBIF1 */
|
||||
GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
|
||||
GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
|
||||
GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
|
||||
|
||||
/* BBIF2 */
|
||||
GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
|
||||
GPIO_FN_BBIF2_RXD2_PORT60,
|
||||
GPIO_FN_BBIF2_TSYNC2_PORT6,
|
||||
GPIO_FN_BBIF2_TSCK2_PORT59,
|
||||
|
||||
GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
|
||||
GPIO_FN_BBIF2_TXD2_PORT183,
|
||||
GPIO_FN_BBIF2_TSCK2_PORT89,
|
||||
GPIO_FN_BBIF2_TSYNC2_PORT184,
|
||||
|
||||
/* BSC / FLCTL / PCMCIA */
|
||||
GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
|
||||
GPIO_FN_CS5B, GPIO_FN_CS6A,
|
||||
GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
|
||||
GPIO_FN_CS5A_PORT19,
|
||||
GPIO_FN_IOIS16, /* ? */
|
||||
|
||||
GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
|
||||
GPIO_FN_A4_FOE, /* share with FLCTL */
|
||||
GPIO_FN_A5_FCDE, /* share with FLCTL */
|
||||
GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
|
||||
GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
|
||||
GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
|
||||
GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
|
||||
GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
|
||||
GPIO_FN_A26,
|
||||
|
||||
GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
|
||||
GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
|
||||
GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
|
||||
GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
|
||||
GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
|
||||
GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
|
||||
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
|
||||
GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
|
||||
|
||||
GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
|
||||
GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
|
||||
GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
|
||||
GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
|
||||
|
||||
GPIO_FN_WE0_FWE, /* share with FLCTL */
|
||||
GPIO_FN_WE1,
|
||||
GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
|
||||
GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
|
||||
GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
|
||||
GPIO_FN_RD_FSC, /* share with FLCTL */
|
||||
GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
|
||||
GPIO_FN_WAIT_PORT90,
|
||||
|
||||
GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
|
||||
|
||||
/* IRDA */
|
||||
GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
|
||||
|
||||
/* ATAPI */
|
||||
GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
|
||||
GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
|
||||
GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
|
||||
GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
|
||||
GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
|
||||
GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
|
||||
GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
|
||||
GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
|
||||
GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
|
||||
GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
|
||||
|
||||
/* RMII */
|
||||
GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
|
||||
GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
|
||||
GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
|
||||
GPIO_FN_RMII_REF50CK, /* for RMII */
|
||||
GPIO_FN_RMII_REF125CK, /* for GMII */
|
||||
|
||||
/* GEther */
|
||||
GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
|
||||
GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
|
||||
GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
|
||||
GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
|
||||
GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
|
||||
GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
|
||||
GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
|
||||
GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
|
||||
GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
|
||||
GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
|
||||
GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
|
||||
GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
|
||||
GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
|
||||
GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
|
||||
|
||||
/* DMA0 */
|
||||
GPIO_FN_DREQ0, GPIO_FN_DACK0,
|
||||
|
||||
/* DMA1 */
|
||||
GPIO_FN_DREQ1, GPIO_FN_DACK1,
|
||||
|
||||
/* SYSC */
|
||||
GPIO_FN_RESETOUTS,
|
||||
GPIO_FN_RESETP_PULLUP,
|
||||
GPIO_FN_RESETP_PLAIN,
|
||||
|
||||
/* SDENC */
|
||||
GPIO_FN_SDENC_CPG,
|
||||
GPIO_FN_SDENC_DV_CLKI,
|
||||
|
||||
/* IRREM */
|
||||
GPIO_FN_IROUT,
|
||||
|
||||
/* DEBUG */
|
||||
GPIO_FN_EDEBGREQ_PULLDOWN,
|
||||
GPIO_FN_EDEBGREQ_PULLUP,
|
||||
|
||||
GPIO_FN_TRACEAUD_FROM_VIO,
|
||||
GPIO_FN_TRACEAUD_FROM_LCDC0,
|
||||
GPIO_FN_TRACEAUD_FROM_MEMC,
|
||||
};
|
||||
|
||||
#endif /* __ASM_R8A7740_H__ */
|
||||
363
arch/arm/mach-shmobile/include/mach/r8a7779.h
Normal file
363
arch/arm/mach-shmobile/include/mach/r8a7779.h
Normal file
|
|
@ -0,0 +1,363 @@
|
|||
#ifndef __ASM_R8A7779_H__
|
||||
#define __ASM_R8A7779_H__
|
||||
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/pm_domain.h>
|
||||
|
||||
/* Pin Function Controller:
|
||||
* GPIO_FN_xx - GPIO used to select pin function
|
||||
* GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
|
||||
*/
|
||||
enum {
|
||||
GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
|
||||
GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
|
||||
GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
|
||||
GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
|
||||
GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
|
||||
GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
|
||||
GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
|
||||
GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
|
||||
|
||||
GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
|
||||
GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
|
||||
GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
|
||||
GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
|
||||
GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
|
||||
GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
|
||||
GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
|
||||
GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
|
||||
|
||||
GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
|
||||
GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
|
||||
GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
|
||||
GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
|
||||
GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
|
||||
GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
|
||||
GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
|
||||
GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
|
||||
|
||||
GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
|
||||
GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
|
||||
GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
|
||||
GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
|
||||
GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
|
||||
GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
|
||||
GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
|
||||
GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
|
||||
|
||||
GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
|
||||
GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
|
||||
GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
|
||||
GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
|
||||
GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
|
||||
GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
|
||||
GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
|
||||
GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
|
||||
|
||||
GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
|
||||
GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
|
||||
GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
|
||||
GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
|
||||
GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
|
||||
GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
|
||||
GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
|
||||
GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
|
||||
|
||||
GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
|
||||
GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
|
||||
GPIO_GP_6_8,
|
||||
|
||||
GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
|
||||
GPIO_FN_A19,
|
||||
|
||||
/* IPSR0 */
|
||||
GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
|
||||
GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
|
||||
GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
|
||||
GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
|
||||
GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
|
||||
GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
|
||||
GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
|
||||
GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
|
||||
GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
|
||||
GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
|
||||
GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
|
||||
GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
|
||||
GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
|
||||
GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
|
||||
GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
|
||||
GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
|
||||
|
||||
/* IPSR1 */
|
||||
GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
|
||||
GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
|
||||
GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
|
||||
GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
|
||||
GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
|
||||
GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
|
||||
GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
|
||||
GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
|
||||
GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
|
||||
GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
|
||||
GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
|
||||
GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
|
||||
GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
|
||||
GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
|
||||
GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
|
||||
GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
|
||||
GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
|
||||
|
||||
/* IPSR2 */
|
||||
GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
|
||||
GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
|
||||
GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
|
||||
GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
|
||||
GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
|
||||
GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
|
||||
GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
|
||||
GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
|
||||
GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
|
||||
GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
|
||||
GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
|
||||
GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
|
||||
GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
|
||||
GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
|
||||
GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
|
||||
GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
|
||||
GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
|
||||
GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
|
||||
GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
|
||||
GPIO_FN_AUDATA2,
|
||||
|
||||
/* IPSR3 */
|
||||
GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
|
||||
GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
|
||||
GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
|
||||
GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
|
||||
GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
|
||||
GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
|
||||
GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
|
||||
GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
|
||||
GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
|
||||
GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
|
||||
GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
|
||||
GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
|
||||
GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
|
||||
GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
|
||||
GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
|
||||
GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
|
||||
GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
|
||||
GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
|
||||
GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
|
||||
|
||||
/* IPSR4 */
|
||||
GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
|
||||
GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
|
||||
GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
|
||||
GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
|
||||
GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
|
||||
GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
|
||||
GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
|
||||
GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
|
||||
GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
|
||||
GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
|
||||
GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
|
||||
GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
|
||||
GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
|
||||
GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
|
||||
GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
|
||||
GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
|
||||
GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
|
||||
GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
|
||||
GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
|
||||
|
||||
/* IPSR5 */
|
||||
GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
|
||||
GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
|
||||
GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
|
||||
GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
|
||||
GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
|
||||
GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
|
||||
GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
|
||||
GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
|
||||
GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
|
||||
GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
|
||||
GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
|
||||
GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
|
||||
GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
|
||||
GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
|
||||
GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
|
||||
GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
|
||||
GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
|
||||
GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
|
||||
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
|
||||
GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
|
||||
GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
|
||||
GPIO_FN_MOUT0,
|
||||
|
||||
/* IPSR6 */
|
||||
GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
|
||||
GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
|
||||
GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
|
||||
GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
|
||||
GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
|
||||
GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
|
||||
GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
|
||||
GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
|
||||
GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
|
||||
GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
|
||||
GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
|
||||
GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
|
||||
GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
|
||||
GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
|
||||
GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
|
||||
GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
|
||||
|
||||
/* IPSR7 */
|
||||
GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
|
||||
GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
|
||||
GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
|
||||
GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
|
||||
GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
|
||||
GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
|
||||
GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
|
||||
GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
|
||||
GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
|
||||
GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
|
||||
GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
|
||||
GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
|
||||
GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
|
||||
GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
|
||||
GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
|
||||
GPIO_FN_CTS1_B,
|
||||
|
||||
/* IPSR8 */
|
||||
GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
|
||||
GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
|
||||
GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
|
||||
GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
|
||||
GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
|
||||
GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
|
||||
GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
|
||||
GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
|
||||
GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
|
||||
GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
|
||||
GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
|
||||
GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
|
||||
GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
|
||||
GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
|
||||
GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
|
||||
GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
|
||||
GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
|
||||
GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
|
||||
GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
|
||||
|
||||
/* IPSR9 */
|
||||
GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
|
||||
GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
|
||||
GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
|
||||
GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
|
||||
GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
|
||||
GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
|
||||
GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
|
||||
GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
|
||||
GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
|
||||
GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
|
||||
GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
|
||||
GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
|
||||
GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
|
||||
GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
|
||||
GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
|
||||
GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
|
||||
GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
|
||||
GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
|
||||
|
||||
/* IPSR10 */
|
||||
GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
|
||||
GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
|
||||
GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
|
||||
GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
|
||||
GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
|
||||
GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
|
||||
GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
|
||||
GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
|
||||
GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
|
||||
GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
|
||||
GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
|
||||
GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
|
||||
GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
|
||||
GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
|
||||
GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
|
||||
GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
|
||||
GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
|
||||
GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
|
||||
GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
|
||||
|
||||
/* IPSR11 */
|
||||
GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
|
||||
GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
|
||||
GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
|
||||
GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
|
||||
GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
|
||||
GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
|
||||
GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
|
||||
GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
|
||||
GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
|
||||
GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
|
||||
GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
|
||||
GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
|
||||
GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
|
||||
GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
|
||||
GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
|
||||
GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
|
||||
GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
|
||||
GPIO_FN_HRTS0_B,
|
||||
|
||||
/* IPSR12 */
|
||||
GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
|
||||
GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
|
||||
GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
|
||||
GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
|
||||
GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
|
||||
GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
|
||||
GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
|
||||
GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
|
||||
GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
|
||||
};
|
||||
|
||||
struct platform_device;
|
||||
|
||||
struct r8a7779_pm_ch {
|
||||
unsigned long chan_offs;
|
||||
unsigned int chan_bit;
|
||||
unsigned int isr_bit;
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
struct r8a7779_pm_ch ch;
|
||||
};
|
||||
|
||||
static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
|
||||
{
|
||||
return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
|
||||
}
|
||||
|
||||
extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
|
||||
extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern struct r8a7779_pm_domain r8a7779_sh4a;
|
||||
extern struct r8a7779_pm_domain r8a7779_sgx;
|
||||
extern struct r8a7779_pm_domain r8a7779_vdp1;
|
||||
extern struct r8a7779_pm_domain r8a7779_impx3;
|
||||
|
||||
extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
|
||||
extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
|
||||
struct platform_device *pdev);
|
||||
#else
|
||||
#define r8a7779_init_pm_domain(pd) do { } while (0)
|
||||
#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
#endif /* __ASM_R8A7779_H__ */
|
||||
631
arch/arm/mach-shmobile/intc-r8a7740.c
Normal file
631
arch/arm/mach-shmobile/intc-r8a7740.c
Normal file
|
|
@ -0,0 +1,631 @@
|
|||
/*
|
||||
* R8A7740 processor support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <mach/intc.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
/*
|
||||
* INTCA
|
||||
*/
|
||||
enum {
|
||||
UNUSED_INTCA = 0,
|
||||
|
||||
/* interrupt sources INTCA */
|
||||
DIRC,
|
||||
ATAPI,
|
||||
IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
|
||||
AP_ARM_COMMTX, AP_ARM_COMMRX,
|
||||
MFI, MFIS,
|
||||
BBIF1, BBIF2,
|
||||
USBHSDMAC,
|
||||
USBF_OUL_SOF, USBF_IXL_INT,
|
||||
SGX540,
|
||||
CMT1_0, CMT1_1, CMT1_2, CMT1_3,
|
||||
CMT2,
|
||||
CMT3,
|
||||
KEYSC,
|
||||
SCIFA0, SCIFA1, SCIFA2, SCIFA3,
|
||||
MSIOF2, MSIOF1,
|
||||
SCIFA4, SCIFA5, SCIFB,
|
||||
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
|
||||
SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
|
||||
SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
|
||||
AP_ARM_L2CINT,
|
||||
IRDA,
|
||||
TPU0,
|
||||
SCIFA6, SCIFA7,
|
||||
GbEther,
|
||||
ICBS0,
|
||||
DDM,
|
||||
SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
|
||||
RWDT0,
|
||||
DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
|
||||
DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
|
||||
DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
|
||||
DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
|
||||
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
|
||||
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
|
||||
SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
|
||||
USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
|
||||
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
|
||||
SPU2_0, SPU2_1,
|
||||
FSI, FMSI,
|
||||
IPMMU,
|
||||
AP_ARM_CTIIRQ, AP_ARM_PMURQ,
|
||||
MFIS2,
|
||||
CPORTR2S,
|
||||
CMT14, CMT15,
|
||||
MMCIF_0, MMCIF_1, MMCIF_2,
|
||||
SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
|
||||
STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
|
||||
|
||||
/* interrupt groups INTCA */
|
||||
DMAC1_1, DMAC1_2,
|
||||
DMAC2_1, DMAC2_2,
|
||||
DMAC3_1, DMAC3_2,
|
||||
AP_ARM1, AP_ARM2,
|
||||
SDHI0, SDHI1, SDHI2,
|
||||
SHWYSTAT,
|
||||
USBF, USBH1, USBH2,
|
||||
RSPI, SPU2, FLCTL, IIC1,
|
||||
};
|
||||
|
||||
static struct intc_vect intca_vectors[] __initdata = {
|
||||
INTC_VECT(DIRC, 0x0560),
|
||||
INTC_VECT(ATAPI, 0x05E0),
|
||||
INTC_VECT(IIC1_ALI, 0x0780),
|
||||
INTC_VECT(IIC1_TACKI, 0x07A0),
|
||||
INTC_VECT(IIC1_WAITI, 0x07C0),
|
||||
INTC_VECT(IIC1_DTEI, 0x07E0),
|
||||
INTC_VECT(AP_ARM_COMMTX, 0x0840),
|
||||
INTC_VECT(AP_ARM_COMMRX, 0x0860),
|
||||
INTC_VECT(MFI, 0x0900),
|
||||
INTC_VECT(MFIS, 0x0920),
|
||||
INTC_VECT(BBIF1, 0x0940),
|
||||
INTC_VECT(BBIF2, 0x0960),
|
||||
INTC_VECT(USBHSDMAC, 0x0A00),
|
||||
INTC_VECT(USBF_OUL_SOF, 0x0A20),
|
||||
INTC_VECT(USBF_IXL_INT, 0x0A40),
|
||||
INTC_VECT(SGX540, 0x0A60),
|
||||
INTC_VECT(CMT1_0, 0x0B00),
|
||||
INTC_VECT(CMT1_1, 0x0B20),
|
||||
INTC_VECT(CMT1_2, 0x0B40),
|
||||
INTC_VECT(CMT1_3, 0x0B60),
|
||||
INTC_VECT(CMT2, 0x0B80),
|
||||
INTC_VECT(CMT3, 0x0BA0),
|
||||
INTC_VECT(KEYSC, 0x0BE0),
|
||||
INTC_VECT(SCIFA0, 0x0C00),
|
||||
INTC_VECT(SCIFA1, 0x0C20),
|
||||
INTC_VECT(SCIFA2, 0x0C40),
|
||||
INTC_VECT(SCIFA3, 0x0C60),
|
||||
INTC_VECT(MSIOF2, 0x0C80),
|
||||
INTC_VECT(MSIOF1, 0x0D00),
|
||||
INTC_VECT(SCIFA4, 0x0D20),
|
||||
INTC_VECT(SCIFA5, 0x0D40),
|
||||
INTC_VECT(SCIFB, 0x0D60),
|
||||
INTC_VECT(FLCTL_FLSTEI, 0x0D80),
|
||||
INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
|
||||
INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
|
||||
INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
|
||||
INTC_VECT(SDHI0_0, 0x0E00),
|
||||
INTC_VECT(SDHI0_1, 0x0E20),
|
||||
INTC_VECT(SDHI0_2, 0x0E40),
|
||||
INTC_VECT(SDHI0_3, 0x0E60),
|
||||
INTC_VECT(SDHI1_0, 0x0E80),
|
||||
INTC_VECT(SDHI1_1, 0x0EA0),
|
||||
INTC_VECT(SDHI1_2, 0x0EC0),
|
||||
INTC_VECT(SDHI1_3, 0x0EE0),
|
||||
INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
|
||||
INTC_VECT(IRDA, 0x0480),
|
||||
INTC_VECT(TPU0, 0x04A0),
|
||||
INTC_VECT(SCIFA6, 0x04C0),
|
||||
INTC_VECT(SCIFA7, 0x04E0),
|
||||
INTC_VECT(GbEther, 0x0500),
|
||||
INTC_VECT(ICBS0, 0x0540),
|
||||
INTC_VECT(DDM, 0x1140),
|
||||
INTC_VECT(SDHI2_0, 0x1200),
|
||||
INTC_VECT(SDHI2_1, 0x1220),
|
||||
INTC_VECT(SDHI2_2, 0x1240),
|
||||
INTC_VECT(SDHI2_3, 0x1260),
|
||||
INTC_VECT(RWDT0, 0x1280),
|
||||
INTC_VECT(DMAC1_1_DEI0, 0x2000),
|
||||
INTC_VECT(DMAC1_1_DEI1, 0x2020),
|
||||
INTC_VECT(DMAC1_1_DEI2, 0x2040),
|
||||
INTC_VECT(DMAC1_1_DEI3, 0x2060),
|
||||
INTC_VECT(DMAC1_2_DEI4, 0x2080),
|
||||
INTC_VECT(DMAC1_2_DEI5, 0x20A0),
|
||||
INTC_VECT(DMAC1_2_DADERR, 0x20C0),
|
||||
INTC_VECT(DMAC2_1_DEI0, 0x2100),
|
||||
INTC_VECT(DMAC2_1_DEI1, 0x2120),
|
||||
INTC_VECT(DMAC2_1_DEI2, 0x2140),
|
||||
INTC_VECT(DMAC2_1_DEI3, 0x2160),
|
||||
INTC_VECT(DMAC2_2_DEI4, 0x2180),
|
||||
INTC_VECT(DMAC2_2_DEI5, 0x21A0),
|
||||
INTC_VECT(DMAC2_2_DADERR, 0x21C0),
|
||||
INTC_VECT(DMAC3_1_DEI0, 0x2200),
|
||||
INTC_VECT(DMAC3_1_DEI1, 0x2220),
|
||||
INTC_VECT(DMAC3_1_DEI2, 0x2240),
|
||||
INTC_VECT(DMAC3_1_DEI3, 0x2260),
|
||||
INTC_VECT(DMAC3_2_DEI4, 0x2280),
|
||||
INTC_VECT(DMAC3_2_DEI5, 0x22A0),
|
||||
INTC_VECT(DMAC3_2_DADERR, 0x22C0),
|
||||
INTC_VECT(SHWYSTAT_RT, 0x1300),
|
||||
INTC_VECT(SHWYSTAT_HS, 0x1320),
|
||||
INTC_VECT(SHWYSTAT_COM, 0x1340),
|
||||
INTC_VECT(USBH_INT, 0x1540),
|
||||
INTC_VECT(USBH_OHCI, 0x1560),
|
||||
INTC_VECT(USBH_EHCI, 0x1580),
|
||||
INTC_VECT(USBH_PME, 0x15A0),
|
||||
INTC_VECT(USBH_BIND, 0x15C0),
|
||||
INTC_VECT(RSPI_OVRF, 0x1780),
|
||||
INTC_VECT(RSPI_SPTEF, 0x17A0),
|
||||
INTC_VECT(RSPI_SPRF, 0x17C0),
|
||||
INTC_VECT(SPU2_0, 0x1800),
|
||||
INTC_VECT(SPU2_1, 0x1820),
|
||||
INTC_VECT(FSI, 0x1840),
|
||||
INTC_VECT(FMSI, 0x1860),
|
||||
INTC_VECT(IPMMU, 0x1920),
|
||||
INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
|
||||
INTC_VECT(AP_ARM_PMURQ, 0x19A0),
|
||||
INTC_VECT(MFIS2, 0x1A00),
|
||||
INTC_VECT(CPORTR2S, 0x1A20),
|
||||
INTC_VECT(CMT14, 0x1A40),
|
||||
INTC_VECT(CMT15, 0x1A60),
|
||||
INTC_VECT(MMCIF_0, 0x1AA0),
|
||||
INTC_VECT(MMCIF_1, 0x1AC0),
|
||||
INTC_VECT(MMCIF_2, 0x1AE0),
|
||||
INTC_VECT(SIM_ERI, 0x1C00),
|
||||
INTC_VECT(SIM_RXI, 0x1C20),
|
||||
INTC_VECT(SIM_TXI, 0x1C40),
|
||||
INTC_VECT(SIM_TEI, 0x1C60),
|
||||
INTC_VECT(STPRO_0, 0x1C80),
|
||||
INTC_VECT(STPRO_1, 0x1CA0),
|
||||
INTC_VECT(STPRO_2, 0x1CC0),
|
||||
INTC_VECT(STPRO_3, 0x1CE0),
|
||||
INTC_VECT(STPRO_4, 0x1D00),
|
||||
};
|
||||
|
||||
static struct intc_group intca_groups[] __initdata = {
|
||||
INTC_GROUP(DMAC1_1,
|
||||
DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
|
||||
INTC_GROUP(DMAC1_2,
|
||||
DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
|
||||
INTC_GROUP(DMAC2_1,
|
||||
DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
|
||||
INTC_GROUP(DMAC2_2,
|
||||
DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
|
||||
INTC_GROUP(DMAC3_1,
|
||||
DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
|
||||
INTC_GROUP(DMAC3_2,
|
||||
DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
|
||||
INTC_GROUP(AP_ARM1,
|
||||
AP_ARM_COMMTX, AP_ARM_COMMRX),
|
||||
INTC_GROUP(AP_ARM2,
|
||||
AP_ARM_CTIIRQ, AP_ARM_PMURQ),
|
||||
INTC_GROUP(USBF,
|
||||
USBF_OUL_SOF, USBF_IXL_INT),
|
||||
INTC_GROUP(SDHI0,
|
||||
SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
|
||||
INTC_GROUP(SDHI1,
|
||||
SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
|
||||
INTC_GROUP(SDHI2,
|
||||
SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
|
||||
INTC_GROUP(SHWYSTAT,
|
||||
SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
|
||||
INTC_GROUP(USBH1, /* FIXME */
|
||||
USBH_INT, USBH_OHCI),
|
||||
INTC_GROUP(USBH2, /* FIXME */
|
||||
USBH_EHCI,
|
||||
USBH_PME, USBH_BIND),
|
||||
INTC_GROUP(RSPI,
|
||||
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
|
||||
INTC_GROUP(SPU2,
|
||||
SPU2_0, SPU2_1),
|
||||
INTC_GROUP(FLCTL,
|
||||
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
|
||||
INTC_GROUP(IIC1,
|
||||
IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intca_mask_registers[] __initdata = {
|
||||
{ /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
|
||||
{ DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
|
||||
0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
|
||||
{ /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
|
||||
{ ATAPI, 0, DIRC, 0,
|
||||
DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
|
||||
{ /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
BBIF1, BBIF2, MFIS, MFI } },
|
||||
{ /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
|
||||
{ DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
|
||||
DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
|
||||
{ /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
|
||||
{ DDM, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
|
||||
{ KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
|
||||
SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
|
||||
{ /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
|
||||
{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
|
||||
0, 0, MSIOF2, 0 } },
|
||||
{ /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
|
||||
{ SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
|
||||
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
|
||||
{ /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
|
||||
{ SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
|
||||
0, USBHSDMAC, 0, AP_ARM_L2CINT } },
|
||||
{ /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
|
||||
{ CMT1_3, CMT1_2, CMT1_1, CMT1_0,
|
||||
CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
|
||||
{ /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
|
||||
{ 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
|
||||
{ IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
|
||||
ICBS0, 0, 0, 0 } },
|
||||
{ /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
|
||||
{ 0, 0, TPU0, SCIFA6,
|
||||
SCIFA7, GbEther, 0, 0 } },
|
||||
{ /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
|
||||
{ SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
|
||||
0, CMT3, 0, RWDT0 } },
|
||||
{ /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
|
||||
{ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
|
||||
0, 0, 0, 0 } },
|
||||
/* IMR1A3 / IMCR1A3 */
|
||||
{ /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
|
||||
{ 0, 0, USBH_INT, USBH_OHCI,
|
||||
USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
|
||||
/* IMR3A3 / IMCR3A3 */
|
||||
{ /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
|
||||
{ /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
|
||||
{ SPU2_0, SPU2_1, FSI, FMSI,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
|
||||
{ 0, IPMMU, 0, 0,
|
||||
AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
|
||||
{ /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
|
||||
{ MFIS2, CPORTR2S, CMT14, CMT15,
|
||||
0, MMCIF_0, MMCIF_1, MMCIF_2 } },
|
||||
/* IMR8A3 / IMCR8A3 */
|
||||
{ /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
|
||||
{ SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
|
||||
STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
|
||||
{ /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
|
||||
{ STPRO_4, 0, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg intca_prio_registers[] __initdata = {
|
||||
{ 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
|
||||
{ 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
|
||||
{ 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
|
||||
{ 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
|
||||
{ 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
|
||||
{ 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
|
||||
SGX540, CMT1_0 } },
|
||||
{ 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
|
||||
SCIFA2, SCIFA3 } },
|
||||
{ 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
|
||||
FLCTL, SDHI0 } },
|
||||
{ 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
|
||||
{ 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
|
||||
AP_ARM_L2CINT, 0 } },
|
||||
{ 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
|
||||
{ 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
|
||||
SCIFA7, GbEther } },
|
||||
{ 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
|
||||
{ 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
|
||||
{ 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
|
||||
{ 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
|
||||
/* IPRBA3 */
|
||||
/* IPRCA3 */
|
||||
/* IPRDA3 */
|
||||
{ 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
|
||||
{ 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
|
||||
/* IPRGA3 */
|
||||
/* IPRHA3 */
|
||||
/* IPRIA3 */
|
||||
{ 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
|
||||
{ 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
|
||||
/* IPRLA3 */
|
||||
{ 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
|
||||
{ 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
|
||||
{ 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
|
||||
CMT14, CMT15 } },
|
||||
{ 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
|
||||
/* IPRQA3 */
|
||||
/* IPRRA3 */
|
||||
{ 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
|
||||
SIM_TXI, SIM_TEI } },
|
||||
{ 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
|
||||
STPRO_2, STPRO_3 } },
|
||||
{ 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
|
||||
intca_vectors, intca_groups,
|
||||
intca_mask_registers, intca_prio_registers,
|
||||
NULL);
|
||||
|
||||
INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
|
||||
INTC_VECT, "r8a7740-intca-irq-pins");
|
||||
|
||||
|
||||
/*
|
||||
* INTCS
|
||||
*/
|
||||
enum {
|
||||
UNUSED_INTCS = 0,
|
||||
|
||||
INTCS,
|
||||
|
||||
/* interrupt sources INTCS */
|
||||
|
||||
/* HUDI */
|
||||
/* STPRO */
|
||||
/* RTDMAC(1) */
|
||||
VPU5HA2,
|
||||
_2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
|
||||
/* MFI */
|
||||
/* BBIF2 */
|
||||
VPU5F,
|
||||
_2DG_BRK_INT,
|
||||
/* SGX540 */
|
||||
/* 2DDMAC */
|
||||
/* IPMMU */
|
||||
/* RTDMAC 2 */
|
||||
/* KEYSC */
|
||||
/* MSIOF */
|
||||
IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
|
||||
TMU0_0, TMU0_1, TMU0_2,
|
||||
CMT0,
|
||||
/* CMT2 */
|
||||
LMB,
|
||||
CTI,
|
||||
VOU,
|
||||
/* RWDT0 */
|
||||
ICB,
|
||||
VIO6C,
|
||||
CEU20, CEU21,
|
||||
JPU,
|
||||
LCDC0,
|
||||
LCRC,
|
||||
/* RTDMAC2(1) */
|
||||
/* RTDMAC2(2) */
|
||||
LCDC1,
|
||||
/* SPU2 */
|
||||
/* FSI */
|
||||
/* FMSI */
|
||||
TMU1_0, TMU1_1, TMU1_2,
|
||||
CMT4,
|
||||
DISP,
|
||||
DSRV,
|
||||
/* MFIS2 */
|
||||
CPORTS2R,
|
||||
|
||||
/* interrupt groups INTCS */
|
||||
_2DG1,
|
||||
IIC0, TMU1,
|
||||
};
|
||||
|
||||
static struct intc_vect intcs_vectors[] = {
|
||||
/* HUDI */
|
||||
/* STPRO */
|
||||
/* RTDMAC(1) */
|
||||
INTCS_VECT(VPU5HA2, 0x0880),
|
||||
INTCS_VECT(_2DG_TRAP, 0x08A0),
|
||||
INTCS_VECT(_2DG_GPM_INT, 0x08C0),
|
||||
INTCS_VECT(_2DG_CER_INT, 0x08E0),
|
||||
/* MFI */
|
||||
/* BBIF2 */
|
||||
INTCS_VECT(VPU5F, 0x0980),
|
||||
INTCS_VECT(_2DG_BRK_INT, 0x09A0),
|
||||
/* SGX540 */
|
||||
/* 2DDMAC */
|
||||
/* IPMMU */
|
||||
/* RTDMAC(2) */
|
||||
/* KEYSC */
|
||||
/* MSIOF */
|
||||
INTCS_VECT(IIC0_ALI, 0x0E00),
|
||||
INTCS_VECT(IIC0_TACKI, 0x0E20),
|
||||
INTCS_VECT(IIC0_WAITI, 0x0E40),
|
||||
INTCS_VECT(IIC0_DTEI, 0x0E60),
|
||||
INTCS_VECT(TMU0_0, 0x0E80),
|
||||
INTCS_VECT(TMU0_1, 0x0EA0),
|
||||
INTCS_VECT(TMU0_2, 0x0EC0),
|
||||
INTCS_VECT(CMT0, 0x0F00),
|
||||
/* CMT2 */
|
||||
INTCS_VECT(LMB, 0x0F60),
|
||||
INTCS_VECT(CTI, 0x0400),
|
||||
INTCS_VECT(VOU, 0x0420),
|
||||
/* RWDT0 */
|
||||
INTCS_VECT(ICB, 0x0480),
|
||||
INTCS_VECT(VIO6C, 0x04E0),
|
||||
INTCS_VECT(CEU20, 0x0500),
|
||||
INTCS_VECT(CEU21, 0x0520),
|
||||
INTCS_VECT(JPU, 0x0560),
|
||||
INTCS_VECT(LCDC0, 0x0580),
|
||||
INTCS_VECT(LCRC, 0x05A0),
|
||||
/* RTDMAC2(1) */
|
||||
/* RTDMAC2(2) */
|
||||
INTCS_VECT(LCDC1, 0x1780),
|
||||
/* SPU2 */
|
||||
/* FSI */
|
||||
/* FMSI */
|
||||
INTCS_VECT(TMU1_0, 0x1900),
|
||||
INTCS_VECT(TMU1_1, 0x1920),
|
||||
INTCS_VECT(TMU1_2, 0x1940),
|
||||
INTCS_VECT(CMT4, 0x1980),
|
||||
INTCS_VECT(DISP, 0x19A0),
|
||||
INTCS_VECT(DSRV, 0x19C0),
|
||||
/* MFIS2 */
|
||||
INTCS_VECT(CPORTS2R, 0x1A20),
|
||||
|
||||
INTC_VECT(INTCS, 0xf80),
|
||||
};
|
||||
|
||||
static struct intc_group intcs_groups[] __initdata = {
|
||||
INTC_GROUP(_2DG1, /*FIXME*/
|
||||
_2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
|
||||
INTC_GROUP(IIC0,
|
||||
IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
|
||||
INTC_GROUP(TMU1,
|
||||
TMU1_0, TMU1_1, TMU1_2),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg intcs_mask_registers[] = {
|
||||
/* IMR0SA / IMCR0SA */ /* all 0 */
|
||||
{ /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
|
||||
{ _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
|
||||
0, 0, 0, 0 /*STPRO*/ } },
|
||||
{ /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
|
||||
{ 0/*STPRO*/, 0, CEU21, VPU5F,
|
||||
0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
|
||||
{ /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
|
||||
{ 0, 0, 0, 0, /*2DDMAC*/
|
||||
VIO6C, 0, 0, ICB } },
|
||||
{ /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
|
||||
{ 0, 0, VOU, CTI,
|
||||
JPU, 0, LCRC, LCDC0 } },
|
||||
/* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
|
||||
/* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
|
||||
{ /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
|
||||
{ 0, TMU0_2, TMU0_1, TMU0_0,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
CEU20, 0, 0, 0 } },
|
||||
{ /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
|
||||
{ 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
|
||||
0, 0, 0, 0 } },
|
||||
/* IMR10SA / IMCR10SA */ /*IPMMU*/
|
||||
{ /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
|
||||
{ IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
|
||||
0, _2DG_BRK_INT, LMB, 0 } },
|
||||
/* IMR12SA / IMCR12SA */
|
||||
/* IMR13SA / IMCR13SA */
|
||||
/* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
|
||||
/* IMR1SA3 / IMCR1SA3 */
|
||||
/* IMR2SA3 / IMCR2SA3 */
|
||||
/* IMR3SA3 / IMCR3SA3 */
|
||||
{ /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
|
||||
{ 0, 0, 0, 0,
|
||||
LCDC1, 0, 0, 0 } },
|
||||
/* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
|
||||
{ /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
|
||||
{ TMU1_0, TMU1_1, TMU1_2, 0,
|
||||
CMT4, DISP, DSRV, 0 } },
|
||||
{ /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
|
||||
{ 0/*MFIS2*/, CPORTS2R, 0, 0,
|
||||
0, 0, 0, 0 } },
|
||||
{ /* INTAMASK */ 0xffd20104, 0, 16,
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, INTCS } },
|
||||
};
|
||||
|
||||
/* Priority is needed for INTCA to receive the INTCS interrupt */
|
||||
static struct intc_prio_reg intcs_prio_registers[] = {
|
||||
{ 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
|
||||
{ 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
|
||||
/* IPRCS */ /*BBIF2*/
|
||||
/* IPRDS */
|
||||
{ 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
|
||||
0/*MFI*/, VPU5F } },
|
||||
{ 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
|
||||
0/*CMT2*/, CMT0 } },
|
||||
{ 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
|
||||
TMU0_2, _2DG1 } },
|
||||
{ 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
|
||||
_2DG_BRK_INT/*FIXME*/ } },
|
||||
{ 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
|
||||
{ 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
|
||||
{ 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
|
||||
{ 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
|
||||
/* IPRMS */ /*RWDT0*/
|
||||
/* IPRAS3 */ /*RTDMAC2(1)*/
|
||||
/* IPRBS3 */ /*RTDMAC2(2)*/
|
||||
/* IPRCS3 */
|
||||
/* IPRDS3 */
|
||||
/* IPRES3 */
|
||||
/* IPRFS3 */
|
||||
/* IPRGS3 */
|
||||
/* IPRHS3 */
|
||||
/* IPRIS3 */
|
||||
{ 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
|
||||
/* IPRKS3 */ /*SPU2/FSI/FMSi*/
|
||||
/* IPRLS3 */
|
||||
{ 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
|
||||
{ 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
|
||||
{ 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
|
||||
/* IPRPS3 */
|
||||
};
|
||||
|
||||
static struct resource intcs_resources[] __initdata = {
|
||||
[0] = {
|
||||
.start = 0xffd20000,
|
||||
.end = 0xffd201ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0xffd50000,
|
||||
.end = 0xffd501ff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
|
||||
static struct intc_desc intcs_desc __initdata = {
|
||||
.name = "r8a7740-intcs",
|
||||
.resource = intcs_resources,
|
||||
.num_resources = ARRAY_SIZE(intcs_resources),
|
||||
.hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
|
||||
intcs_prio_registers, NULL, NULL),
|
||||
};
|
||||
|
||||
static void intcs_demux(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
void __iomem *reg = (void *)irq_get_handler_data(irq);
|
||||
unsigned int evtcodeas = ioread32(reg);
|
||||
|
||||
generic_handle_irq(intcs_evt2irq(evtcodeas));
|
||||
}
|
||||
|
||||
void __init r8a7740_init_irq(void)
|
||||
{
|
||||
void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
|
||||
|
||||
register_intc_controller(&intca_desc);
|
||||
register_intc_controller(&intca_irq_pins_desc);
|
||||
register_intc_controller(&intcs_desc);
|
||||
|
||||
/* demux using INTEVTSA */
|
||||
irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
|
||||
irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
|
||||
}
|
||||
58
arch/arm/mach-shmobile/intc-r8a7779.c
Normal file
58
arch/arm/mach-shmobile/intc-r8a7779.c
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* r8a7779 processor support - INTC hardware block
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/intc.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
#define INT2SMSKCR0 0xfe7822a0
|
||||
#define INT2SMSKCR1 0xfe7822a4
|
||||
#define INT2SMSKCR2 0xfe7822a8
|
||||
#define INT2SMSKCR3 0xfe7822ac
|
||||
#define INT2SMSKCR4 0xfe7822b0
|
||||
|
||||
static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
return 0; /* always allow wakeup */
|
||||
}
|
||||
|
||||
void __init r8a7779_init_irq(void)
|
||||
{
|
||||
void __iomem *gic_dist_base = __io(0xf0001000);
|
||||
void __iomem *gic_cpu_base = __io(0xf0000100);
|
||||
|
||||
/* use GIC to handle interrupts */
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
|
||||
|
||||
/* unmask all known interrupts in INTCS2 */
|
||||
__raw_writel(0xfffffff0, INT2SMSKCR0);
|
||||
__raw_writel(0xfff7ffff, INT2SMSKCR1);
|
||||
__raw_writel(0xfffbffdf, INT2SMSKCR2);
|
||||
__raw_writel(0xbffffffc, INT2SMSKCR3);
|
||||
__raw_writel(0x003fee3f, INT2SMSKCR4);
|
||||
}
|
||||
2562
arch/arm/mach-shmobile/pfc-r8a7740.c
Normal file
2562
arch/arm/mach-shmobile/pfc-r8a7740.c
Normal file
File diff suppressed because it is too large
Load Diff
2645
arch/arm/mach-shmobile/pfc-r8a7779.c
Normal file
2645
arch/arm/mach-shmobile/pfc-r8a7779.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -22,12 +22,16 @@
|
|||
#include <mach/common.h>
|
||||
|
||||
#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
|
||||
#define is_r8a7779() machine_is_marzen()
|
||||
|
||||
static unsigned int __init shmobile_smp_get_core_count(void)
|
||||
{
|
||||
if (is_sh73a0())
|
||||
return sh73a0_get_core_count();
|
||||
|
||||
if (is_r8a7779())
|
||||
return r8a7779_get_core_count();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -35,6 +39,17 @@ static void __init shmobile_smp_prepare_cpus(void)
|
|||
{
|
||||
if (is_sh73a0())
|
||||
sh73a0_smp_prepare_cpus();
|
||||
|
||||
if (is_r8a7779())
|
||||
r8a7779_smp_prepare_cpus();
|
||||
}
|
||||
|
||||
int shmobile_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
if (is_r8a7779())
|
||||
return r8a7779_platform_cpu_kill(cpu);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void __cpuinit platform_secondary_init(unsigned int cpu)
|
||||
|
|
@ -43,6 +58,9 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
|
|||
|
||||
if (is_sh73a0())
|
||||
sh73a0_secondary_init(cpu);
|
||||
|
||||
if (is_r8a7779())
|
||||
r8a7779_secondary_init(cpu);
|
||||
}
|
||||
|
||||
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
||||
|
|
@ -50,6 +68,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|||
if (is_sh73a0())
|
||||
return sh73a0_boot_secondary(cpu);
|
||||
|
||||
if (is_r8a7779())
|
||||
return r8a7779_boot_secondary(cpu);
|
||||
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
|
|
|
|||
249
arch/arm/mach-shmobile/pm-r8a7779.c
Normal file
249
arch/arm/mach-shmobile/pm-r8a7779.c
Normal file
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* r8a7779 Power management support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#include <linux/pm.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/console.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7779.h>
|
||||
|
||||
static void __iomem *r8a7779_sysc_base;
|
||||
|
||||
/* SYSC */
|
||||
#define SYSCSR 0x00
|
||||
#define SYSCISR 0x04
|
||||
#define SYSCISCR 0x08
|
||||
#define SYSCIER 0x0c
|
||||
#define SYSCIMR 0x10
|
||||
#define PWRSR0 0x40
|
||||
#define PWRSR1 0x80
|
||||
#define PWRSR2 0xc0
|
||||
#define PWRSR3 0x100
|
||||
#define PWRSR4 0x140
|
||||
|
||||
#define PWRSR_OFFS 0x00
|
||||
#define PWROFFCR_OFFS 0x04
|
||||
#define PWRONCR_OFFS 0x0c
|
||||
#define PWRER_OFFS 0x14
|
||||
|
||||
#define SYSCSR_RETRIES 100
|
||||
#define SYSCSR_DELAY_US 1
|
||||
|
||||
#define SYSCISR_RETRIES 1000
|
||||
#define SYSCISR_DELAY_US 1
|
||||
|
||||
#if defined(CONFIG_PM) || defined(CONFIG_SMP)
|
||||
|
||||
static DEFINE_SPINLOCK(r8a7779_sysc_lock); /* SMP CPUs + I/O devices */
|
||||
|
||||
static int r8a7779_sysc_pwr_on_off(struct r8a7779_pm_ch *r8a7779_ch,
|
||||
int sr_bit, int reg_offs)
|
||||
{
|
||||
int k;
|
||||
|
||||
for (k = 0; k < SYSCSR_RETRIES; k++) {
|
||||
if (ioread32(r8a7779_sysc_base + SYSCSR) & (1 << sr_bit))
|
||||
break;
|
||||
udelay(SYSCSR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCSR_RETRIES)
|
||||
return -EAGAIN;
|
||||
|
||||
iowrite32(1 << r8a7779_ch->chan_bit,
|
||||
r8a7779_sysc_base + r8a7779_ch->chan_offs + reg_offs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r8a7779_sysc_pwr_off(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_pwr_on_off(r8a7779_ch, 0, PWROFFCR_OFFS);
|
||||
}
|
||||
|
||||
static int r8a7779_sysc_pwr_on(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_pwr_on_off(r8a7779_ch, 1, PWRONCR_OFFS);
|
||||
}
|
||||
|
||||
static int r8a7779_sysc_update(struct r8a7779_pm_ch *r8a7779_ch,
|
||||
int (*on_off_fn)(struct r8a7779_pm_ch *))
|
||||
{
|
||||
unsigned int isr_mask = 1 << r8a7779_ch->isr_bit;
|
||||
unsigned int chan_mask = 1 << r8a7779_ch->chan_bit;
|
||||
unsigned int status;
|
||||
unsigned long flags;
|
||||
int ret = 0;
|
||||
int k;
|
||||
|
||||
spin_lock_irqsave(&r8a7779_sysc_lock, flags);
|
||||
|
||||
iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
|
||||
|
||||
do {
|
||||
ret = on_off_fn(r8a7779_ch);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
status = ioread32(r8a7779_sysc_base +
|
||||
r8a7779_ch->chan_offs + PWRER_OFFS);
|
||||
} while (status & chan_mask);
|
||||
|
||||
for (k = 0; k < SYSCISR_RETRIES; k++) {
|
||||
if (ioread32(r8a7779_sysc_base + SYSCISR) & isr_mask)
|
||||
break;
|
||||
udelay(SYSCISR_DELAY_US);
|
||||
}
|
||||
|
||||
if (k == SYSCISR_RETRIES)
|
||||
ret = -EIO;
|
||||
|
||||
iowrite32(isr_mask, r8a7779_sysc_base + SYSCISCR);
|
||||
|
||||
out:
|
||||
spin_unlock_irqrestore(&r8a7779_sysc_lock, flags);
|
||||
|
||||
pr_debug("r8a7779 power domain %d: %02x %02x %02x %02x %02x -> %d\n",
|
||||
r8a7779_ch->isr_bit, ioread32(r8a7779_sysc_base + PWRSR0),
|
||||
ioread32(r8a7779_sysc_base + PWRSR1),
|
||||
ioread32(r8a7779_sysc_base + PWRSR2),
|
||||
ioread32(r8a7779_sysc_base + PWRSR3),
|
||||
ioread32(r8a7779_sysc_base + PWRSR4), ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_off);
|
||||
}
|
||||
|
||||
int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch)
|
||||
{
|
||||
return r8a7779_sysc_update(r8a7779_ch, r8a7779_sysc_pwr_on);
|
||||
}
|
||||
|
||||
static void __init r8a7779_sysc_init(void)
|
||||
{
|
||||
r8a7779_sysc_base = ioremap_nocache(0xffd85000, PAGE_SIZE);
|
||||
if (!r8a7779_sysc_base)
|
||||
panic("unable to ioremap r8a7779 SYSC hardware block\n");
|
||||
|
||||
/* enable all interrupt sources, but do not use interrupt handler */
|
||||
iowrite32(0x0131000e, r8a7779_sysc_base + SYSCIER);
|
||||
iowrite32(0, r8a7779_sysc_base + SYSCIMR);
|
||||
}
|
||||
|
||||
#else /* CONFIG_PM || CONFIG_SMP */
|
||||
|
||||
static inline void r8a7779_sysc_init(void) {}
|
||||
|
||||
#endif /* CONFIG_PM || CONFIG_SMP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int pd_power_down(struct generic_pm_domain *genpd)
|
||||
{
|
||||
return r8a7779_sysc_power_down(to_r8a7779_ch(genpd));
|
||||
}
|
||||
|
||||
static int pd_power_up(struct generic_pm_domain *genpd)
|
||||
{
|
||||
return r8a7779_sysc_power_up(to_r8a7779_ch(genpd));
|
||||
}
|
||||
|
||||
static bool pd_is_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct r8a7779_pm_ch *r8a7779_ch = to_r8a7779_ch(genpd);
|
||||
unsigned int st;
|
||||
|
||||
st = ioread32(r8a7779_sysc_base + r8a7779_ch->chan_offs + PWRSR_OFFS);
|
||||
if (st & (1 << r8a7779_ch->chan_bit))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool pd_active_wakeup(struct device *dev)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd)
|
||||
{
|
||||
struct generic_pm_domain *genpd = &r8a7779_pd->genpd;
|
||||
|
||||
pm_genpd_init(genpd, NULL, false);
|
||||
genpd->dev_ops.stop = pm_clk_suspend;
|
||||
genpd->dev_ops.start = pm_clk_resume;
|
||||
genpd->dev_ops.active_wakeup = pd_active_wakeup;
|
||||
genpd->dev_irq_safe = true;
|
||||
genpd->power_off = pd_power_down;
|
||||
genpd->power_on = pd_power_up;
|
||||
|
||||
if (pd_is_off(&r8a7779_pd->genpd))
|
||||
pd_power_up(&r8a7779_pd->genpd);
|
||||
}
|
||||
|
||||
void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
|
||||
struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
pm_genpd_add_device(&r8a7779_pd->genpd, dev);
|
||||
if (pm_clk_no_clocks(dev))
|
||||
pm_clk_add(dev, NULL);
|
||||
}
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_sh4a = {
|
||||
.ch = {
|
||||
.chan_offs = 0x80, /* PWRSR1 .. PWRER1 */
|
||||
.isr_bit = 16, /* SH4A */
|
||||
}
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_sgx = {
|
||||
.ch = {
|
||||
.chan_offs = 0xc0, /* PWRSR2 .. PWRER2 */
|
||||
.isr_bit = 20, /* SGX */
|
||||
}
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_vdp1 = {
|
||||
.ch = {
|
||||
.chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
|
||||
.isr_bit = 21, /* VDP */
|
||||
}
|
||||
};
|
||||
|
||||
struct r8a7779_pm_domain r8a7779_impx3 = {
|
||||
.ch = {
|
||||
.chan_offs = 0x140, /* PWRSR4 .. PWRER4 */
|
||||
.isr_bit = 24, /* IMP */
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
void __init r8a7779_pm_init(void)
|
||||
{
|
||||
static int once;
|
||||
|
||||
if (!once++)
|
||||
r8a7779_sysc_init();
|
||||
}
|
||||
352
arch/arm/mach-shmobile/setup-r8a7740.c
Normal file
352
arch/arm/mach-shmobile/setup-r8a7740.c
Normal file
|
|
@ -0,0 +1,352 @@
|
|||
/*
|
||||
* R8A7740 processor support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/delay.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/r8a7740.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
/* SCIFA0 */
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xe6c40000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA1 */
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.mapbase = 0xe6c50000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA2 */
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.mapbase = 0xe6c60000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA3 */
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.mapbase = 0xe6c70000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA4 */
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.mapbase = 0xe6c80000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA5 */
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.mapbase = 0xe6cb0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA6 */
|
||||
static struct plat_sci_port scif6_platform_data = {
|
||||
.mapbase = 0xe6cc0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
|
||||
};
|
||||
|
||||
static struct platform_device scif6_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 6,
|
||||
.dev = {
|
||||
.platform_data = &scif6_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFA7 */
|
||||
static struct plat_sci_port scif7_platform_data = {
|
||||
.mapbase = 0xe6cd0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFA,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
|
||||
};
|
||||
|
||||
static struct platform_device scif7_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 7,
|
||||
.dev = {
|
||||
.platform_data = &scif7_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* SCIFB */
|
||||
static struct plat_sci_port scifb_platform_data = {
|
||||
.mapbase = 0xe6c30000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.scscr = SCSCR_RE | SCSCR_TE,
|
||||
.scbrr_algo_id = SCBRR_ALGO_4,
|
||||
.type = PORT_SCIFB,
|
||||
.irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
|
||||
};
|
||||
|
||||
static struct platform_device scifb_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 8,
|
||||
.dev = {
|
||||
.platform_data = &scifb_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* CMT */
|
||||
static struct sh_timer_config cmt10_platform_data = {
|
||||
.name = "CMT10",
|
||||
.channel_offset = 0x10,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 125,
|
||||
.clocksource_rating = 125,
|
||||
};
|
||||
|
||||
static struct resource cmt10_resources[] = {
|
||||
[0] = {
|
||||
.name = "CMT10",
|
||||
.start = 0xe6138010,
|
||||
.end = 0xe613801b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x0b00),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device cmt10_device = {
|
||||
.name = "sh_cmt",
|
||||
.id = 10,
|
||||
.dev = {
|
||||
.platform_data = &cmt10_platform_data,
|
||||
},
|
||||
.resource = cmt10_resources,
|
||||
.num_resources = ARRAY_SIZE(cmt10_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7740_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&scif6_device,
|
||||
&scif7_device,
|
||||
&scifb_device,
|
||||
&cmt10_device,
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
static struct resource i2c0_resources[] = {
|
||||
[0] = {
|
||||
.name = "IIC0",
|
||||
.start = 0xfff20000,
|
||||
.end = 0xfff20425 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0xe00),
|
||||
.end = intcs_evt2irq(0xe60),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource i2c1_resources[] = {
|
||||
[0] = {
|
||||
.name = "IIC1",
|
||||
.start = 0xe6c20000,
|
||||
.end = 0xe6c20425 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = evt2irq(0x780), /* IIC1_ALI1 */
|
||||
.end = evt2irq(0x7e0), /* IIC1_DTEI1 */
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c0_device = {
|
||||
.name = "i2c-sh_mobile",
|
||||
.id = 0,
|
||||
.resource = i2c0_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c0_resources),
|
||||
};
|
||||
|
||||
static struct platform_device i2c1_device = {
|
||||
.name = "i2c-sh_mobile",
|
||||
.id = 1,
|
||||
.resource = i2c1_resources,
|
||||
.num_resources = ARRAY_SIZE(i2c1_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7740_late_devices[] __initdata = {
|
||||
&i2c0_device,
|
||||
&i2c1_device,
|
||||
};
|
||||
|
||||
#define ICCR 0x0004
|
||||
#define ICSTART 0x0070
|
||||
|
||||
#define i2c_read(reg, offset) ioread8(reg + offset)
|
||||
#define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
|
||||
|
||||
/*
|
||||
* r8a7740 chip has lasting errata on I2C I/O pad reset.
|
||||
* this is work-around for it.
|
||||
*/
|
||||
static void r8a7740_i2c_workaround(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
void __iomem *reg;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (unlikely(!res)) {
|
||||
pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
reg = ioremap(res->start, resource_size(res));
|
||||
if (unlikely(!reg)) {
|
||||
pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
|
||||
i2c_read(reg, ICCR); /* dummy read */
|
||||
|
||||
i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
|
||||
i2c_read(reg, ICSTART); /* dummy read */
|
||||
|
||||
mdelay(100);
|
||||
|
||||
i2c_write(reg, ICCR, 0x01);
|
||||
i2c_read(reg, ICCR);
|
||||
i2c_write(reg, ICSTART, 0x00);
|
||||
i2c_read(reg, ICSTART);
|
||||
|
||||
i2c_write(reg, ICCR, 0x10);
|
||||
mdelay(100);
|
||||
i2c_write(reg, ICCR, 0x00);
|
||||
mdelay(100);
|
||||
i2c_write(reg, ICCR, 0x10);
|
||||
mdelay(100);
|
||||
|
||||
iounmap(reg);
|
||||
}
|
||||
|
||||
void __init r8a7740_add_standard_devices(void)
|
||||
{
|
||||
/* I2C work-around */
|
||||
r8a7740_i2c_workaround(&i2c0_device);
|
||||
r8a7740_i2c_workaround(&i2c1_device);
|
||||
|
||||
platform_add_devices(r8a7740_early_devices,
|
||||
ARRAY_SIZE(r8a7740_early_devices));
|
||||
platform_add_devices(r8a7740_late_devices,
|
||||
ARRAY_SIZE(r8a7740_late_devices));
|
||||
}
|
||||
|
||||
void __init r8a7740_add_early_devices(void)
|
||||
{
|
||||
early_platform_add_devices(r8a7740_early_devices,
|
||||
ARRAY_SIZE(r8a7740_early_devices));
|
||||
}
|
||||
239
arch/arm/mach-shmobile/setup-r8a7779.c
Normal file
239
arch/arm/mach-shmobile/setup-r8a7779.c
Normal file
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* r8a7779 processor support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_intc.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xffe40000,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { gic_spi(88), gic_spi(88),
|
||||
gic_spi(88), gic_spi(88) },
|
||||
};
|
||||
|
||||
static struct platform_device scif0_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &scif0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif1_platform_data = {
|
||||
.mapbase = 0xffe41000,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { gic_spi(89), gic_spi(89),
|
||||
gic_spi(89), gic_spi(89) },
|
||||
};
|
||||
|
||||
static struct platform_device scif1_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &scif1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif2_platform_data = {
|
||||
.mapbase = 0xffe42000,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { gic_spi(90), gic_spi(90),
|
||||
gic_spi(90), gic_spi(90) },
|
||||
};
|
||||
|
||||
static struct platform_device scif2_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &scif2_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif3_platform_data = {
|
||||
.mapbase = 0xffe43000,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { gic_spi(91), gic_spi(91),
|
||||
gic_spi(91), gic_spi(91) },
|
||||
};
|
||||
|
||||
static struct platform_device scif3_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &scif3_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif4_platform_data = {
|
||||
.mapbase = 0xffe44000,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { gic_spi(92), gic_spi(92),
|
||||
gic_spi(92), gic_spi(92) },
|
||||
};
|
||||
|
||||
static struct platform_device scif4_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &scif4_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_sci_port scif5_platform_data = {
|
||||
.mapbase = 0xffe45000,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
|
||||
.scbrr_algo_id = SCBRR_ALGO_2,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { gic_spi(93), gic_spi(93),
|
||||
gic_spi(93), gic_spi(93) },
|
||||
};
|
||||
|
||||
static struct platform_device scif5_device = {
|
||||
.name = "sh-sci",
|
||||
.id = 5,
|
||||
.dev = {
|
||||
.platform_data = &scif5_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* TMU */
|
||||
static struct sh_timer_config tmu00_platform_data = {
|
||||
.name = "TMU00",
|
||||
.channel_offset = 0x4,
|
||||
.timer_bit = 0,
|
||||
.clockevent_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource tmu00_resources[] = {
|
||||
[0] = {
|
||||
.name = "TMU00",
|
||||
.start = 0xffd80008,
|
||||
.end = 0xffd80013,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(32),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device tmu00_device = {
|
||||
.name = "sh_tmu",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &tmu00_platform_data,
|
||||
},
|
||||
.resource = tmu00_resources,
|
||||
.num_resources = ARRAY_SIZE(tmu00_resources),
|
||||
};
|
||||
|
||||
static struct sh_timer_config tmu01_platform_data = {
|
||||
.name = "TMU01",
|
||||
.channel_offset = 0x10,
|
||||
.timer_bit = 1,
|
||||
.clocksource_rating = 200,
|
||||
};
|
||||
|
||||
static struct resource tmu01_resources[] = {
|
||||
[0] = {
|
||||
.name = "TMU01",
|
||||
.start = 0xffd80014,
|
||||
.end = 0xffd8001f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_spi(33),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device tmu01_device = {
|
||||
.name = "sh_tmu",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &tmu01_platform_data,
|
||||
},
|
||||
.resource = tmu01_resources,
|
||||
.num_resources = ARRAY_SIZE(tmu01_resources),
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_early_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&tmu00_device,
|
||||
&tmu01_device,
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_late_devices[] __initdata = {
|
||||
};
|
||||
|
||||
void __init r8a7779_add_standard_devices(void)
|
||||
{
|
||||
r8a7779_pm_init();
|
||||
|
||||
r8a7779_init_pm_domain(&r8a7779_sh4a);
|
||||
r8a7779_init_pm_domain(&r8a7779_sgx);
|
||||
r8a7779_init_pm_domain(&r8a7779_vdp1);
|
||||
r8a7779_init_pm_domain(&r8a7779_impx3);
|
||||
|
||||
platform_add_devices(r8a7779_early_devices,
|
||||
ARRAY_SIZE(r8a7779_early_devices));
|
||||
platform_add_devices(r8a7779_late_devices,
|
||||
ARRAY_SIZE(r8a7779_late_devices));
|
||||
}
|
||||
|
||||
void __init r8a7779_add_early_devices(void)
|
||||
{
|
||||
early_platform_add_devices(r8a7779_early_devices,
|
||||
ARRAY_SIZE(r8a7779_early_devices));
|
||||
}
|
||||
|
|
@ -504,7 +504,7 @@ static struct resource sh7372_dmae0_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.name = "error_irq",
|
||||
.start = evt2irq(0x20c0),
|
||||
.end = evt2irq(0x20c0),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
|
@ -532,7 +532,7 @@ static struct resource sh7372_dmae1_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.name = "error_irq",
|
||||
.start = evt2irq(0x21c0),
|
||||
.end = evt2irq(0x21c0),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
|
@ -560,7 +560,7 @@ static struct resource sh7372_dmae2_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.name = "error_irq",
|
||||
.start = evt2irq(0x22c0),
|
||||
.end = evt2irq(0x22c0),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
|
|
|||
|
|
@ -607,7 +607,7 @@ static struct resource sh73a0_dmae_resources[] = {
|
|||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.name = "error_irq",
|
||||
.start = gic_spi(129),
|
||||
.end = gic_spi(129),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
|
|
|||
153
arch/arm/mach-shmobile/smp-r8a7779.c
Normal file
153
arch/arm/mach-shmobile/smp-r8a7779.c
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/*
|
||||
* SMP support for R-Mobile / SH-Mobile - r8a7779 portion
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/r8a7779.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/smp_twd.h>
|
||||
#include <asm/hardware/gic.h>
|
||||
|
||||
#define AVECR 0xfe700040
|
||||
|
||||
static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
|
||||
.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
|
||||
.chan_bit = 1, /* ARM1 */
|
||||
.isr_bit = 1, /* ARM1 */
|
||||
};
|
||||
|
||||
static struct r8a7779_pm_ch r8a7779_ch_cpu2 = {
|
||||
.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
|
||||
.chan_bit = 2, /* ARM2 */
|
||||
.isr_bit = 2, /* ARM2 */
|
||||
};
|
||||
|
||||
static struct r8a7779_pm_ch r8a7779_ch_cpu3 = {
|
||||
.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
|
||||
.chan_bit = 3, /* ARM3 */
|
||||
.isr_bit = 3, /* ARM3 */
|
||||
};
|
||||
|
||||
static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
|
||||
[1] = &r8a7779_ch_cpu1,
|
||||
[2] = &r8a7779_ch_cpu2,
|
||||
[3] = &r8a7779_ch_cpu3,
|
||||
};
|
||||
|
||||
static void __iomem *scu_base_addr(void)
|
||||
{
|
||||
return (void __iomem *)0xf0000000;
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(scu_lock);
|
||||
static unsigned long tmp;
|
||||
|
||||
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
|
||||
{
|
||||
void __iomem *scu_base = scu_base_addr();
|
||||
|
||||
spin_lock(&scu_lock);
|
||||
tmp = __raw_readl(scu_base + 8);
|
||||
tmp &= ~clr;
|
||||
tmp |= set;
|
||||
spin_unlock(&scu_lock);
|
||||
|
||||
/* disable cache coherency after releasing the lock */
|
||||
__raw_writel(tmp, scu_base + 8);
|
||||
}
|
||||
|
||||
unsigned int __init r8a7779_get_core_count(void)
|
||||
{
|
||||
void __iomem *scu_base = scu_base_addr();
|
||||
|
||||
#ifdef CONFIG_HAVE_ARM_TWD
|
||||
/* twd_base needs to be initialized before percpu_timer_setup() */
|
||||
twd_base = (void __iomem *)0xf0000600;
|
||||
#endif
|
||||
|
||||
return scu_get_core_count(scu_base);
|
||||
}
|
||||
|
||||
int r8a7779_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
struct r8a7779_pm_ch *ch = NULL;
|
||||
int ret = -EIO;
|
||||
|
||||
cpu = cpu_logical_map(cpu);
|
||||
|
||||
/* disable cache coherency */
|
||||
modify_scu_cpu_psr(3 << (cpu * 8), 0);
|
||||
|
||||
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
|
||||
ch = r8a7779_ch_cpu[cpu];
|
||||
|
||||
if (ch)
|
||||
ret = r8a7779_sysc_power_down(ch);
|
||||
|
||||
return ret ? ret : 1;
|
||||
}
|
||||
|
||||
void __cpuinit r8a7779_secondary_init(unsigned int cpu)
|
||||
{
|
||||
gic_secondary_init(0);
|
||||
}
|
||||
|
||||
int __cpuinit r8a7779_boot_secondary(unsigned int cpu)
|
||||
{
|
||||
struct r8a7779_pm_ch *ch = NULL;
|
||||
int ret = -EIO;
|
||||
|
||||
cpu = cpu_logical_map(cpu);
|
||||
|
||||
/* enable cache coherency */
|
||||
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
||||
|
||||
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
|
||||
ch = r8a7779_ch_cpu[cpu];
|
||||
|
||||
if (ch)
|
||||
ret = r8a7779_sysc_power_up(ch);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void __init r8a7779_smp_prepare_cpus(void)
|
||||
{
|
||||
int cpu = cpu_logical_map(0);
|
||||
|
||||
scu_enable(scu_base_addr());
|
||||
|
||||
/* Map the reset vector (in headsmp.S) */
|
||||
__raw_writel(__pa(shmobile_secondary_vector), __io(AVECR));
|
||||
|
||||
/* enable cache coherency on CPU0 */
|
||||
modify_scu_cpu_psr(0, 3 << (cpu * 8));
|
||||
|
||||
r8a7779_pm_init();
|
||||
|
||||
/* power off secondary CPUs */
|
||||
r8a7779_platform_cpu_kill(1);
|
||||
r8a7779_platform_cpu_kill(2);
|
||||
r8a7779_platform_cpu_kill(3);
|
||||
}
|
||||
178
drivers/sh/pfc.c
178
drivers/sh/pfc.c
|
|
@ -135,6 +135,19 @@ static void gpio_write_raw_reg(void __iomem *mapped_reg,
|
|||
BUG();
|
||||
}
|
||||
|
||||
static int gpio_read_bit(struct pinmux_data_reg *dr,
|
||||
unsigned long in_pos)
|
||||
{
|
||||
unsigned long pos;
|
||||
|
||||
pos = dr->reg_width - (in_pos + 1);
|
||||
|
||||
pr_debug("read_bit: addr = %lx, pos = %ld, "
|
||||
"r_width = %ld\n", dr->reg, pos, dr->reg_width);
|
||||
|
||||
return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
|
||||
}
|
||||
|
||||
static void gpio_write_bit(struct pinmux_data_reg *dr,
|
||||
unsigned long in_pos, unsigned long value)
|
||||
{
|
||||
|
|
@ -154,51 +167,69 @@ static void gpio_write_bit(struct pinmux_data_reg *dr,
|
|||
gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
|
||||
}
|
||||
|
||||
static int gpio_read_reg(void __iomem *mapped_reg, unsigned long reg_width,
|
||||
unsigned long field_width, unsigned long in_pos,
|
||||
unsigned long reg)
|
||||
static void config_reg_helper(struct pinmux_info *gpioc,
|
||||
struct pinmux_cfg_reg *crp,
|
||||
unsigned long in_pos,
|
||||
void __iomem **mapped_regp,
|
||||
unsigned long *maskp,
|
||||
unsigned long *posp)
|
||||
{
|
||||
unsigned long data, mask, pos;
|
||||
int k;
|
||||
|
||||
data = 0;
|
||||
mask = (1 << field_width) - 1;
|
||||
pos = reg_width - ((in_pos + 1) * field_width);
|
||||
*mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
|
||||
|
||||
pr_debug("read_reg: addr = %lx, pos = %ld, "
|
||||
"r_width = %ld, f_width = %ld\n",
|
||||
reg, pos, reg_width, field_width);
|
||||
|
||||
data = gpio_read_raw_reg(mapped_reg, reg_width);
|
||||
return (data >> pos) & mask;
|
||||
if (crp->field_width) {
|
||||
*maskp = (1 << crp->field_width) - 1;
|
||||
*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
|
||||
} else {
|
||||
*maskp = (1 << crp->var_field_width[in_pos]) - 1;
|
||||
*posp = crp->reg_width;
|
||||
for (k = 0; k <= in_pos; k++)
|
||||
*posp -= crp->var_field_width[k];
|
||||
}
|
||||
}
|
||||
|
||||
static void gpio_write_reg(void __iomem *mapped_reg, unsigned long reg_width,
|
||||
unsigned long field_width, unsigned long in_pos,
|
||||
unsigned long value, unsigned long reg)
|
||||
static int read_config_reg(struct pinmux_info *gpioc,
|
||||
struct pinmux_cfg_reg *crp,
|
||||
unsigned long field)
|
||||
{
|
||||
void __iomem *mapped_reg;
|
||||
unsigned long mask, pos;
|
||||
|
||||
mask = (1 << field_width) - 1;
|
||||
pos = reg_width - ((in_pos + 1) * field_width);
|
||||
config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
|
||||
|
||||
pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
|
||||
pr_debug("read_reg: addr = %lx, field = %ld, "
|
||||
"r_width = %ld, f_width = %ld\n",
|
||||
reg, value, pos, reg_width, field_width);
|
||||
crp->reg, field, crp->reg_width, crp->field_width);
|
||||
|
||||
return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
|
||||
}
|
||||
|
||||
static void write_config_reg(struct pinmux_info *gpioc,
|
||||
struct pinmux_cfg_reg *crp,
|
||||
unsigned long field, unsigned long value)
|
||||
{
|
||||
void __iomem *mapped_reg;
|
||||
unsigned long mask, pos, data;
|
||||
|
||||
config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
|
||||
|
||||
pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
|
||||
"r_width = %ld, f_width = %ld\n",
|
||||
crp->reg, value, field, crp->reg_width, crp->field_width);
|
||||
|
||||
mask = ~(mask << pos);
|
||||
value = value << pos;
|
||||
|
||||
switch (reg_width) {
|
||||
case 8:
|
||||
iowrite8((ioread8(mapped_reg) & mask) | value, mapped_reg);
|
||||
break;
|
||||
case 16:
|
||||
iowrite16((ioread16(mapped_reg) & mask) | value, mapped_reg);
|
||||
break;
|
||||
case 32:
|
||||
iowrite32((ioread32(mapped_reg) & mask) | value, mapped_reg);
|
||||
break;
|
||||
}
|
||||
data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
|
||||
data &= mask;
|
||||
data |= value;
|
||||
|
||||
if (gpioc->unlock_reg)
|
||||
gpio_write_raw_reg(pfc_phys_to_virt(gpioc, gpioc->unlock_reg),
|
||||
32, ~data);
|
||||
|
||||
gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
|
||||
}
|
||||
|
||||
static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
|
||||
|
|
@ -274,12 +305,13 @@ static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
|
|||
}
|
||||
|
||||
static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
|
||||
struct pinmux_cfg_reg **crp, int *indexp,
|
||||
struct pinmux_cfg_reg **crp,
|
||||
int *fieldp, int *valuep,
|
||||
unsigned long **cntp)
|
||||
{
|
||||
struct pinmux_cfg_reg *config_reg;
|
||||
unsigned long r_width, f_width;
|
||||
int k, n;
|
||||
unsigned long r_width, f_width, curr_width, ncomb;
|
||||
int k, m, n, pos, bit_pos;
|
||||
|
||||
k = 0;
|
||||
while (1) {
|
||||
|
|
@ -290,13 +322,27 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
|
|||
|
||||
if (!r_width)
|
||||
break;
|
||||
for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) {
|
||||
if (config_reg->enum_ids[n] == enum_id) {
|
||||
*crp = config_reg;
|
||||
*indexp = n;
|
||||
*cntp = &config_reg->cnt[n / (1 << f_width)];
|
||||
return 0;
|
||||
|
||||
pos = 0;
|
||||
m = 0;
|
||||
for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
|
||||
if (f_width)
|
||||
curr_width = f_width;
|
||||
else
|
||||
curr_width = config_reg->var_field_width[m];
|
||||
|
||||
ncomb = 1 << curr_width;
|
||||
for (n = 0; n < ncomb; n++) {
|
||||
if (config_reg->enum_ids[pos + n] == enum_id) {
|
||||
*crp = config_reg;
|
||||
*fieldp = m;
|
||||
*valuep = n;
|
||||
*cntp = &config_reg->cnt[m];
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
pos += ncomb;
|
||||
m++;
|
||||
}
|
||||
k++;
|
||||
}
|
||||
|
|
@ -334,43 +380,6 @@ static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
|
|||
return -1;
|
||||
}
|
||||
|
||||
static void write_config_reg(struct pinmux_info *gpioc,
|
||||
struct pinmux_cfg_reg *crp,
|
||||
int index)
|
||||
{
|
||||
unsigned long ncomb, pos, value;
|
||||
void __iomem *mapped_reg;
|
||||
|
||||
ncomb = 1 << crp->field_width;
|
||||
pos = index / ncomb;
|
||||
value = index % ncomb;
|
||||
|
||||
mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
|
||||
|
||||
gpio_write_reg(mapped_reg, crp->reg_width, crp->field_width,
|
||||
pos, value, crp->reg);
|
||||
}
|
||||
|
||||
static int check_config_reg(struct pinmux_info *gpioc,
|
||||
struct pinmux_cfg_reg *crp,
|
||||
int index)
|
||||
{
|
||||
unsigned long ncomb, pos, value;
|
||||
void __iomem *mapped_reg;
|
||||
|
||||
ncomb = 1 << crp->field_width;
|
||||
pos = index / ncomb;
|
||||
value = index % ncomb;
|
||||
|
||||
mapped_reg = pfc_phys_to_virt(gpioc, crp->reg);
|
||||
|
||||
if (gpio_read_reg(mapped_reg, crp->reg_width,
|
||||
crp->field_width, pos, crp->reg) == value)
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
|
||||
|
||||
static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
||||
|
|
@ -379,7 +388,7 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
|||
struct pinmux_cfg_reg *cr = NULL;
|
||||
pinmux_enum_t enum_id;
|
||||
struct pinmux_range *range;
|
||||
int in_range, pos, index;
|
||||
int in_range, pos, field, value;
|
||||
unsigned long *cntp;
|
||||
|
||||
switch (pinmux_type) {
|
||||
|
|
@ -410,7 +419,8 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
|||
|
||||
pos = 0;
|
||||
enum_id = 0;
|
||||
index = 0;
|
||||
field = 0;
|
||||
value = 0;
|
||||
while (1) {
|
||||
pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
|
||||
if (pos <= 0)
|
||||
|
|
@ -457,17 +467,19 @@ static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
|
|||
if (!in_range)
|
||||
continue;
|
||||
|
||||
if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
|
||||
if (get_config_reg(gpioc, enum_id, &cr,
|
||||
&field, &value, &cntp) != 0)
|
||||
goto out_err;
|
||||
|
||||
switch (cfg_mode) {
|
||||
case GPIO_CFG_DRYRUN:
|
||||
if (!*cntp || !check_config_reg(gpioc, cr, index))
|
||||
if (!*cntp ||
|
||||
(read_config_reg(gpioc, cr, field) != value))
|
||||
continue;
|
||||
break;
|
||||
|
||||
case GPIO_CFG_REQ:
|
||||
write_config_reg(gpioc, cr, index);
|
||||
write_config_reg(gpioc, cr, field, value);
|
||||
*cntp = *cntp + 1;
|
||||
break;
|
||||
|
||||
|
|
@ -644,7 +656,7 @@ static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
|
|||
if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
|
||||
return -EINVAL;
|
||||
|
||||
return gpio_read_reg(dr->mapped_reg, dr->reg_width, 1, bit, dr->reg);
|
||||
return gpio_read_bit(dr, bit);
|
||||
}
|
||||
|
||||
static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
|
|
|
|||
|
|
@ -17,7 +17,9 @@
|
|||
defined(CONFIG_ARCH_SH73A0) || \
|
||||
defined(CONFIG_ARCH_SH7367) || \
|
||||
defined(CONFIG_ARCH_SH7377) || \
|
||||
defined(CONFIG_ARCH_SH7372)
|
||||
defined(CONFIG_ARCH_SH7372) || \
|
||||
defined(CONFIG_ARCH_R8A7740)
|
||||
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
|
||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
|
||||
|
|
|
|||
|
|
@ -45,12 +45,19 @@ struct pinmux_cfg_reg {
|
|||
unsigned long reg, reg_width, field_width;
|
||||
unsigned long *cnt;
|
||||
pinmux_enum_t *enum_ids;
|
||||
unsigned long *var_field_width;
|
||||
};
|
||||
|
||||
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
|
||||
.reg = r, .reg_width = r_width, .field_width = f_width, \
|
||||
.cnt = (unsigned long [r_width / f_width]) {}, \
|
||||
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \
|
||||
.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
|
||||
|
||||
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.cnt = (unsigned long [r_width]) {}, \
|
||||
.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
|
||||
.enum_ids = (pinmux_enum_t [])
|
||||
|
||||
struct pinmux_data_reg {
|
||||
unsigned long reg, reg_width, reg_shadow;
|
||||
|
|
@ -109,6 +116,8 @@ struct pinmux_info {
|
|||
unsigned int num_resources;
|
||||
struct pfc_window *window;
|
||||
|
||||
unsigned long unlock_reg;
|
||||
|
||||
struct gpio_chip chip;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user