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ufs: add support for DesignWare Controller
This patch has the goal to add support for DesignWare UFS Controller specific operations. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Reviewed-by: Hannes Reinicke <hare@suse.de> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Joao Pinto
Martin K. Petersen
parent
79fcc03349
commit
4b9ffb5a35
@ -11770,6 +11770,12 @@ S: Supported
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F: Documentation/scsi/ufs.txt
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F: drivers/scsi/ufs/
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UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER DWC HOOKS
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M: Joao Pinto <Joao.Pinto@synopsys.com>
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L: linux-scsi@vger.kernel.org
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S: Supported
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F: drivers/scsi/ufs/*dwc*
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UNSORTED BLOCK IMAGES (UBI)
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M: Artem Bityutskiy <dedekind1@gmail.com>
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M: Richard Weinberger <richard@nod.at>
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150
drivers/scsi/ufs/ufshcd-dwc.c
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150
drivers/scsi/ufs/ufshcd-dwc.c
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@ -0,0 +1,150 @@
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/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "ufshcd.h"
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#include "unipro.h"
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#include "ufshcd-dwc.h"
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#include "ufshci-dwc.h"
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int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
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const struct ufshcd_dme_attr_val *v, int n)
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{
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int ret = 0;
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int attr_node = 0;
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for (attr_node = 0; attr_node < n; attr_node++) {
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ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel,
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ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer);
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if (ret)
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return ret;
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}
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return 0;
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}
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EXPORT_SYMBOL(ufshcd_dwc_dme_set_attrs);
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/**
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* ufshcd_dwc_program_clk_div()
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* This function programs the clk divider value. This value is needed to
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* provide 1 microsecond tick to unipro layer.
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* @hba: Private Structure pointer
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* @divider_val: clock divider value to be programmed
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*
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*/
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static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
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{
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ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
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}
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/**
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* ufshcd_dwc_link_is_up()
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* Check if link is up
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* @hba: private structure poitner
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*
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* Returns 0 on success, non-zero value on failure
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*/
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static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
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{
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int dme_result = 0;
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ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result);
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if (dme_result == UFSHCD_LINK_IS_UP) {
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ufshcd_set_link_active(hba);
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return 0;
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}
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return 1;
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}
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/**
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* ufshcd_dwc_connection_setup()
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* This function configures both the local side (host) and the peer side
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* (device) unipro attributes to establish the connection to application/
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* cport.
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* This function is not required if the hardware is properly configured to
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* have this connection setup on reset. But invoking this function does no
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* harm and should be fine even working with any ufs device.
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*
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* @hba: pointer to drivers private data
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*
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* Returns 0 on success non-zero value on failure
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*/
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static int ufshcd_dwc_connection_setup(struct ufs_hba *hba)
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{
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const struct ufshcd_dme_attr_val setup_attrs[] = {
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{ UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL },
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{ UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL },
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{ UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL },
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{ UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL },
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{ UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL },
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{ UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL },
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{ UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL },
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{ UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL },
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{ UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL },
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{ UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_PEER },
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{ UIC_ARG_MIB(N_DEVICEID), 1, DME_PEER },
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{ UIC_ARG_MIB(N_DEVICEID_VALID), 1, DME_PEER },
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{ UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_PEER },
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{ UIC_ARG_MIB(T_PEERCPORTID), 0, DME_PEER },
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{ UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_PEER },
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{ UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_PEER },
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{ UIC_ARG_MIB(T_CPORTMODE), 1, DME_PEER },
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{ UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_PEER }
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};
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return ufshcd_dwc_dme_set_attrs(hba, setup_attrs, ARRAY_SIZE(setup_attrs));
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}
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/**
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* ufshcd_dwc_link_startup_notify()
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* UFS Host DWC specific link startup sequence
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* @hba: private structure poitner
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* @status: Callback notify status
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*
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* Returns 0 on success, non-zero value on failure
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*/
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int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status)
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{
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int err = 0;
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if (status == PRE_CHANGE) {
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ufshcd_dwc_program_clk_div(hba, DWC_UFS_REG_HCLKDIV_DIV_125);
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if (hba->vops->phy_initialization) {
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err = hba->vops->phy_initialization(hba);
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if (err) {
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dev_err(hba->dev, "Phy setup failed (%d)\n",
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err);
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goto out;
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}
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}
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} else { /* POST_CHANGE */
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err = ufshcd_dwc_link_is_up(hba);
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if (err) {
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dev_err(hba->dev, "Link is not up\n");
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goto out;
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}
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err = ufshcd_dwc_connection_setup(hba);
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if (err)
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dev_err(hba->dev, "Connection setup failed (%d)\n",
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err);
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}
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out:
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return err;
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}
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EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
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26
drivers/scsi/ufs/ufshcd-dwc.h
Normal file
26
drivers/scsi/ufs/ufshcd-dwc.h
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@ -0,0 +1,26 @@
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/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _UFSHCD_DWC_H
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#define _UFSHCD_DWC_H
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struct ufshcd_dme_attr_val {
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u32 attr_sel;
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u32 mib_val;
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u8 peer;
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};
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int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status);
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int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
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const struct ufshcd_dme_attr_val *v, int n);
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#endif /* End of Header */
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@ -264,6 +264,7 @@ struct ufs_pwr_mode_info {
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* @suspend: called during host controller PM callback
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* @resume: called during host controller PM callback
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* @dbg_register_dump: used to dump controller debug information
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* @phy_initialization: used to initialize phys
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*/
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struct ufs_hba_variant_ops {
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const char *name;
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@ -285,6 +286,7 @@ struct ufs_hba_variant_ops {
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int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
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int (*resume)(struct ufs_hba *, enum ufs_pm_op);
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void (*dbg_register_dump)(struct ufs_hba *hba);
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int (*phy_initialization)(struct ufs_hba *);
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};
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/* clock gating state */
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@ -567,11 +569,16 @@ static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
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static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
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{
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/* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/
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#ifndef CONFIG_SCSI_UFS_DWC
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if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
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!(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
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return true;
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else
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return false;
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#else
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return true;
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#endif
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}
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#define ufshcd_writel(hba, val, reg) \
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36
drivers/scsi/ufs/ufshci-dwc.h
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36
drivers/scsi/ufs/ufshci-dwc.h
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@ -0,0 +1,36 @@
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/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _UFSHCI_DWC_H
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#define _UFSHCI_DWC_H
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/* DWC HC UFSHCI specific Registers */
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enum dwc_specific_registers {
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DWC_UFS_REG_HCLKDIV = 0xFC,
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};
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/* Clock Divider Values: Hex equivalent of frequency in MHz */
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enum clk_div_values {
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DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
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DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
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DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
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};
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/* Selector Index */
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enum selector_index {
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SELIND_LN0_TX = 0x00,
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SELIND_LN1_TX = 0x01,
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SELIND_LN0_RX = 0x04,
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SELIND_LN1_RX = 0x05,
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};
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#endif /* End of Header */
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