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drm/radeon/uvd: lower msg&fb buffer requirements on UVD3

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Starting with UVD3 message and feedback buffers have their
own 256MB segment, so no need to force them into VRAM any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König 2013-09-23 09:42:32 +02:00 committed by Alex Deucher
parent 4a1132a023
commit 4b40e59212
3 changed files with 5 additions and 5 deletions
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3
drivers/gpu/drm/radeon/radeon_cs.c
View File

@ -85,8 +85,9 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
VRAM, also but everything into VRAM on AGP cards to avoid
image corruptions */
if (p->ring == R600_RING_TYPE_UVD_INDEX &&
p->rdev->family < CHIP_PALM &&
(i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
/* TODO: is this still needed for NI+ ? */
p->relocs[i].lobj.domain =
RADEON_GEM_DOMAIN_VRAM;

3
drivers/gpu/drm/radeon/radeon_uvd.c
View File

@ -476,8 +476,7 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
return -EINVAL;
}
/* TODO: is this still necessary on NI+ ? */
if ((cmd == 0 || cmd == 0x3) &&
if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
start, end);

4
drivers/gpu/drm/radeon/uvd_v1_0.c
View File

@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev)
/* enable VCPU clock */
WREG32(UVD_VCPU_CNTL, 1 << 9);
/* enable UMC */
WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
/* enable UMC and NC0 */
WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));
/* boot up the VCPU */
WREG32(UVD_SOFT_RESET, 0);