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drm/amdgpu/gfx8: add ring reset callback for gfx
Add ring reset callback for gfx. v2: fix operator precedence (kernel test robot) Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -6149,6 +6149,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
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{
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bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
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bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
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bool exec = flags & AMDGPU_FENCE_FLAG_EXEC;
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/* Workaround for cache flush problems. First send a dummy EOP
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* event down the pipe with seq one below.
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@ -6172,7 +6173,8 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
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EOP_TC_ACTION_EN |
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EOP_TC_WB_ACTION_EN |
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EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
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EVENT_INDEX(5)));
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EVENT_INDEX(5) |
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(exec ? EOP_EXEC : 0)));
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amdgpu_ring_write(ring, addr & 0xfffffffc);
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amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
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DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
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@ -6380,6 +6382,34 @@ static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
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amdgpu_ring_write(ring, val);
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}
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static void gfx_v8_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
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int mem_space, int opt, uint32_t addr0,
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uint32_t addr1, uint32_t ref, uint32_t mask,
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uint32_t inv)
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{
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amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
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amdgpu_ring_write(ring,
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/* memory (1) or register (0) */
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(WAIT_REG_MEM_MEM_SPACE(mem_space) |
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WAIT_REG_MEM_OPERATION(opt) | /* wait */
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WAIT_REG_MEM_FUNCTION(3) | /* equal */
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WAIT_REG_MEM_ENGINE(eng_sel)));
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if (mem_space)
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BUG_ON(addr0 & 0x3); /* Dword align */
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amdgpu_ring_write(ring, addr0);
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amdgpu_ring_write(ring, addr1);
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amdgpu_ring_write(ring, ref);
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amdgpu_ring_write(ring, mask);
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amdgpu_ring_write(ring, inv); /* poll interval */
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}
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static void gfx_v8_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask)
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{
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gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
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}
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static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
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{
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struct amdgpu_device *adev = ring->adev;
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@ -6856,6 +6886,48 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
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}
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static int gfx_v8_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
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struct amdgpu_ring *kiq_ring = &kiq->ring;
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unsigned long flags;
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u32 tmp;
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int r;
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if (amdgpu_sriov_vf(adev))
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return -EINVAL;
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if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
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return -EINVAL;
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spin_lock_irqsave(&kiq->ring_lock, flags);
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if (amdgpu_ring_alloc(kiq_ring, 5)) {
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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return -ENOMEM;
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}
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tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid);
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gfx_v8_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp);
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amdgpu_ring_commit(kiq_ring);
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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r = amdgpu_ring_test_ring(kiq_ring);
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if (r)
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return r;
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if (amdgpu_ring_alloc(ring, 7 + 12 + 5))
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return -ENOMEM;
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gfx_v8_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr,
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ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC);
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gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff);
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gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0);
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return amdgpu_ring_test_ring(ring);
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}
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static const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
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.name = "gfx_v8_0",
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.early_init = gfx_v8_0_early_init,
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@ -6923,6 +6995,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
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.emit_wreg = gfx_v8_0_ring_emit_wreg,
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.soft_recovery = gfx_v8_0_ring_soft_recovery,
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.emit_mem_sync = gfx_v8_0_emit_mem_sync,
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.reset = gfx_v8_0_reset_kgq,
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};
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static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
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@ -246,6 +246,7 @@
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* 1 - Stream
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* 2 - Bypass
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*/
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#define EOP_EXEC (1 << 28) /* For Trailing Fence */
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#define DATA_SEL(x) ((x) << 29)
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/* 0 - discard
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* 1 - send low 32bit data
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