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crypto: ccp - Add support for PCI device 0x17E0
PCI device 0x17E0 includes new TEE offsets, doesn't support a platform mailbox, and does support platform doorbell so introduce a new structure to represent it. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -361,6 +361,14 @@ static const struct tee_vdata teev1 = {
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.ring_rptr_reg = 0x10554, /* C2PMSG_21 */
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};
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static const struct tee_vdata teev2 = {
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.cmdresp_reg = 0x10944, /* C2PMSG_17 */
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.cmdbuff_addr_lo_reg = 0x10948, /* C2PMSG_18 */
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.cmdbuff_addr_hi_reg = 0x1094c, /* C2PMSG_19 */
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.ring_wptr_reg = 0x10950, /* C2PMSG_20 */
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.ring_rptr_reg = 0x10954, /* C2PMSG_21 */
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};
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static const struct platform_access_vdata pa_v1 = {
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.cmdresp_reg = 0x10570, /* C2PMSG_28 */
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.cmdbuff_addr_lo_reg = 0x10574, /* C2PMSG_29 */
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@ -369,6 +377,11 @@ static const struct platform_access_vdata pa_v1 = {
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.doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */
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};
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static const struct platform_access_vdata pa_v2 = {
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.doorbell_button_reg = 0x10a24, /* C2PMSG_73 */
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.doorbell_cmd_reg = 0x10a40, /* C2PMSG_80 */
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};
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static const struct psp_vdata pspv1 = {
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.sev = &sevv1,
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.feature_reg = 0x105fc, /* C2PMSG_63 */
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@ -399,6 +412,14 @@ static const struct psp_vdata pspv4 = {
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.intsts_reg = 0x10694, /* P2CMSG_INTSTS */
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};
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static const struct psp_vdata pspv5 = {
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.tee = &teev2,
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.platform_access = &pa_v2,
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.feature_reg = 0x109fc, /* C2PMSG_63 */
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.inten_reg = 0x10510, /* P2CMSG_INTEN */
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.intsts_reg = 0x10514, /* P2CMSG_INTSTS */
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};
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#endif
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static const struct sp_dev_vdata dev_vdata[] = {
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@ -451,6 +472,12 @@ static const struct sp_dev_vdata dev_vdata[] = {
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.bar = 2,
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#ifdef CONFIG_CRYPTO_DEV_SP_PSP
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.psp_vdata = &pspv3,
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#endif
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},
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{ /* 7 */
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.bar = 2,
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#ifdef CONFIG_CRYPTO_DEV_SP_PSP
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.psp_vdata = &pspv5,
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#endif
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},
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};
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@ -463,6 +490,7 @@ static const struct pci_device_id sp_pci_table[] = {
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{ PCI_VDEVICE(AMD, 0x14CA), (kernel_ulong_t)&dev_vdata[5] },
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{ PCI_VDEVICE(AMD, 0x15C7), (kernel_ulong_t)&dev_vdata[6] },
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{ PCI_VDEVICE(AMD, 0x1649), (kernel_ulong_t)&dev_vdata[6] },
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{ PCI_VDEVICE(AMD, 0x17E0), (kernel_ulong_t)&dev_vdata[7] },
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/* Last entry must be zero */
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{ 0, }
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};
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