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drm/nouveau/fifo: add id_engine hook

Browse Source 
Will be used by common code in subsequent commits to lookup driver
engine state from HW engine ID.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2021-02-09 13:06:35 +10:00
parent 3e7d4a0cad
commit 496162037c
10 changed files with 97 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
View File

@ -38,6 +38,52 @@ g84_fifo_uevent_init(struct nvkm_fifo *fifo)
nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
}
static struct nvkm_engine *
g84_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
{
struct nvkm_device *device = fifo->engine.subdev.device;
struct nvkm_engine *engine;
enum nvkm_subdev_type type;
switch (engi) {
case G84_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break;
case G84_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break;
case G84_FIFO_ENGN_MPEG :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPPP, 0)))
return engine;
type = NVKM_ENGINE_MPEG;
break;
case G84_FIFO_ENGN_ME :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_CE, 0)))
return engine;
type = NVKM_ENGINE_ME;
break;
case G84_FIFO_ENGN_VP :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSPDEC, 0)))
return engine;
type = NVKM_ENGINE_VP;
break;
case G84_FIFO_ENGN_CIPHER:
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_VIC, 0)))
return engine;
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_SEC, 0)))
return engine;
type = NVKM_ENGINE_CIPHER;
break;
case G84_FIFO_ENGN_BSP :
if ((engine = nvkm_device_engine(device, NVKM_ENGINE_MSVLD, 0)))
return engine;
type = NVKM_ENGINE_BSP;
break;
case G84_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break;
default:
WARN_ON(1);
return NULL;
}
return nvkm_device_engine(fifo->engine.subdev.device, type, 0);
}
static int
g84_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
@ -67,6 +113,7 @@ g84_fifo = {
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = g84_fifo_engine_id,
.id_engine = g84_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.uevent_init = g84_fifo_uevent_init,

28
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -105,23 +105,26 @@ gf100_fifo_runlist_insert(struct gf100_fifo *fifo, struct gf100_fifo_chan *chan)
mutex_unlock(&fifo->base.mutex);
}
static inline struct nvkm_engine *
gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
static struct nvkm_engine *
gf100_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
{
struct nvkm_device *device = fifo->base.engine.subdev.device;
enum nvkm_subdev_type type;
int inst;
switch (engn) {
case 0: engn = NVKM_ENGINE_GR; break;
case 1: engn = NVKM_ENGINE_MSVLD; break;
case 2: engn = NVKM_ENGINE_MSPPP; break;
case 3: engn = NVKM_ENGINE_MSPDEC; break;
case 4: engn = NVKM_ENGINE_CE0; break;
case 5: engn = NVKM_ENGINE_CE1; break;
switch (engi) {
case GF100_FIFO_ENGN_GR : type = NVKM_ENGINE_GR ; inst = 0; break;
case GF100_FIFO_ENGN_MSPDEC: type = NVKM_ENGINE_MSPDEC; inst = 0; break;
case GF100_FIFO_ENGN_MSPPP : type = NVKM_ENGINE_MSPPP ; inst = 0; break;
case GF100_FIFO_ENGN_MSVLD : type = NVKM_ENGINE_MSVLD ; inst = 0; break;
case GF100_FIFO_ENGN_CE0 : type = NVKM_ENGINE_CE ; inst = 0; break;
case GF100_FIFO_ENGN_CE1 : type = NVKM_ENGINE_CE ; inst = 1; break;
case GF100_FIFO_ENGN_SW : type = NVKM_ENGINE_SW ; inst = 0; break;
default:
WARN_ON(1);
return NULL;
}
return nvkm_device_engine(device, engn, 0);
return nvkm_device_engine(fifo->engine.subdev.device, type, inst);
}
static int
@ -337,7 +340,7 @@ gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo)
if (busy && unk0 && unk1) {
list_for_each_entry(chan, &fifo->chan, head) {
if (chan->base.chid == chid) {
engine = gf100_fifo_engine(fifo, engn);
engine = gf100_fifo_id_engine(&fifo->base, engn);
if (!engine)
break;
gf100_fifo_recover(fifo, engine, chan);
@ -676,6 +679,7 @@ gf100_fifo = {
.intr = gf100_fifo_intr,
.fault = gf100_fifo_fault,
.engine_id = gf100_fifo_engine_id,
.id_engine = gf100_fifo_id_engine,
.uevent_init = gf100_fifo_uevent_init,
.uevent_fini = gf100_fifo_uevent_fini,
.chan = {

7
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -258,6 +258,12 @@ gk104_fifo_pbdma = {
.init = gk104_fifo_pbdma_init,
};
struct nvkm_engine *
gk104_fifo_id_engine(struct nvkm_fifo *base, int engi)
{
return gk104_fifo(base)->engine[engi].engine;
}
int
gk104_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
@ -1037,6 +1043,7 @@ gk104_fifo_ = {
.intr = gk104_fifo_intr,
.fault = gk104_fifo_fault,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = gk104_fifo_recover_chan,

19
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
View File

@ -94,6 +94,24 @@ __releases(fifo->base.lock)
spin_unlock_irqrestore(&fifo->base.lock, flags);
}
struct nvkm_engine *
nv04_fifo_id_engine(struct nvkm_fifo *fifo, int engi)
{
enum nvkm_subdev_type type;
switch (engi) {
case NV04_FIFO_ENGN_SW : type = NVKM_ENGINE_SW; break;
case NV04_FIFO_ENGN_GR : type = NVKM_ENGINE_GR; break;
case NV04_FIFO_ENGN_MPEG: type = NVKM_ENGINE_MPEG; break;
case NV04_FIFO_ENGN_DMA : type = NVKM_ENGINE_DMAOBJ; break;
default:
WARN_ON(1);
return NULL;
}
return nvkm_device_engine(fifo->engine.subdev.device, type, 0);
}
int
nv04_fifo_engine_id(struct nvkm_fifo *base, struct nvkm_engine *engine)
{
@ -364,6 +382,7 @@ nv04_fifo = {
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
View File

@ -44,6 +44,7 @@ nv10_fifo = {
.init = nv04_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
View File

@ -82,6 +82,7 @@ nv17_fifo = {
.init = nv17_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
View File

@ -113,6 +113,7 @@ nv40_fifo = {
.init = nv40_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
View File

@ -132,6 +132,7 @@ nv50_fifo = {
.init = nv50_fifo_init,
.intr = nv04_fifo_intr,
.engine_id = nv04_fifo_engine_id,
.id_engine = nv04_fifo_id_engine,
.pause = nv04_fifo_pause,
.start = nv04_fifo_start,
.chan = {

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
View File

@ -24,6 +24,7 @@ struct nvkm_fifo_func {
void (*intr)(struct nvkm_fifo *);
void (*fault)(struct nvkm_fifo *, struct nvkm_fault_data *);
int (*engine_id)(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *(*id_engine)(struct nvkm_fifo *, int engi);
void (*pause)(struct nvkm_fifo *, unsigned long *);
void (*start)(struct nvkm_fifo *, unsigned long *);
void (*uevent_init)(struct nvkm_fifo *);
@ -37,10 +38,12 @@ struct nvkm_fifo_func {
void nv04_fifo_intr(struct nvkm_fifo *);
int nv04_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *nv04_fifo_id_engine(struct nvkm_fifo *, int);
void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
void gf100_fifo_intr_fault(struct nvkm_fifo *, int);
int gk104_fifo_engine_id(struct nvkm_fifo *, struct nvkm_engine *);
struct nvkm_engine *gk104_fifo_id_engine(struct nvkm_fifo *, int);
#endif

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
View File

@ -457,6 +457,7 @@ tu102_fifo_ = {
.intr = tu102_fifo_intr,
.fault = tu102_fifo_fault,
.engine_id = gk104_fifo_engine_id,
.id_engine = gk104_fifo_id_engine,
.uevent_init = gk104_fifo_uevent_init,
.uevent_fini = gk104_fifo_uevent_fini,
.recover_chan = tu102_fifo_recover_chan,