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Merge tag 'drm-hisilicon-next-2016-04-29' of github.com:xin3liang/linux into drm-next
drm-hisilicon-next for 4.7 Add new hisilicon kirin drm driver: - Add maintainer for hisilicon DRM driver - Add support for external bridge - Add designware dsi host driver - Add designware dsi encoder driver - Add cma fbdev and hotplug - Add vblank driver for ADE - Add plane driver for ADE - Add crtc driver for ADE - Add hisilicon kirin drm master driver - Add device tree binding for hi6220 display subsystem * tag 'drm-hisilicon-next-2016-04-29' of github.com:xin3liang/linux: MAINTAINERS: Add maintainer for hisilicon DRM driver drm/hisilicon: Add support for external bridge drm/hisilicon: Add designware dsi host driver drm/hisilicon: Add designware dsi encoder driver drm/hisilicon: Add cma fbdev and hotplug drm/hisilicon: Add vblank driver for ADE drm/hisilicon: Add plane driver for ADE drm/hisilicon: Add crtc driver for ADE drm/hisilicon: Add hisilicon kirin drm master driver drm/hisilicon: Add device tree binding for hi6220 display subsystem
This commit is contained in:
Dave Airlie
commit
4946dd2e14
@ -0,0 +1,72 @@
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Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
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A DSI Host Controller resides in the middle of display controller and external
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HDMI converter or panel.
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Required properties:
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- compatible: value should be "hisilicon,hi6220-dsi".
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- reg: physical base address and length of dsi controller's registers.
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- clocks: contains APB clock phandle + clock-specifier pair.
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- clock-names: should be "pclk".
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- ports: contains DSI controller input and output sub port.
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The input port connects to ADE output port with the reg value "0".
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The output port with the reg value "1", it could connect to panel or
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any other bridge endpoints.
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See Documentation/devicetree/bindings/graph.txt for more device graph info.
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A example of HiKey board hi6220 SoC and board specific DT entry:
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Example:
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SoC specific:
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dsi: dsi@f4107800 {
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compatible = "hisilicon,hi6220-dsi";
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reg = <0x0 0xf4107800 0x0 0x100>;
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clocks = <&media_ctrl HI6220_DSI_PCLK>;
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clock-names = "pclk";
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 0 for input port */
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port@0 {
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reg = <0>;
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dsi_in: endpoint {
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remote-endpoint = <&ade_out>;
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};
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};
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};
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};
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Board specific:
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&dsi {
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status = "ok";
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ports {
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/* 1 for output port */
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port@1 {
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reg = <1>;
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dsi_out0: endpoint@0 {
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remote-endpoint = <&adv7533_in>;
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};
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};
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};
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};
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&i2c2 {
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...
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adv7533: adv7533@39 {
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...
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port {
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adv7533_in: endpoint {
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remote-endpoint = <&dsi_out0>;
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};
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};
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};
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};
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@ -0,0 +1,64 @@
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Device-Tree bindings for hisilicon ADE display controller driver
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ADE (Advanced Display Engine) is the display controller which grab image
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data from memory, do composition, do post image processing, generate RGB
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timing stream and transfer to DSI.
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Required properties:
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- compatible: value should be "hisilicon,hi6220-ade".
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- reg: physical base address and length of the ADE controller's registers.
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- hisilicon,noc-syscon: ADE NOC QoS syscon.
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- resets: The ADE reset controller node.
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- interrupt: the ldi vblank interrupt number used.
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- clocks: a list of phandle + clock-specifier pairs, one for each entry
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in clock-names.
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- clock-names: should contain:
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"clk_ade_core" for the ADE core clock.
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"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
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jpeg codec.
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"clk_ade_pix" for the ADE pixel clok.
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- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
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phandle + clock-specifier pairs.
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- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
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The rate of "clk_ade_core" could be "360000000" or "180000000";
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The rate of "clk_codec_jpeg" could be or less than "1440000000".
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These rate values could be configured according to performance and power
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consumption.
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- port: the output port. This contains one endpoint subnode, with its
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remote-endpoint set to the phandle of the connected DSI input endpoint.
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See Documentation/devicetree/bindings/graph.txt for more device graph info.
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Optional properties:
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- dma-coherent: Present if dma operations are coherent.
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A example of HiKey board hi6220 SoC specific DT entry:
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Example:
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ade: ade@f4100000 {
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compatible = "hisilicon,hi6220-ade";
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reg = <0x0 0xf4100000 0x0 0x7800>;
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reg-names = "ade_base";
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hisilicon,noc-syscon = <&medianoc_ade>;
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resets = <&media_ctrl MEDIA_ADE>;
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interrupts = <0 115 4>; /* ldi interrupt */
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clocks = <&media_ctrl HI6220_ADE_CORE>,
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<&media_ctrl HI6220_CODEC_JPEG>,
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<&media_ctrl HI6220_ADE_PIX_SRC>;
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/*clock name*/
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clock-names = "clk_ade_core",
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"clk_codec_jpeg",
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"clk_ade_pix";
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assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
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<&media_ctrl HI6220_CODEC_JPEG>;
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assigned-clock-rates = <360000000>, <288000000>;
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dma-coherent;
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port {
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ade_out: endpoint {
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remote-endpoint = <&dsi_in>;
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};
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};
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};
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10
MAINTAINERS
10
MAINTAINERS
@ -3853,6 +3853,16 @@ T: git git://github.com/patjak/drm-gma500
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S: Maintained
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F: drivers/gpu/drm/gma500/
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DRM DRIVERS FOR HISILICON
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M: Xinliang Liu <z.liuxinliang@hisilicon.com>
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R: Xinwei Kong <kong.kongxinwei@hisilicon.com>
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R: Chen Feng <puck.chen@hisilicon.com>
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L: dri-devel@lists.freedesktop.org
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T: git git://github.com/xin3liang/linux.git
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S: Maintained
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F: drivers/gpu/drm/hisilicon/
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F: Documentation/devicetree/bindings/display/hisilicon/
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DRM DRIVERS FOR NVIDIA TEGRA
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M: Thierry Reding <thierry.reding@gmail.com>
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M: Terje Bergström <tbergstrom@nvidia.com>
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@ -285,3 +285,5 @@ source "drivers/gpu/drm/vc4/Kconfig"
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source "drivers/gpu/drm/etnaviv/Kconfig"
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source "drivers/gpu/drm/arc/Kconfig"
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source "drivers/gpu/drm/hisilicon/Kconfig"
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@ -80,3 +80,4 @@ obj-y += bridge/
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obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
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obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/
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obj-$(CONFIG_DRM_ARCPGU)+= arc/
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obj-y += hisilicon/
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5
drivers/gpu/drm/hisilicon/Kconfig
Normal file
5
drivers/gpu/drm/hisilicon/Kconfig
Normal file
@ -0,0 +1,5 @@
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#
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# hisilicon drm device configuration.
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# Please keep this list sorted alphabetically
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source "drivers/gpu/drm/hisilicon/kirin/Kconfig"
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5
drivers/gpu/drm/hisilicon/Makefile
Normal file
5
drivers/gpu/drm/hisilicon/Makefile
Normal file
@ -0,0 +1,5 @@
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#
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# Makefile for hisilicon drm drivers.
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# Please keep this list sorted alphabetically
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obj-$(CONFIG_DRM_HISI_KIRIN) += kirin/
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18
drivers/gpu/drm/hisilicon/kirin/Kconfig
Normal file
18
drivers/gpu/drm/hisilicon/kirin/Kconfig
Normal file
@ -0,0 +1,18 @@
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config DRM_HISI_KIRIN
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tristate "DRM Support for Hisilicon Kirin series SoCs Platform"
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depends on DRM && OF && ARM64
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select DRM_KMS_HELPER
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select DRM_GEM_CMA_HELPER
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select DRM_KMS_CMA_HELPER
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help
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Choose this option if you have a hisilicon Kirin chipsets(hi6220).
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If M is selected the module will be called kirin-drm.
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config HISI_KIRIN_DW_DSI
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tristate "HiSilicon Kirin specific extensions for Synopsys DW MIPI DSI"
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depends on DRM_HISI_KIRIN
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select DRM_MIPI_DSI
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help
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This selects support for HiSilicon Kirin SoC specific extensions for
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the Synopsys DesignWare DSI driver. If you want to enable MIPI DSI on
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hi6220 based SoC, you should selet this option.
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6
drivers/gpu/drm/hisilicon/kirin/Makefile
Normal file
6
drivers/gpu/drm/hisilicon/kirin/Makefile
Normal file
@ -0,0 +1,6 @@
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kirin-drm-y := kirin_drm_drv.o \
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kirin_drm_ade.o
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obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o
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obj-$(CONFIG_HISI_KIRIN_DW_DSI) += dw_drm_dsi.o
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857
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
Normal file
857
drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
Normal file
@ -0,0 +1,857 @@
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/*
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* DesignWare MIPI DSI Host Controller v1.02 driver
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*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2014-2016 Hisilicon Limited.
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*
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* Author:
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* Xinliang Liu <z.liuxinliang@hisilicon.com>
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* Xinliang Liu <xinliang.liu@linaro.org>
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* Xinwei Kong <kong.kongxinwei@hisilicon.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_graph.h>
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#include <drm/drm_of.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_mipi_dsi.h>
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#include <drm/drm_encoder_slave.h>
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#include <drm/drm_atomic_helper.h>
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#include "dw_dsi_reg.h"
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#define MAX_TX_ESC_CLK 10
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#define ROUND(x, y) ((x) / (y) + \
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((x) % (y) * 10 / (y) >= 5 ? 1 : 0))
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#define PHY_REF_CLK_RATE 19200000
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#define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000))
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#define encoder_to_dsi(encoder) \
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container_of(encoder, struct dw_dsi, encoder)
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#define host_to_dsi(host) \
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container_of(host, struct dw_dsi, host)
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struct mipi_phy_params {
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u32 clk_t_lpx;
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u32 clk_t_hs_prepare;
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u32 clk_t_hs_zero;
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u32 clk_t_hs_trial;
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u32 clk_t_wakeup;
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u32 data_t_lpx;
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u32 data_t_hs_prepare;
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u32 data_t_hs_zero;
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u32 data_t_hs_trial;
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u32 data_t_ta_go;
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u32 data_t_ta_get;
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u32 data_t_wakeup;
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u32 hstx_ckg_sel;
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u32 pll_fbd_div5f;
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u32 pll_fbd_div1f;
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u32 pll_fbd_2p;
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u32 pll_enbwt;
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u32 pll_fbd_p;
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u32 pll_fbd_s;
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u32 pll_pre_div1p;
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u32 pll_pre_p;
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u32 pll_vco_750M;
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u32 pll_lpf_rs;
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u32 pll_lpf_cs;
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u32 clklp2hs_time;
|
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u32 clkhs2lp_time;
|
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u32 lp2hs_time;
|
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u32 hs2lp_time;
|
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u32 clk_to_data_delay;
|
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u32 data_to_clk_delay;
|
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u32 lane_byte_clk_kHz;
|
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u32 clk_division;
|
||||
};
|
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|
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struct dsi_hw_ctx {
|
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void __iomem *base;
|
||||
struct clk *pclk;
|
||||
};
|
||||
|
||||
struct dw_dsi {
|
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struct drm_encoder encoder;
|
||||
struct drm_bridge *bridge;
|
||||
struct mipi_dsi_host host;
|
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struct drm_display_mode cur_mode;
|
||||
struct dsi_hw_ctx *ctx;
|
||||
struct mipi_phy_params phy;
|
||||
|
||||
u32 lanes;
|
||||
enum mipi_dsi_pixel_format format;
|
||||
unsigned long mode_flags;
|
||||
bool enable;
|
||||
};
|
||||
|
||||
struct dsi_data {
|
||||
struct dw_dsi dsi;
|
||||
struct dsi_hw_ctx ctx;
|
||||
};
|
||||
|
||||
struct dsi_phy_range {
|
||||
u32 min_range_kHz;
|
||||
u32 max_range_kHz;
|
||||
u32 pll_vco_750M;
|
||||
u32 hstx_ckg_sel;
|
||||
};
|
||||
|
||||
static const struct dsi_phy_range dphy_range_info[] = {
|
||||
{ 46875, 62500, 1, 7 },
|
||||
{ 62500, 93750, 0, 7 },
|
||||
{ 93750, 125000, 1, 6 },
|
||||
{ 125000, 187500, 0, 6 },
|
||||
{ 187500, 250000, 1, 5 },
|
||||
{ 250000, 375000, 0, 5 },
|
||||
{ 375000, 500000, 1, 4 },
|
||||
{ 500000, 750000, 0, 4 },
|
||||
{ 750000, 1000000, 1, 0 },
|
||||
{ 1000000, 1500000, 0, 0 }
|
||||
};
|
||||
|
||||
static u32 dsi_calc_phy_rate(u32 req_kHz, struct mipi_phy_params *phy)
|
||||
{
|
||||
u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
|
||||
u32 tmp_kHz = req_kHz;
|
||||
u32 i = 0;
|
||||
u32 q_pll = 1;
|
||||
u32 m_pll = 0;
|
||||
u32 n_pll = 0;
|
||||
u32 r_pll = 1;
|
||||
u32 m_n = 0;
|
||||
u32 m_n_int = 0;
|
||||
u32 f_kHz = 0;
|
||||
u64 temp;
|
||||
|
||||
/*
|
||||
* Find a rate >= req_kHz.
|
||||
*/
|
||||
do {
|
||||
f_kHz = tmp_kHz;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++)
|
||||
if (f_kHz >= dphy_range_info[i].min_range_kHz &&
|
||||
f_kHz <= dphy_range_info[i].max_range_kHz)
|
||||
break;
|
||||
|
||||
if (i == ARRAY_SIZE(dphy_range_info)) {
|
||||
DRM_ERROR("%dkHz out of range\n", f_kHz);
|
||||
return 0;
|
||||
}
|
||||
|
||||
phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M;
|
||||
phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel;
|
||||
|
||||
if (phy->hstx_ckg_sel <= 7 &&
|
||||
phy->hstx_ckg_sel >= 4)
|
||||
q_pll = 0x10 >> (7 - phy->hstx_ckg_sel);
|
||||
|
||||
temp = f_kHz * (u64)q_pll * (u64)ref_clk_ps;
|
||||
m_n_int = temp / (u64)1000000000;
|
||||
m_n = (temp % (u64)1000000000) / (u64)100000000;
|
||||
|
||||
if (m_n_int % 2 == 0) {
|
||||
if (m_n * 6 >= 50) {
|
||||
n_pll = 2;
|
||||
m_pll = (m_n_int + 1) * n_pll;
|
||||
} else if (m_n * 6 >= 30) {
|
||||
n_pll = 3;
|
||||
m_pll = m_n_int * n_pll + 2;
|
||||
} else {
|
||||
n_pll = 1;
|
||||
m_pll = m_n_int * n_pll;
|
||||
}
|
||||
} else {
|
||||
if (m_n * 6 >= 50) {
|
||||
n_pll = 1;
|
||||
m_pll = (m_n_int + 1) * n_pll;
|
||||
} else if (m_n * 6 >= 30) {
|
||||
n_pll = 1;
|
||||
m_pll = (m_n_int + 1) * n_pll;
|
||||
} else if (m_n * 6 >= 10) {
|
||||
n_pll = 3;
|
||||
m_pll = m_n_int * n_pll + 1;
|
||||
} else {
|
||||
n_pll = 2;
|
||||
m_pll = m_n_int * n_pll;
|
||||
}
|
||||
}
|
||||
|
||||
if (n_pll == 1) {
|
||||
phy->pll_fbd_p = 0;
|
||||
phy->pll_pre_div1p = 1;
|
||||
} else {
|
||||
phy->pll_fbd_p = n_pll;
|
||||
phy->pll_pre_div1p = 0;
|
||||
}
|
||||
|
||||
if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4)
|
||||
r_pll = 0x10 >> (7 - phy->pll_fbd_2p);
|
||||
|
||||
if (m_pll == 2) {
|
||||
phy->pll_pre_p = 0;
|
||||
phy->pll_fbd_s = 0;
|
||||
phy->pll_fbd_div1f = 0;
|
||||
phy->pll_fbd_div5f = 1;
|
||||
} else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) {
|
||||
phy->pll_pre_p = m_pll / (2 * r_pll);
|
||||
phy->pll_fbd_s = 0;
|
||||
phy->pll_fbd_div1f = 1;
|
||||
phy->pll_fbd_div5f = 0;
|
||||
} else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) {
|
||||
if (((m_pll / (2 * r_pll)) % 2) == 0) {
|
||||
phy->pll_pre_p =
|
||||
(m_pll / (2 * r_pll)) / 2 - 1;
|
||||
phy->pll_fbd_s =
|
||||
(m_pll / (2 * r_pll)) % 2 + 2;
|
||||
} else {
|
||||
phy->pll_pre_p =
|
||||
(m_pll / (2 * r_pll)) / 2;
|
||||
phy->pll_fbd_s =
|
||||
(m_pll / (2 * r_pll)) % 2;
|
||||
}
|
||||
phy->pll_fbd_div1f = 0;
|
||||
phy->pll_fbd_div5f = 0;
|
||||
} else {
|
||||
phy->pll_pre_p = 0;
|
||||
phy->pll_fbd_s = 0;
|
||||
phy->pll_fbd_div1f = 0;
|
||||
phy->pll_fbd_div5f = 1;
|
||||
}
|
||||
|
||||
f_kHz = (u64)1000000000 * (u64)m_pll /
|
||||
((u64)ref_clk_ps * (u64)n_pll * (u64)q_pll);
|
||||
|
||||
if (f_kHz >= req_kHz)
|
||||
break;
|
||||
|
||||
tmp_kHz += 10;
|
||||
|
||||
} while (true);
|
||||
|
||||
return f_kHz;
|
||||
}
|
||||
|
||||
static void dsi_get_phy_params(u32 phy_req_kHz,
|
||||
struct mipi_phy_params *phy)
|
||||
{
|
||||
u32 ref_clk_ps = PHY_REF_CLK_PERIOD_PS;
|
||||
u32 phy_rate_kHz;
|
||||
u32 ui;
|
||||
|
||||
memset(phy, 0, sizeof(*phy));
|
||||
|
||||
phy_rate_kHz = dsi_calc_phy_rate(phy_req_kHz, phy);
|
||||
if (!phy_rate_kHz)
|
||||
return;
|
||||
|
||||
ui = 1000000 / phy_rate_kHz;
|
||||
|
||||
phy->clk_t_lpx = ROUND(50, 8 * ui);
|
||||
phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1;
|
||||
|
||||
phy->clk_t_hs_zero = ROUND(262, 8 * ui);
|
||||
phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1);
|
||||
phy->clk_t_wakeup = ROUND(1000000, (ref_clk_ps / 1000) - 1);
|
||||
if (phy->clk_t_wakeup > 0xff)
|
||||
phy->clk_t_wakeup = 0xff;
|
||||
phy->data_t_wakeup = phy->clk_t_wakeup;
|
||||
phy->data_t_lpx = phy->clk_t_lpx;
|
||||
phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1;
|
||||
phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui);
|
||||
phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1);
|
||||
phy->data_t_ta_go = 3;
|
||||
phy->data_t_ta_get = 4;
|
||||
|
||||
phy->pll_enbwt = 1;
|
||||
phy->clklp2hs_time = ROUND(407, 8 * ui) + 12;
|
||||
phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui);
|
||||
phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1;
|
||||
phy->hs2lp_time = phy->clkhs2lp_time;
|
||||
phy->clk_to_data_delay = 1 + phy->clklp2hs_time;
|
||||
phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) +
|
||||
phy->clkhs2lp_time;
|
||||
|
||||
phy->lane_byte_clk_kHz = phy_rate_kHz / 8;
|
||||
phy->clk_division =
|
||||
DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK);
|
||||
}
|
||||
|
||||
static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* TODO: only support RGB888 now, to support more
|
||||
*/
|
||||
switch (format) {
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
val = DSI_24BITS_1;
|
||||
break;
|
||||
default:
|
||||
val = DSI_24BITS_1;
|
||||
break;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
* dsi phy reg write function
|
||||
*/
|
||||
static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
|
||||
{
|
||||
u32 reg_write = 0x10000 + reg;
|
||||
|
||||
/*
|
||||
* latch reg first
|
||||
*/
|
||||
writel(reg_write, base + PHY_TST_CTRL1);
|
||||
writel(0x02, base + PHY_TST_CTRL0);
|
||||
writel(0x00, base + PHY_TST_CTRL0);
|
||||
|
||||
/*
|
||||
* then latch value
|
||||
*/
|
||||
writel(val, base + PHY_TST_CTRL1);
|
||||
writel(0x02, base + PHY_TST_CTRL0);
|
||||
writel(0x00, base + PHY_TST_CTRL0);
|
||||
}
|
||||
|
||||
static void dsi_set_phy_timer(void __iomem *base,
|
||||
struct mipi_phy_params *phy,
|
||||
u32 lanes)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
/*
|
||||
* Set lane value and phy stop wait time.
|
||||
*/
|
||||
val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8);
|
||||
writel(val, base + PHY_IF_CFG);
|
||||
|
||||
/*
|
||||
* Set phy clk division.
|
||||
*/
|
||||
val = readl(base + CLKMGR_CFG) | phy->clk_division;
|
||||
writel(val, base + CLKMGR_CFG);
|
||||
|
||||
/*
|
||||
* Set lp and hs switching params.
|
||||
*/
|
||||
dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time);
|
||||
dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time);
|
||||
dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10),
|
||||
phy->clkhs2lp_time);
|
||||
dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10),
|
||||
phy->clklp2hs_time);
|
||||
dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8),
|
||||
phy->data_to_clk_delay);
|
||||
dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8),
|
||||
phy->clk_to_data_delay);
|
||||
}
|
||||
|
||||
static void dsi_set_mipi_phy(void __iomem *base,
|
||||
struct mipi_phy_params *phy,
|
||||
u32 lanes)
|
||||
{
|
||||
u32 delay_count;
|
||||
u32 val;
|
||||
u32 i;
|
||||
|
||||
/* phy timer setting */
|
||||
dsi_set_phy_timer(base, phy, lanes);
|
||||
|
||||
/*
|
||||
* Reset to clean up phy tst params.
|
||||
*/
|
||||
writel(0, base + PHY_RSTZ);
|
||||
writel(0, base + PHY_TST_CTRL0);
|
||||
writel(1, base + PHY_TST_CTRL0);
|
||||
writel(0, base + PHY_TST_CTRL0);
|
||||
|
||||
/*
|
||||
* Clock lane timing control setting: TLPX, THS-PREPARE,
|
||||
* THS-ZERO, THS-TRAIL, TWAKEUP.
|
||||
*/
|
||||
dsi_phy_tst_set(base, CLK_TLPX, phy->clk_t_lpx);
|
||||
dsi_phy_tst_set(base, CLK_THS_PREPARE, phy->clk_t_hs_prepare);
|
||||
dsi_phy_tst_set(base, CLK_THS_ZERO, phy->clk_t_hs_zero);
|
||||
dsi_phy_tst_set(base, CLK_THS_TRAIL, phy->clk_t_hs_trial);
|
||||
dsi_phy_tst_set(base, CLK_TWAKEUP, phy->clk_t_wakeup);
|
||||
|
||||
/*
|
||||
* Data lane timing control setting: TLPX, THS-PREPARE,
|
||||
* THS-ZERO, THS-TRAIL, TTA-GO, TTA-GET, TWAKEUP.
|
||||
*/
|
||||
for (i = 0; i < lanes; i++) {
|
||||
dsi_phy_tst_set(base, DATA_TLPX(i), phy->data_t_lpx);
|
||||
dsi_phy_tst_set(base, DATA_THS_PREPARE(i),
|
||||
phy->data_t_hs_prepare);
|
||||
dsi_phy_tst_set(base, DATA_THS_ZERO(i), phy->data_t_hs_zero);
|
||||
dsi_phy_tst_set(base, DATA_THS_TRAIL(i), phy->data_t_hs_trial);
|
||||
dsi_phy_tst_set(base, DATA_TTA_GO(i), phy->data_t_ta_go);
|
||||
dsi_phy_tst_set(base, DATA_TTA_GET(i), phy->data_t_ta_get);
|
||||
dsi_phy_tst_set(base, DATA_TWAKEUP(i), phy->data_t_wakeup);
|
||||
}
|
||||
|
||||
/*
|
||||
* physical configuration: I, pll I, pll II, pll III,
|
||||
* pll IV, pll V.
|
||||
*/
|
||||
dsi_phy_tst_set(base, PHY_CFG_I, phy->hstx_ckg_sel);
|
||||
val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) +
|
||||
(phy->pll_fbd_2p << 1) + phy->pll_enbwt;
|
||||
dsi_phy_tst_set(base, PHY_CFG_PLL_I, val);
|
||||
dsi_phy_tst_set(base, PHY_CFG_PLL_II, phy->pll_fbd_p);
|
||||
dsi_phy_tst_set(base, PHY_CFG_PLL_III, phy->pll_fbd_s);
|
||||
val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p;
|
||||
dsi_phy_tst_set(base, PHY_CFG_PLL_IV, val);
|
||||
val = (5 << 5) + (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) +
|
||||
phy->pll_lpf_cs;
|
||||
dsi_phy_tst_set(base, PHY_CFG_PLL_V, val);
|
||||
|
||||
writel(PHY_ENABLECLK, base + PHY_RSTZ);
|
||||
udelay(1);
|
||||
writel(PHY_ENABLECLK | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
|
||||
udelay(1);
|
||||
writel(PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ, base + PHY_RSTZ);
|
||||
usleep_range(1000, 1500);
|
||||
|
||||
/*
|
||||
* wait for phy's clock ready
|
||||
*/
|
||||
delay_count = 100;
|
||||
while (delay_count--) {
|
||||
val = readl(base + PHY_STATUS);
|
||||
if ((BIT(0) | BIT(2)) & val)
|
||||
break;
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
if (!delay_count)
|
||||
DRM_INFO("phylock and phystopstateclklane is not ready.\n");
|
||||
}
|
||||
|
||||
static void dsi_set_mode_timing(void __iomem *base,
|
||||
u32 lane_byte_clk_kHz,
|
||||
struct drm_display_mode *mode,
|
||||
enum mipi_dsi_pixel_format format)
|
||||
{
|
||||
u32 hfp, hbp, hsw, vfp, vbp, vsw;
|
||||
u32 hline_time;
|
||||
u32 hsa_time;
|
||||
u32 hbp_time;
|
||||
u32 pixel_clk_kHz;
|
||||
int htot, vtot;
|
||||
u32 val;
|
||||
u64 tmp;
|
||||
|
||||
val = dsi_get_dpi_color_coding(format);
|
||||
writel(val, base + DPI_COLOR_CODING);
|
||||
|
||||
val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2;
|
||||
val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1;
|
||||
writel(val, base + DPI_CFG_POL);
|
||||
|
||||
/*
|
||||
* The DSI IP accepts vertical timing using lines as normal,
|
||||
* but horizontal timing is a mixture of pixel-clocks for the
|
||||
* active region and byte-lane clocks for the blanking-related
|
||||
* timings. hfp is specified as the total hline_time in byte-
|
||||
* lane clocks minus hsa, hbp and active.
|
||||
*/
|
||||
pixel_clk_kHz = mode->clock;
|
||||
htot = mode->htotal;
|
||||
vtot = mode->vtotal;
|
||||
hfp = mode->hsync_start - mode->hdisplay;
|
||||
hbp = mode->htotal - mode->hsync_end;
|
||||
hsw = mode->hsync_end - mode->hsync_start;
|
||||
vfp = mode->vsync_start - mode->vdisplay;
|
||||
vbp = mode->vtotal - mode->vsync_end;
|
||||
vsw = mode->vsync_end - mode->vsync_start;
|
||||
if (vsw > 15) {
|
||||
DRM_DEBUG_DRIVER("vsw exceeded 15\n");
|
||||
vsw = 15;
|
||||
}
|
||||
|
||||
hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz;
|
||||
hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz;
|
||||
tmp = (u64)htot * (u64)lane_byte_clk_kHz;
|
||||
hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
|
||||
|
||||
/* all specified in byte-lane clocks */
|
||||
writel(hsa_time, base + VID_HSA_TIME);
|
||||
writel(hbp_time, base + VID_HBP_TIME);
|
||||
writel(hline_time, base + VID_HLINE_TIME);
|
||||
|
||||
writel(vsw, base + VID_VSA_LINES);
|
||||
writel(vbp, base + VID_VBP_LINES);
|
||||
writel(vfp, base + VID_VFP_LINES);
|
||||
writel(mode->vdisplay, base + VID_VACTIVE_LINES);
|
||||
writel(mode->hdisplay, base + VID_PKT_SIZE);
|
||||
|
||||
DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n",
|
||||
htot, hfp, hbp, hsw);
|
||||
DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n",
|
||||
vtot, vfp, vbp, vsw);
|
||||
DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n",
|
||||
hsa_time, hbp_time, hline_time);
|
||||
}
|
||||
|
||||
static void dsi_set_video_mode(void __iomem *base, unsigned long flags)
|
||||
{
|
||||
u32 val;
|
||||
u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
|
||||
MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
|
||||
u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO |
|
||||
MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
|
||||
u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
|
||||
|
||||
/*
|
||||
* choose video mode type
|
||||
*/
|
||||
if ((flags & mode_mask) == non_burst_sync_pulse)
|
||||
val = DSI_NON_BURST_SYNC_PULSES;
|
||||
else if ((flags & mode_mask) == non_burst_sync_event)
|
||||
val = DSI_NON_BURST_SYNC_EVENTS;
|
||||
else
|
||||
val = DSI_BURST_SYNC_PULSES_1;
|
||||
writel(val, base + VID_MODE_CFG);
|
||||
|
||||
writel(PHY_TXREQUESTCLKHS, base + LPCLK_CTRL);
|
||||
writel(DSI_VIDEO_MODE, base + MODE_CFG);
|
||||
}
|
||||
|
||||
static void dsi_mipi_init(struct dw_dsi *dsi)
|
||||
{
|
||||
struct dsi_hw_ctx *ctx = dsi->ctx;
|
||||
struct mipi_phy_params *phy = &dsi->phy;
|
||||
struct drm_display_mode *mode = &dsi->cur_mode;
|
||||
u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||
void __iomem *base = ctx->base;
|
||||
u32 dphy_req_kHz;
|
||||
|
||||
/*
|
||||
* count phy params
|
||||
*/
|
||||
dphy_req_kHz = mode->clock * bpp / dsi->lanes;
|
||||
dsi_get_phy_params(dphy_req_kHz, phy);
|
||||
|
||||
/* reset Core */
|
||||
writel(RESET, base + PWR_UP);
|
||||
|
||||
/* set dsi phy params */
|
||||
dsi_set_mipi_phy(base, phy, dsi->lanes);
|
||||
|
||||
/* set dsi mode timing */
|
||||
dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format);
|
||||
|
||||
/* set dsi video mode */
|
||||
dsi_set_video_mode(base, dsi->mode_flags);
|
||||
|
||||
/* dsi wake up */
|
||||
writel(POWERUP, base + PWR_UP);
|
||||
|
||||
DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n",
|
||||
dsi->lanes, mode->clock, phy->lane_byte_clk_kHz);
|
||||
}
|
||||
|
||||
static void dsi_encoder_disable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct dw_dsi *dsi = encoder_to_dsi(encoder);
|
||||
struct dsi_hw_ctx *ctx = dsi->ctx;
|
||||
void __iomem *base = ctx->base;
|
||||
|
||||
if (!dsi->enable)
|
||||
return;
|
||||
|
||||
writel(0, base + PWR_UP);
|
||||
writel(0, base + LPCLK_CTRL);
|
||||
writel(0, base + PHY_RSTZ);
|
||||
clk_disable_unprepare(ctx->pclk);
|
||||
|
||||
dsi->enable = false;
|
||||
}
|
||||
|
||||
static void dsi_encoder_enable(struct drm_encoder *encoder)
|
||||
{
|
||||
struct dw_dsi *dsi = encoder_to_dsi(encoder);
|
||||
struct dsi_hw_ctx *ctx = dsi->ctx;
|
||||
int ret;
|
||||
|
||||
if (dsi->enable)
|
||||
return;
|
||||
|
||||
ret = clk_prepare_enable(ctx->pclk);
|
||||
if (ret) {
|
||||
DRM_ERROR("fail to enable pclk: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
dsi_mipi_init(dsi);
|
||||
|
||||
dsi->enable = true;
|
||||
}
|
||||
|
||||
static void dsi_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adj_mode)
|
||||
{
|
||||
struct dw_dsi *dsi = encoder_to_dsi(encoder);
|
||||
|
||||
drm_mode_copy(&dsi->cur_mode, adj_mode);
|
||||
}
|
||||
|
||||
static int dsi_encoder_atomic_check(struct drm_encoder *encoder,
|
||||
struct drm_crtc_state *crtc_state,
|
||||
struct drm_connector_state *conn_state)
|
||||
{
|
||||
/* do nothing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = {
|
||||
.atomic_check = dsi_encoder_atomic_check,
|
||||
.mode_set = dsi_encoder_mode_set,
|
||||
.enable = dsi_encoder_enable,
|
||||
.disable = dsi_encoder_disable
|
||||
};
|
||||
|
||||
static const struct drm_encoder_funcs dw_encoder_funcs = {
|
||||
.destroy = drm_encoder_cleanup,
|
||||
};
|
||||
|
||||
static int dw_drm_encoder_init(struct device *dev,
|
||||
struct drm_device *drm_dev,
|
||||
struct drm_encoder *encoder)
|
||||
{
|
||||
int ret;
|
||||
u32 crtc_mask = drm_of_find_possible_crtcs(drm_dev, dev->of_node);
|
||||
|
||||
if (!crtc_mask) {
|
||||
DRM_ERROR("failed to find crtc mask\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
encoder->possible_crtcs = crtc_mask;
|
||||
ret = drm_encoder_init(drm_dev, encoder, &dw_encoder_funcs,
|
||||
DRM_MODE_ENCODER_DSI, NULL);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to init dsi encoder\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
drm_encoder_helper_add(encoder, &dw_encoder_helper_funcs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_host_attach(struct mipi_dsi_host *host,
|
||||
struct mipi_dsi_device *mdsi)
|
||||
{
|
||||
struct dw_dsi *dsi = host_to_dsi(host);
|
||||
|
||||
if (mdsi->lanes < 1 || mdsi->lanes > 4) {
|
||||
DRM_ERROR("dsi device params invalid\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dsi->lanes = mdsi->lanes;
|
||||
dsi->format = mdsi->format;
|
||||
dsi->mode_flags = mdsi->mode_flags;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_host_detach(struct mipi_dsi_host *host,
|
||||
struct mipi_dsi_device *mdsi)
|
||||
{
|
||||
/* do nothing */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mipi_dsi_host_ops dsi_host_ops = {
|
||||
.attach = dsi_host_attach,
|
||||
.detach = dsi_host_detach,
|
||||
};
|
||||
|
||||
static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
|
||||
{
|
||||
struct mipi_dsi_host *host = &dsi->host;
|
||||
int ret;
|
||||
|
||||
host->dev = dev;
|
||||
host->ops = &dsi_host_ops;
|
||||
ret = mipi_dsi_host_register(host);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to register dsi host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi)
|
||||
{
|
||||
struct drm_encoder *encoder = &dsi->encoder;
|
||||
struct drm_bridge *bridge = dsi->bridge;
|
||||
int ret;
|
||||
|
||||
/* associate the bridge to dsi encoder */
|
||||
encoder->bridge = bridge;
|
||||
bridge->encoder = encoder;
|
||||
|
||||
ret = drm_bridge_attach(dev, bridge);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to attach external bridge\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_bind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
struct dsi_data *ddata = dev_get_drvdata(dev);
|
||||
struct dw_dsi *dsi = &ddata->dsi;
|
||||
struct drm_device *drm_dev = data;
|
||||
int ret;
|
||||
|
||||
ret = dw_drm_encoder_init(dev, drm_dev, &dsi->encoder);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = dsi_host_init(dev, dsi);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = dsi_bridge_init(drm_dev, dsi);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dsi_unbind(struct device *dev, struct device *master, void *data)
|
||||
{
|
||||
/* do nothing */
|
||||
}
|
||||
|
||||
static const struct component_ops dsi_ops = {
|
||||
.bind = dsi_bind,
|
||||
.unbind = dsi_unbind,
|
||||
};
|
||||
|
||||
static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
|
||||
{
|
||||
struct dsi_hw_ctx *ctx = dsi->ctx;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device_node *endpoint, *bridge_node;
|
||||
struct drm_bridge *bridge;
|
||||
struct resource *res;
|
||||
|
||||
/*
|
||||
* Get the endpoint node. In our case, dsi has one output port1
|
||||
* to which the external HDMI bridge is connected.
|
||||
*/
|
||||
endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
|
||||
if (!endpoint) {
|
||||
DRM_ERROR("no valid endpoint node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
of_node_put(endpoint);
|
||||
|
||||
bridge_node = of_graph_get_remote_port_parent(endpoint);
|
||||
if (!bridge_node) {
|
||||
DRM_ERROR("no valid bridge node\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
of_node_put(bridge_node);
|
||||
|
||||
bridge = of_drm_find_bridge(bridge_node);
|
||||
if (!bridge) {
|
||||
DRM_INFO("wait for external HDMI bridge driver.\n");
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
dsi->bridge = bridge;
|
||||
|
||||
ctx->pclk = devm_clk_get(&pdev->dev, "pclk");
|
||||
if (IS_ERR(ctx->pclk)) {
|
||||
DRM_ERROR("failed to get pclk clock\n");
|
||||
return PTR_ERR(ctx->pclk);
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
ctx->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(ctx->base)) {
|
||||
DRM_ERROR("failed to remap dsi io region\n");
|
||||
return PTR_ERR(ctx->base);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dsi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct dsi_data *data;
|
||||
struct dw_dsi *dsi;
|
||||
struct dsi_hw_ctx *ctx;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data) {
|
||||
DRM_ERROR("failed to allocate dsi data.\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
dsi = &data->dsi;
|
||||
ctx = &data->ctx;
|
||||
dsi->ctx = ctx;
|
||||
|
||||
ret = dsi_parse_dt(pdev, dsi);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return component_add(&pdev->dev, &dsi_ops);
|
||||
}
|
||||
|
||||
static int dsi_remove(struct platform_device *pdev)
|
||||
{
|
||||
component_del(&pdev->dev, &dsi_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id dsi_of_match[] = {
|
||||
{.compatible = "hisilicon,hi6220-dsi"},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dsi_of_match);
|
||||
|
||||
static struct platform_driver dsi_driver = {
|
||||
.probe = dsi_probe,
|
||||
.remove = dsi_remove,
|
||||
.driver = {
|
||||
.name = "dw-dsi",
|
||||
.of_match_table = dsi_of_match,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(dsi_driver);
|
||||
|
||||
MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
|
||||
MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
|
||||
MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
|
||||
MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
103
drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
Normal file
103
drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h
Normal file
@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (c) 2016 Linaro Limited.
|
||||
* Copyright (c) 2014-2016 Hisilicon Limited.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DW_DSI_REG_H__
|
||||
#define __DW_DSI_REG_H__
|
||||
|
||||
#define MASK(x) (BIT(x) - 1)
|
||||
|
||||
/*
|
||||
* regs
|
||||
*/
|
||||
#define PWR_UP 0x04 /* Core power-up */
|
||||
#define RESET 0
|
||||
#define POWERUP BIT(0)
|
||||
#define PHY_IF_CFG 0xA4 /* D-PHY interface configuration */
|
||||
#define CLKMGR_CFG 0x08 /* the internal clock dividers */
|
||||
#define PHY_RSTZ 0xA0 /* D-PHY reset control */
|
||||
#define PHY_ENABLECLK BIT(2)
|
||||
#define PHY_UNRSTZ BIT(1)
|
||||
#define PHY_UNSHUTDOWNZ BIT(0)
|
||||
#define PHY_TST_CTRL0 0xB4 /* D-PHY test interface control 0 */
|
||||
#define PHY_TST_CTRL1 0xB8 /* D-PHY test interface control 1 */
|
||||
#define CLK_TLPX 0x10
|
||||
#define CLK_THS_PREPARE 0x11
|
||||
#define CLK_THS_ZERO 0x12
|
||||
#define CLK_THS_TRAIL 0x13
|
||||
#define CLK_TWAKEUP 0x14
|
||||
#define DATA_TLPX(x) (0x20 + ((x) << 4))
|
||||
#define DATA_THS_PREPARE(x) (0x21 + ((x) << 4))
|
||||
#define DATA_THS_ZERO(x) (0x22 + ((x) << 4))
|
||||
#define DATA_THS_TRAIL(x) (0x23 + ((x) << 4))
|
||||
#define DATA_TTA_GO(x) (0x24 + ((x) << 4))
|
||||
#define DATA_TTA_GET(x) (0x25 + ((x) << 4))
|
||||
#define DATA_TWAKEUP(x) (0x26 + ((x) << 4))
|
||||
#define PHY_CFG_I 0x60
|
||||
#define PHY_CFG_PLL_I 0x63
|
||||
#define PHY_CFG_PLL_II 0x64
|
||||
#define PHY_CFG_PLL_III 0x65
|
||||
#define PHY_CFG_PLL_IV 0x66
|
||||
#define PHY_CFG_PLL_V 0x67
|
||||
#define DPI_COLOR_CODING 0x10 /* DPI color coding */
|
||||
#define DPI_CFG_POL 0x14 /* DPI polarity configuration */
|
||||
#define VID_HSA_TIME 0x48 /* Horizontal Sync Active time */
|
||||
#define VID_HBP_TIME 0x4C /* Horizontal Back Porch time */
|
||||
#define VID_HLINE_TIME 0x50 /* Line time */
|
||||
#define VID_VSA_LINES 0x54 /* Vertical Sync Active period */
|
||||
#define VID_VBP_LINES 0x58 /* Vertical Back Porch period */
|
||||
#define VID_VFP_LINES 0x5C /* Vertical Front Porch period */
|
||||
#define VID_VACTIVE_LINES 0x60 /* Vertical resolution */
|
||||
#define VID_PKT_SIZE 0x3C /* Video packet size */
|
||||
#define VID_MODE_CFG 0x38 /* Video mode configuration */
|
||||
#define PHY_TMR_CFG 0x9C /* Data lanes timing configuration */
|
||||
#define BTA_TO_CNT 0x8C /* Response timeout definition */
|
||||
#define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */
|
||||
#define CLK_DATA_TMR_CFG 0xCC
|
||||
#define LPCLK_CTRL 0x94 /* Low-power in clock lane */
|
||||
#define PHY_TXREQUESTCLKHS BIT(0)
|
||||
#define MODE_CFG 0x34 /* Video or Command mode selection */
|
||||
#define PHY_STATUS 0xB0 /* D-PHY PPI status interface */
|
||||
|
||||
#define PHY_STOP_WAIT_TIME 0x30
|
||||
|
||||
/*
|
||||
* regs relevant enum
|
||||
*/
|
||||
enum dpi_color_coding {
|
||||
DSI_24BITS_1 = 5,
|
||||
};
|
||||
|
||||
enum dsi_video_mode_type {
|
||||
DSI_NON_BURST_SYNC_PULSES = 0,
|
||||
DSI_NON_BURST_SYNC_EVENTS,
|
||||
DSI_BURST_SYNC_PULSES_1,
|
||||
DSI_BURST_SYNC_PULSES_2
|
||||
};
|
||||
|
||||
enum dsi_work_mode {
|
||||
DSI_VIDEO_MODE = 0,
|
||||
DSI_COMMAND_MODE
|
||||
};
|
||||
|
||||
/*
|
||||
* Register Write/Read Helper functions
|
||||
*/
|
||||
static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
|
||||
u32 mask, u32 val)
|
||||
{
|
||||
u32 tmp, orig;
|
||||
|
||||
orig = readl(addr);
|
||||
tmp = orig & ~(mask << bit_start);
|
||||
tmp |= (val & mask) << bit_start;
|
||||
writel(tmp, addr);
|
||||
}
|
||||
|
||||
#endif /* __DW_DRM_DSI_H__ */
|
||||
230
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
Normal file
230
drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h
Normal file
@ -0,0 +1,230 @@
|
||||
/*
|
||||
* Copyright (c) 2016 Linaro Limited.
|
||||
* Copyright (c) 2014-2016 Hisilicon Limited.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __KIRIN_ADE_REG_H__
|
||||
#define __KIRIN_ADE_REG_H__
|
||||
|
||||
/*
|
||||
* ADE Registers
|
||||
*/
|
||||
#define MASK(x) (BIT(x) - 1)
|
||||
|
||||
#define ADE_CTRL 0x0004
|
||||
#define FRM_END_START_OFST 0
|
||||
#define FRM_END_START_MASK MASK(2)
|
||||
#define AUTO_CLK_GATE_EN_OFST 0
|
||||
#define AUTO_CLK_GATE_EN BIT(0)
|
||||
#define ADE_DISP_SRC_CFG 0x0018
|
||||
#define ADE_CTRL1 0x008C
|
||||
#define ADE_EN 0x0100
|
||||
#define ADE_DISABLE 0
|
||||
#define ADE_ENABLE 1
|
||||
/* reset and reload regs */
|
||||
#define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
|
||||
#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
|
||||
#define RDMA_OFST 0
|
||||
#define CLIP_OFST 15
|
||||
#define SCL_OFST 21
|
||||
#define CTRAN_OFST 24
|
||||
#define OVLY_OFST 37 /* 32+5 */
|
||||
/* channel regs */
|
||||
#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80)
|
||||
#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80)
|
||||
#define RD_CH_SIZE(x) (0x100C + (x) * 0x80)
|
||||
#define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80)
|
||||
#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80)
|
||||
#define RD_CH_EN(x) (0x1020 + (x) * 0x80)
|
||||
/* overlay regs */
|
||||
#define ADE_OVLY1_TRANS_CFG 0x002C
|
||||
#define ADE_OVLY_CTL 0x0098
|
||||
#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4)
|
||||
#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4)
|
||||
#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4)
|
||||
#define ADE_OVLY_OUTPUT_SIZE(x) (0x2070 + (x) * 8)
|
||||
#define OUTPUT_XSIZE_OFST 16
|
||||
#define ADE_OVLYX_CTL(x) (0x209C + (x) * 4)
|
||||
#define CH_OVLY_SEL_OFST(x) ((x) * 4)
|
||||
#define CH_OVLY_SEL_MASK MASK(2)
|
||||
#define CH_OVLY_SEL_VAL(x) ((x) + 1)
|
||||
#define CH_ALP_MODE_OFST 0
|
||||
#define CH_ALP_SEL_OFST 2
|
||||
#define CH_UNDER_ALP_SEL_OFST 4
|
||||
#define CH_EN_OFST 6
|
||||
#define CH_ALP_GBL_OFST 15
|
||||
#define CH_SEL_OFST 28
|
||||
/* ctran regs */
|
||||
#define ADE_CTRAN_DIS(x) (0x5004 + (x) * 0x100)
|
||||
#define CTRAN_BYPASS_ON 1
|
||||
#define CTRAN_BYPASS_OFF 0
|
||||
#define ADE_CTRAN_IMAGE_SIZE(x) (0x503C + (x) * 0x100)
|
||||
/* clip regs */
|
||||
#define ADE_CLIP_DISABLE(x) (0x6800 + (x) * 0x100)
|
||||
#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100)
|
||||
#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100)
|
||||
|
||||
/*
|
||||
* LDI Registers
|
||||
*/
|
||||
#define LDI_HRZ_CTRL0 0x7400
|
||||
#define HBP_OFST 20
|
||||
#define LDI_HRZ_CTRL1 0x7404
|
||||
#define LDI_VRT_CTRL0 0x7408
|
||||
#define VBP_OFST 20
|
||||
#define LDI_VRT_CTRL1 0x740C
|
||||
#define LDI_PLR_CTRL 0x7410
|
||||
#define FLAG_NVSYNC BIT(0)
|
||||
#define FLAG_NHSYNC BIT(1)
|
||||
#define FLAG_NPIXCLK BIT(2)
|
||||
#define FLAG_NDE BIT(3)
|
||||
#define LDI_DSP_SIZE 0x7414
|
||||
#define VSIZE_OFST 20
|
||||
#define LDI_INT_EN 0x741C
|
||||
#define FRAME_END_INT_EN_OFST 1
|
||||
#define LDI_CTRL 0x7420
|
||||
#define BPP_OFST 3
|
||||
#define DATA_GATE_EN BIT(2)
|
||||
#define LDI_EN BIT(0)
|
||||
#define LDI_MSK_INT 0x7428
|
||||
#define LDI_INT_CLR 0x742C
|
||||
#define LDI_WORK_MODE 0x7430
|
||||
#define LDI_HDMI_DSI_GT 0x7434
|
||||
|
||||
/*
|
||||
* ADE media bus service regs
|
||||
*/
|
||||
#define ADE0_QOSGENERATOR_MODE 0x010C
|
||||
#define QOSGENERATOR_MODE_MASK MASK(2)
|
||||
#define ADE0_QOSGENERATOR_EXTCONTROL 0x0118
|
||||
#define SOCKET_QOS_EN BIT(0)
|
||||
#define ADE1_QOSGENERATOR_MODE 0x020C
|
||||
#define ADE1_QOSGENERATOR_EXTCONTROL 0x0218
|
||||
|
||||
/*
|
||||
* ADE regs relevant enums
|
||||
*/
|
||||
enum frame_end_start {
|
||||
/* regs take effect in every vsync */
|
||||
REG_EFFECTIVE_IN_VSYNC = 0,
|
||||
/* regs take effect in fist ade en and every frame end */
|
||||
REG_EFFECTIVE_IN_ADEEN_FRMEND,
|
||||
/* regs take effect in ade en immediately */
|
||||
REG_EFFECTIVE_IN_ADEEN,
|
||||
/* regs take effect in first vsync and every frame end */
|
||||
REG_EFFECTIVE_IN_VSYNC_FRMEND
|
||||
};
|
||||
|
||||
enum ade_fb_format {
|
||||
ADE_RGB_565 = 0,
|
||||
ADE_BGR_565,
|
||||
ADE_XRGB_8888,
|
||||
ADE_XBGR_8888,
|
||||
ADE_ARGB_8888,
|
||||
ADE_ABGR_8888,
|
||||
ADE_RGBA_8888,
|
||||
ADE_BGRA_8888,
|
||||
ADE_RGB_888,
|
||||
ADE_BGR_888 = 9,
|
||||
ADE_FORMAT_UNSUPPORT = 800
|
||||
};
|
||||
|
||||
enum ade_channel {
|
||||
ADE_CH1 = 0, /* channel 1 for primary plane */
|
||||
ADE_CH_NUM
|
||||
};
|
||||
|
||||
enum ade_scale {
|
||||
ADE_SCL1 = 0,
|
||||
ADE_SCL2,
|
||||
ADE_SCL3,
|
||||
ADE_SCL_NUM
|
||||
};
|
||||
|
||||
enum ade_ctran {
|
||||
ADE_CTRAN1 = 0,
|
||||
ADE_CTRAN2,
|
||||
ADE_CTRAN3,
|
||||
ADE_CTRAN4,
|
||||
ADE_CTRAN5,
|
||||
ADE_CTRAN6,
|
||||
ADE_CTRAN_NUM
|
||||
};
|
||||
|
||||
enum ade_overlay {
|
||||
ADE_OVLY1 = 0,
|
||||
ADE_OVLY2,
|
||||
ADE_OVLY3,
|
||||
ADE_OVLY_NUM
|
||||
};
|
||||
|
||||
enum ade_alpha_mode {
|
||||
ADE_ALP_GLOBAL = 0,
|
||||
ADE_ALP_PIXEL,
|
||||
ADE_ALP_PIXEL_AND_GLB
|
||||
};
|
||||
|
||||
enum ade_alpha_blending_mode {
|
||||
ADE_ALP_MUL_COEFF_0 = 0, /* alpha */
|
||||
ADE_ALP_MUL_COEFF_1, /* 1-alpha */
|
||||
ADE_ALP_MUL_COEFF_2, /* 0 */
|
||||
ADE_ALP_MUL_COEFF_3 /* 1 */
|
||||
};
|
||||
|
||||
/*
|
||||
* LDI regs relevant enums
|
||||
*/
|
||||
enum dsi_pclk_en {
|
||||
DSI_PCLK_ON = 0,
|
||||
DSI_PCLK_OFF
|
||||
};
|
||||
|
||||
enum ldi_output_format {
|
||||
LDI_OUT_RGB_565 = 0,
|
||||
LDI_OUT_RGB_666,
|
||||
LDI_OUT_RGB_888
|
||||
};
|
||||
|
||||
enum ldi_work_mode {
|
||||
TEST_MODE = 0,
|
||||
NORMAL_MODE
|
||||
};
|
||||
|
||||
enum ldi_input_source {
|
||||
DISP_SRC_NONE = 0,
|
||||
DISP_SRC_OVLY2,
|
||||
DISP_SRC_DISP,
|
||||
DISP_SRC_ROT,
|
||||
DISP_SRC_SCL2
|
||||
};
|
||||
|
||||
/*
|
||||
* ADE media bus service relevant enums
|
||||
*/
|
||||
enum qos_generator_mode {
|
||||
FIXED_MODE = 0,
|
||||
LIMITER_MODE,
|
||||
BYPASS_MODE,
|
||||
REGULATOR_MODE
|
||||
};
|
||||
|
||||
/*
|
||||
* Register Write/Read Helper functions
|
||||
*/
|
||||
static inline void ade_update_bits(void __iomem *addr, u32 bit_start,
|
||||
u32 mask, u32 val)
|
||||
{
|
||||
u32 tmp, orig;
|
||||
|
||||
orig = readl(addr);
|
||||
tmp = orig & ~(mask << bit_start);
|
||||
tmp |= (val & mask) << bit_start;
|
||||
writel(tmp, addr);
|
||||
}
|
||||
|
||||
#endif
|
||||
1057
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
Normal file
1057
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
Normal file
File diff suppressed because it is too large
Load Diff
367
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
Normal file
367
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c
Normal file
@ -0,0 +1,367 @@
|
||||
/*
|
||||
* Hisilicon Kirin SoCs drm master driver
|
||||
*
|
||||
* Copyright (c) 2016 Linaro Limited.
|
||||
* Copyright (c) 2014-2016 Hisilicon Limited.
|
||||
*
|
||||
* Author:
|
||||
* Xinliang Liu <z.liuxinliang@hisilicon.com>
|
||||
* Xinliang Liu <xinliang.liu@linaro.org>
|
||||
* Xinwei Kong <kong.kongxinwei@hisilicon.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/component.h>
|
||||
#include <linux/of_graph.h>
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_gem_cma_helper.h>
|
||||
#include <drm/drm_fb_cma_helper.h>
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
|
||||
#include "kirin_drm_drv.h"
|
||||
|
||||
static struct kirin_dc_ops *dc_ops;
|
||||
|
||||
static int kirin_drm_kms_cleanup(struct drm_device *dev)
|
||||
{
|
||||
struct kirin_drm_private *priv = dev->dev_private;
|
||||
|
||||
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
||||
if (priv->fbdev) {
|
||||
drm_fbdev_cma_fini(priv->fbdev);
|
||||
priv->fbdev = NULL;
|
||||
}
|
||||
#endif
|
||||
drm_kms_helper_poll_fini(dev);
|
||||
drm_vblank_cleanup(dev);
|
||||
dc_ops->cleanup(dev);
|
||||
drm_mode_config_cleanup(dev);
|
||||
devm_kfree(dev->dev, priv);
|
||||
dev->dev_private = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
||||
static void kirin_fbdev_output_poll_changed(struct drm_device *dev)
|
||||
{
|
||||
struct kirin_drm_private *priv = dev->dev_private;
|
||||
|
||||
if (priv->fbdev) {
|
||||
drm_fbdev_cma_hotplug_event(priv->fbdev);
|
||||
} else {
|
||||
priv->fbdev = drm_fbdev_cma_init(dev, 32,
|
||||
dev->mode_config.num_crtc,
|
||||
dev->mode_config.num_connector);
|
||||
if (IS_ERR(priv->fbdev))
|
||||
priv->fbdev = NULL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct drm_mode_config_funcs kirin_drm_mode_config_funcs = {
|
||||
.fb_create = drm_fb_cma_create,
|
||||
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
||||
.output_poll_changed = kirin_fbdev_output_poll_changed,
|
||||
#endif
|
||||
.atomic_check = drm_atomic_helper_check,
|
||||
.atomic_commit = drm_atomic_helper_commit,
|
||||
};
|
||||
|
||||
static void kirin_drm_mode_config_init(struct drm_device *dev)
|
||||
{
|
||||
dev->mode_config.min_width = 0;
|
||||
dev->mode_config.min_height = 0;
|
||||
|
||||
dev->mode_config.max_width = 2048;
|
||||
dev->mode_config.max_height = 2048;
|
||||
|
||||
dev->mode_config.funcs = &kirin_drm_mode_config_funcs;
|
||||
}
|
||||
|
||||
static int kirin_drm_kms_init(struct drm_device *dev)
|
||||
{
|
||||
struct kirin_drm_private *priv;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->dev_private = priv;
|
||||
dev_set_drvdata(dev->dev, dev);
|
||||
|
||||
/* dev->mode_config initialization */
|
||||
drm_mode_config_init(dev);
|
||||
kirin_drm_mode_config_init(dev);
|
||||
|
||||
/* display controller init */
|
||||
ret = dc_ops->init(dev);
|
||||
if (ret)
|
||||
goto err_mode_config_cleanup;
|
||||
|
||||
/* bind and init sub drivers */
|
||||
ret = component_bind_all(dev->dev, dev);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to bind all component.\n");
|
||||
goto err_dc_cleanup;
|
||||
}
|
||||
|
||||
/* vblank init */
|
||||
ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
|
||||
if (ret) {
|
||||
DRM_ERROR("failed to initialize vblank.\n");
|
||||
goto err_unbind_all;
|
||||
}
|
||||
/* with irq_enabled = true, we can use the vblank feature. */
|
||||
dev->irq_enabled = true;
|
||||
|
||||
/* reset all the states of crtc/plane/encoder/connector */
|
||||
drm_mode_config_reset(dev);
|
||||
|
||||
/* init kms poll for handling hpd */
|
||||
drm_kms_helper_poll_init(dev);
|
||||
|
||||
/* force detection after connectors init */
|
||||
(void)drm_helper_hpd_irq_event(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_unbind_all:
|
||||
component_unbind_all(dev->dev, dev);
|
||||
err_dc_cleanup:
|
||||
dc_ops->cleanup(dev);
|
||||
err_mode_config_cleanup:
|
||||
drm_mode_config_cleanup(dev);
|
||||
devm_kfree(dev->dev, priv);
|
||||
dev->dev_private = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct file_operations kirin_drm_fops = {
|
||||
.owner = THIS_MODULE,
|
||||
.open = drm_open,
|
||||
.release = drm_release,
|
||||
.unlocked_ioctl = drm_ioctl,
|
||||
#ifdef CONFIG_COMPAT
|
||||
.compat_ioctl = drm_compat_ioctl,
|
||||
#endif
|
||||
.poll = drm_poll,
|
||||
.read = drm_read,
|
||||
.llseek = no_llseek,
|
||||
.mmap = drm_gem_cma_mmap,
|
||||
};
|
||||
|
||||
static int kirin_gem_cma_dumb_create(struct drm_file *file,
|
||||
struct drm_device *dev,
|
||||
struct drm_mode_create_dumb *args)
|
||||
{
|
||||
return drm_gem_cma_dumb_create_internal(file, dev, args);
|
||||
}
|
||||
|
||||
static struct drm_driver kirin_drm_driver = {
|
||||
.driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
|
||||
DRIVER_ATOMIC | DRIVER_HAVE_IRQ,
|
||||
.fops = &kirin_drm_fops,
|
||||
.set_busid = drm_platform_set_busid,
|
||||
|
||||
.gem_free_object = drm_gem_cma_free_object,
|
||||
.gem_vm_ops = &drm_gem_cma_vm_ops,
|
||||
.dumb_create = kirin_gem_cma_dumb_create,
|
||||
.dumb_map_offset = drm_gem_cma_dumb_map_offset,
|
||||
.dumb_destroy = drm_gem_dumb_destroy,
|
||||
|
||||
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
||||
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
||||
.gem_prime_export = drm_gem_prime_export,
|
||||
.gem_prime_import = drm_gem_prime_import,
|
||||
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
|
||||
.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
|
||||
.gem_prime_vmap = drm_gem_cma_prime_vmap,
|
||||
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
|
||||
.gem_prime_mmap = drm_gem_cma_prime_mmap,
|
||||
|
||||
.name = "kirin",
|
||||
.desc = "Hisilicon Kirin SoCs' DRM Driver",
|
||||
.date = "20150718",
|
||||
.major = 1,
|
||||
.minor = 0,
|
||||
};
|
||||
|
||||
static int compare_of(struct device *dev, void *data)
|
||||
{
|
||||
return dev->of_node == data;
|
||||
}
|
||||
|
||||
static int kirin_drm_connectors_register(struct drm_device *dev)
|
||||
{
|
||||
struct drm_connector *connector;
|
||||
struct drm_connector *failed_connector;
|
||||
int ret;
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
drm_for_each_connector(connector, dev) {
|
||||
ret = drm_connector_register(connector);
|
||||
if (ret) {
|
||||
failed_connector = connector;
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
drm_for_each_connector(connector, dev) {
|
||||
if (failed_connector == connector)
|
||||
break;
|
||||
drm_connector_unregister(connector);
|
||||
}
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int kirin_drm_bind(struct device *dev)
|
||||
{
|
||||
struct drm_driver *driver = &kirin_drm_driver;
|
||||
struct drm_device *drm_dev;
|
||||
int ret;
|
||||
|
||||
drm_dev = drm_dev_alloc(driver, dev);
|
||||
if (!drm_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
drm_dev->platformdev = to_platform_device(dev);
|
||||
|
||||
ret = kirin_drm_kms_init(drm_dev);
|
||||
if (ret)
|
||||
goto err_drm_dev_unref;
|
||||
|
||||
ret = drm_dev_register(drm_dev, 0);
|
||||
if (ret)
|
||||
goto err_kms_cleanup;
|
||||
|
||||
/* connectors should be registered after drm device register */
|
||||
ret = kirin_drm_connectors_register(drm_dev);
|
||||
if (ret)
|
||||
goto err_drm_dev_unregister;
|
||||
|
||||
DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
|
||||
driver->name, driver->major, driver->minor, driver->patchlevel,
|
||||
driver->date, drm_dev->primary->index);
|
||||
|
||||
return 0;
|
||||
|
||||
err_drm_dev_unregister:
|
||||
drm_dev_unregister(drm_dev);
|
||||
err_kms_cleanup:
|
||||
kirin_drm_kms_cleanup(drm_dev);
|
||||
err_drm_dev_unref:
|
||||
drm_dev_unref(drm_dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void kirin_drm_unbind(struct device *dev)
|
||||
{
|
||||
drm_put_dev(dev_get_drvdata(dev));
|
||||
}
|
||||
|
||||
static const struct component_master_ops kirin_drm_ops = {
|
||||
.bind = kirin_drm_bind,
|
||||
.unbind = kirin_drm_unbind,
|
||||
};
|
||||
|
||||
static struct device_node *kirin_get_remote_node(struct device_node *np)
|
||||
{
|
||||
struct device_node *endpoint, *remote;
|
||||
|
||||
/* get the first endpoint, in our case only one remote node
|
||||
* is connected to display controller.
|
||||
*/
|
||||
endpoint = of_graph_get_next_endpoint(np, NULL);
|
||||
if (!endpoint) {
|
||||
DRM_ERROR("no valid endpoint node\n");
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
of_node_put(endpoint);
|
||||
|
||||
remote = of_graph_get_remote_port_parent(endpoint);
|
||||
if (!remote) {
|
||||
DRM_ERROR("no valid remote node\n");
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
of_node_put(remote);
|
||||
|
||||
if (!of_device_is_available(remote)) {
|
||||
DRM_ERROR("not available for remote node\n");
|
||||
return ERR_PTR(-ENODEV);
|
||||
}
|
||||
|
||||
return remote;
|
||||
}
|
||||
|
||||
static int kirin_drm_platform_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct component_match *match = NULL;
|
||||
struct device_node *remote;
|
||||
|
||||
dc_ops = (struct kirin_dc_ops *)of_device_get_match_data(dev);
|
||||
if (!dc_ops) {
|
||||
DRM_ERROR("failed to get dt id data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
remote = kirin_get_remote_node(np);
|
||||
if (IS_ERR(remote))
|
||||
return PTR_ERR(remote);
|
||||
|
||||
component_match_add(dev, &match, compare_of, remote);
|
||||
|
||||
return component_master_add_with_match(dev, &kirin_drm_ops, match);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int kirin_drm_platform_remove(struct platform_device *pdev)
|
||||
{
|
||||
component_master_del(&pdev->dev, &kirin_drm_ops);
|
||||
dc_ops = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id kirin_drm_dt_ids[] = {
|
||||
{ .compatible = "hisilicon,hi6220-ade",
|
||||
.data = &ade_dc_ops,
|
||||
},
|
||||
{ /* end node */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, kirin_drm_dt_ids);
|
||||
|
||||
static struct platform_driver kirin_drm_platform_driver = {
|
||||
.probe = kirin_drm_platform_probe,
|
||||
.remove = kirin_drm_platform_remove,
|
||||
.driver = {
|
||||
.name = "kirin-drm",
|
||||
.of_match_table = kirin_drm_dt_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(kirin_drm_platform_driver);
|
||||
|
||||
MODULE_AUTHOR("Xinliang Liu <xinliang.liu@linaro.org>");
|
||||
MODULE_AUTHOR("Xinliang Liu <z.liuxinliang@hisilicon.com>");
|
||||
MODULE_AUTHOR("Xinwei Kong <kong.kongxinwei@hisilicon.com>");
|
||||
MODULE_DESCRIPTION("hisilicon Kirin SoCs' DRM master driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
31
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h
Normal file
31
drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h
Normal file
@ -0,0 +1,31 @@
|
||||
/*
|
||||
* Copyright (c) 2016 Linaro Limited.
|
||||
* Copyright (c) 2014-2016 Hisilicon Limited.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __KIRIN_DRM_DRV_H__
|
||||
#define __KIRIN_DRM_DRV_H__
|
||||
|
||||
#define MAX_CRTC 2
|
||||
|
||||
/* display controller init/cleanup ops */
|
||||
struct kirin_dc_ops {
|
||||
int (*init)(struct drm_device *dev);
|
||||
void (*cleanup)(struct drm_device *dev);
|
||||
};
|
||||
|
||||
struct kirin_drm_private {
|
||||
struct drm_crtc *crtc[MAX_CRTC];
|
||||
#ifdef CONFIG_DRM_FBDEV_EMULATION
|
||||
struct drm_fbdev_cma *fbdev;
|
||||
#endif
|
||||
};
|
||||
|
||||
extern const struct kirin_dc_ops ade_dc_ops;
|
||||
|
||||
#endif /* __KIRIN_DRM_DRV_H__ */
|
||||
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Reference in New Issue
Block a user