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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
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commit
48ea753075
@ -113,7 +113,7 @@ CONFIG_IOSAPIC=y
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CONFIG_IA64_SGI_SN_XP=m
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CONFIG_FORCE_MAX_ZONEORDER=17
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CONFIG_SMP=y
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CONFIG_NR_CPUS=512
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CONFIG_NR_CPUS=1024
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# CONFIG_HOTPLUG_CPU is not set
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CONFIG_SCHED_SMT=y
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CONFIG_PREEMPT=y
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@ -249,3 +249,32 @@ time_init (void)
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*/
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set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
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}
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#define SMALLUSECS 100
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void
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udelay (unsigned long usecs)
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{
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unsigned long start;
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unsigned long cycles;
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unsigned long smallusecs;
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/*
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* Execute the non-preemptible delay loop (because the ITC might
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* not be synchronized between CPUS) in relatively short time
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* chunks, allowing preemption between the chunks.
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*/
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while (usecs > 0) {
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smallusecs = (usecs > SMALLUSECS) ? SMALLUSECS : usecs;
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preempt_disable();
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cycles = smallusecs*local_cpu_data->cyc_per_usec;
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start = ia64_get_itc();
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while (ia64_get_itc() - start < cycles)
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cpu_relax();
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preempt_enable();
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usecs -= smallusecs;
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}
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}
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EXPORT_SYMBOL(udelay);
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@ -53,7 +53,7 @@ static void uncached_ipi_visibility(void *data)
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if ((status != PAL_VISIBILITY_OK) &&
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(status != PAL_VISIBILITY_OK_REMOTE_NEEDED))
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printk(KERN_DEBUG "pal_prefetch_visibility() returns %i on "
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"CPU %i\n", status, get_cpu());
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"CPU %i\n", status, raw_smp_processor_id());
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}
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@ -63,7 +63,7 @@ static void uncached_ipi_mc_drain(void *data)
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status = ia64_pal_mc_drain();
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if (status)
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printk(KERN_WARNING "ia64_pal_mc_drain() failed with %i on "
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"CPU %i\n", status, get_cpu());
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"CPU %i\n", status, raw_smp_processor_id());
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}
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@ -105,7 +105,7 @@ uncached_get_new_chunk(struct gen_pool *poolp)
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status = ia64_pal_prefetch_visibility(PAL_VISIBILITY_PHYSICAL);
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dprintk(KERN_INFO "pal_prefetch_visibility() returns %i on cpu %i\n",
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status, get_cpu());
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status, raw_smp_processor_id());
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if (!status) {
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status = smp_call_function(uncached_ipi_visibility, NULL, 0, 1);
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@ -177,6 +177,9 @@ SECTIONS
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}
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. = ALIGN(PAGE_SIZE); /* make sure the gate page doesn't expose kernel data */
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.data.read_mostly : AT(ADDR(.data.read_mostly) - LOAD_OFFSET)
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{ *(.data.read_mostly) }
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.data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - LOAD_OFFSET)
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{ *(.data.cacheline_aligned) }
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@ -202,7 +202,7 @@ sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long nbits)
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{
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int i, opt, shub1, cnode, mynasid, cpu, lcpu = 0, nasid, flushed = 0;
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int mymm = (mm == current->active_mm);
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int mymm = (mm == current->active_mm && current->mm);
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volatile unsigned long *ptc0, *ptc1;
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unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value;
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short nasids[MAX_NUMNODES], nix;
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@ -84,14 +84,6 @@ __delay (unsigned long loops)
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ia64_delay_loop (loops - 1);
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}
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static __inline__ void
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udelay (unsigned long usecs)
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{
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unsigned long start = ia64_get_itc();
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unsigned long cycles = usecs*local_cpu_data->cyc_per_usec;
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while (ia64_get_itc() - start < cycles)
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cpu_relax();
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}
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extern void udelay (unsigned long usecs);
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#endif /* _ASM_IA64_DELAY_H */
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@ -13,7 +13,7 @@
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#endif
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#if defined(CONFIG_X86) || defined(CONFIG_SPARC64)
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#if defined(CONFIG_X86) || defined(CONFIG_SPARC64) || defined(CONFIG_IA64)
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#define __read_mostly __attribute__((__section__(".data.read_mostly")))
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#else
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#define __read_mostly
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