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mtd: nand: mxic-ecc: Add Macronix external ECC engine support
Some SPI-NAND chips do not support on-die ECC. For these chips, correction must apply on the SPI controller end. In order to avoid doing all the calculations by software, Macronix provides a specific engine that can offload the intensive work. Add Macronix ECC engine support, this engine can work in conjunction with a SPI controller and a raw NAND controller, it can be pipelined or external and supports linear and syndrome layouts. Right now the simplest configuration is supported: SPI controller external and linear ECC engine. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20211216111654.238086-15-miquel.raynal@bootlin.com
This commit is contained in:
Miquel Raynal
parent
cda32a618d
commit
48e6633a9f
@ -46,6 +46,12 @@ config MTD_NAND_ECC_SW_BCH
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ECC codes. They are used with NAND devices requiring more than 1 bit
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ECC codes. They are used with NAND devices requiring more than 1 bit
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of error correction.
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of error correction.
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config MTD_NAND_ECC_MXIC
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bool "Macronix external hardware ECC engine"
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select MTD_NAND_ECC
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help
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This enables support for the hardware ECC engine from Macronix.
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endmenu
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endmenu
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endmenu
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endmenu
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@ -10,3 +10,4 @@ obj-y += spi/
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nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
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nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o
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nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
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nandcore-$(CONFIG_MTD_NAND_ECC_SW_HAMMING) += ecc-sw-hamming.o
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nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
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nandcore-$(CONFIG_MTD_NAND_ECC_SW_BCH) += ecc-sw-bch.o
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nandcore-$(CONFIG_MTD_NAND_ECC_MXIC) += ecc-mxic.o
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695
drivers/mtd/nand/ecc-mxic.c
Normal file
695
drivers/mtd/nand/ecc-mxic.c
Normal file
@ -0,0 +1,695 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Macronix external hardware ECC engine for NAND devices, also
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* called DPE for Data Processing Engine.
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*
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* Copyright © 2019 Macronix
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* Author: Miquel Raynal <miquel.raynal@bootlin.com>
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*/
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mutex.h>
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#include <linux/of_device.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* DPE Configuration */
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#define DP_CONFIG 0x00
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#define ECC_EN BIT(0)
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#define ECC_TYP(idx) (((idx) << 3) & GENMASK(6, 3))
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/* DPE Interrupt Status */
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#define INTRPT_STS 0x04
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#define TRANS_CMPLT BIT(0)
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#define SDMA_MAIN BIT(1)
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#define SDMA_SPARE BIT(2)
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#define ECC_ERR BIT(3)
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#define TO_SPARE BIT(4)
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#define TO_MAIN BIT(5)
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/* DPE Interrupt Status Enable */
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#define INTRPT_STS_EN 0x08
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/* DPE Interrupt Signal Enable */
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#define INTRPT_SIG_EN 0x0C
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/* Host Controller Configuration */
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#define HC_CONFIG 0x10
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#define MEM2MEM BIT(4) /* TRANS_TYP_IO in the spec */
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#define ECC_PACKED 0 /* LAYOUT_TYP_INTEGRATED in the spec */
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#define ECC_INTERLEAVED BIT(2) /* LAYOUT_TYP_DISTRIBUTED in the spec */
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#define BURST_TYP_FIXED 0
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#define BURST_TYP_INCREASING BIT(0)
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/* Host Controller Slave Address */
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#define HC_SLV_ADDR 0x14
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/* ECC Chunk Size */
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#define CHUNK_SIZE 0x20
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/* Main Data Size */
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#define MAIN_SIZE 0x24
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/* Spare Data Size */
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#define SPARE_SIZE 0x28
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#define META_SZ(reg) ((reg) & GENMASK(7, 0))
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#define PARITY_SZ(reg) (((reg) & GENMASK(15, 8)) >> 8)
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#define RSV_SZ(reg) (((reg) & GENMASK(23, 16)) >> 16)
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#define SPARE_SZ(reg) ((reg) >> 24)
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/* ECC Chunk Count */
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#define CHUNK_CNT 0x30
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/* SDMA Control */
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#define SDMA_CTRL 0x40
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#define WRITE_NAND 0
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#define READ_NAND BIT(1)
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#define CONT_NAND BIT(29)
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#define CONT_SYSM BIT(30) /* Continue System Memory? */
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#define SDMA_STRT BIT(31)
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/* SDMA Address of Main Data */
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#define SDMA_MAIN_ADDR 0x44
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/* SDMA Address of Spare Data */
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#define SDMA_SPARE_ADDR 0x48
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/* DPE Version Number */
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#define DP_VER 0xD0
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#define DP_VER_OFFSET 16
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/* Status bytes between each chunk of spare data */
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#define STAT_BYTES 4
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#define NO_ERR 0x00
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#define MAX_CORR_ERR 0x28
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#define UNCORR_ERR 0xFE
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#define ERASED_CHUNK 0xFF
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struct mxic_ecc_engine {
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct completion complete;
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struct nand_ecc_engine external_engine;
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struct mutex lock;
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};
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struct mxic_ecc_ctx {
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/* ECC machinery */
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unsigned int data_step_sz;
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unsigned int oob_step_sz;
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unsigned int parity_sz;
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unsigned int meta_sz;
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u8 *status;
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int steps;
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/* DMA boilerplate */
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struct nand_ecc_req_tweak_ctx req_ctx;
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u8 *oobwithstat;
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struct scatterlist sg[2];
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struct nand_page_io_req *req;
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};
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static struct mxic_ecc_engine *ext_ecc_eng_to_mxic(struct nand_ecc_engine *eng)
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{
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return container_of(eng, struct mxic_ecc_engine, external_engine);
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}
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static struct mxic_ecc_engine *nand_to_mxic(struct nand_device *nand)
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{
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struct nand_ecc_engine *eng = nand->ecc.engine;
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return ext_ecc_eng_to_mxic(eng);
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}
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static int mxic_ecc_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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struct nand_device *nand = mtd_to_nanddev(mtd);
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struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
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if (section < 0 || section >= ctx->steps)
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return -ERANGE;
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oobregion->offset = (section * ctx->oob_step_sz) + ctx->meta_sz;
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oobregion->length = ctx->parity_sz;
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return 0;
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}
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static int mxic_ecc_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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struct nand_device *nand = mtd_to_nanddev(mtd);
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struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
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if (section < 0 || section >= ctx->steps)
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return -ERANGE;
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if (!section) {
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oobregion->offset = 2;
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oobregion->length = ctx->meta_sz - 2;
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} else {
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oobregion->offset = section * ctx->oob_step_sz;
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oobregion->length = ctx->meta_sz;
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}
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return 0;
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}
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static const struct mtd_ooblayout_ops mxic_ecc_ooblayout_ops = {
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.ecc = mxic_ecc_ooblayout_ecc,
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.free = mxic_ecc_ooblayout_free,
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};
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static void mxic_ecc_disable_engine(struct mxic_ecc_engine *mxic)
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{
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u32 reg;
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reg = readl(mxic->regs + DP_CONFIG);
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reg &= ~ECC_EN;
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writel(reg, mxic->regs + DP_CONFIG);
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}
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static void mxic_ecc_enable_engine(struct mxic_ecc_engine *mxic)
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{
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u32 reg;
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reg = readl(mxic->regs + DP_CONFIG);
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reg |= ECC_EN;
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writel(reg, mxic->regs + DP_CONFIG);
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}
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static void mxic_ecc_disable_int(struct mxic_ecc_engine *mxic)
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{
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writel(0, mxic->regs + INTRPT_SIG_EN);
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}
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static void mxic_ecc_enable_int(struct mxic_ecc_engine *mxic)
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{
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writel(TRANS_CMPLT, mxic->regs + INTRPT_SIG_EN);
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}
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static irqreturn_t mxic_ecc_isr(int irq, void *dev_id)
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{
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struct mxic_ecc_engine *mxic = dev_id;
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u32 sts;
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sts = readl(mxic->regs + INTRPT_STS);
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if (!sts)
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return IRQ_NONE;
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if (sts & TRANS_CMPLT)
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complete(&mxic->complete);
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writel(sts, mxic->regs + INTRPT_STS);
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return IRQ_HANDLED;
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}
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static int mxic_ecc_init_ctx(struct nand_device *nand, struct device *dev)
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{
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struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
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struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
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struct nand_ecc_props *reqs = &nand->ecc.requirements;
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struct nand_ecc_props *user = &nand->ecc.user_conf;
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struct mtd_info *mtd = nanddev_to_mtd(nand);
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int step_size = 0, strength = 0, desired_correction = 0, steps, idx;
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int possible_strength[] = {4, 8, 40, 48};
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int spare_size[] = {32, 32, 96, 96};
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struct mxic_ecc_ctx *ctx;
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u32 spare_reg;
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int ret;
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ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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nand->ecc.ctx.priv = ctx;
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/* Only large page NAND chips may use BCH */
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if (mtd->oobsize < 64) {
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pr_err("BCH cannot be used with small page NAND chips\n");
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return -EINVAL;
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}
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mtd_set_ooblayout(mtd, &mxic_ecc_ooblayout_ops);
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/* Enable all status bits */
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writel(TRANS_CMPLT | SDMA_MAIN | SDMA_SPARE | ECC_ERR |
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TO_SPARE | TO_MAIN, mxic->regs + INTRPT_STS_EN);
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/* Configure the correction depending on the NAND device topology */
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if (user->step_size && user->strength) {
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step_size = user->step_size;
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strength = user->strength;
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} else if (reqs->step_size && reqs->strength) {
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step_size = reqs->step_size;
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strength = reqs->strength;
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}
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if (step_size && strength) {
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steps = mtd->writesize / step_size;
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desired_correction = steps * strength;
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}
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/* Step size is fixed to 1kiB, strength may vary (4 possible values) */
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conf->step_size = SZ_1K;
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steps = mtd->writesize / conf->step_size;
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ctx->status = devm_kzalloc(dev, steps * sizeof(u8), GFP_KERNEL);
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if (!ctx->status)
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return -ENOMEM;
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if (desired_correction) {
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strength = desired_correction / steps;
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for (idx = 0; idx < ARRAY_SIZE(possible_strength); idx++)
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if (possible_strength[idx] >= strength)
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break;
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idx = min_t(unsigned int, idx,
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ARRAY_SIZE(possible_strength) - 1);
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} else {
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/* Missing data, maximize the correction */
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idx = ARRAY_SIZE(possible_strength) - 1;
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}
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/* Tune the selected strength until it fits in the OOB area */
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for (; idx >= 0; idx--) {
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if (spare_size[idx] * steps <= mtd->oobsize)
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break;
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}
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/* This engine cannot be used with this NAND device */
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if (idx < 0)
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return -EINVAL;
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/* Configure the engine for the desired strength */
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writel(ECC_TYP(idx), mxic->regs + DP_CONFIG);
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conf->strength = possible_strength[idx];
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spare_reg = readl(mxic->regs + SPARE_SIZE);
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ctx->steps = steps;
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ctx->data_step_sz = mtd->writesize / steps;
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ctx->oob_step_sz = mtd->oobsize / steps;
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ctx->parity_sz = PARITY_SZ(spare_reg);
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ctx->meta_sz = META_SZ(spare_reg);
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/* Ensure buffers will contain enough bytes to store the STAT_BYTES */
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ctx->req_ctx.oob_buffer_size = nanddev_per_page_oobsize(nand) +
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(ctx->steps * STAT_BYTES);
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ret = nand_ecc_init_req_tweaking(&ctx->req_ctx, nand);
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if (ret)
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return ret;
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ctx->oobwithstat = kmalloc(mtd->oobsize + (ctx->steps * STAT_BYTES),
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GFP_KERNEL);
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if (!ctx->oobwithstat) {
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ret = -ENOMEM;
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goto cleanup_req_tweak;
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}
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sg_init_table(ctx->sg, 2);
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/* Configuration dump and sanity checks */
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dev_err(dev, "DPE version number: %d\n",
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readl(mxic->regs + DP_VER) >> DP_VER_OFFSET);
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dev_err(dev, "Chunk size: %d\n", readl(mxic->regs + CHUNK_SIZE));
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dev_err(dev, "Main size: %d\n", readl(mxic->regs + MAIN_SIZE));
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dev_err(dev, "Spare size: %d\n", SPARE_SZ(spare_reg));
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dev_err(dev, "Rsv size: %ld\n", RSV_SZ(spare_reg));
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dev_err(dev, "Parity size: %d\n", ctx->parity_sz);
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dev_err(dev, "Meta size: %d\n", ctx->meta_sz);
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if ((ctx->meta_sz + ctx->parity_sz + RSV_SZ(spare_reg)) !=
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SPARE_SZ(spare_reg)) {
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dev_err(dev, "Wrong OOB configuration: %d + %d + %ld != %d\n",
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ctx->meta_sz, ctx->parity_sz, RSV_SZ(spare_reg),
|
||||||
|
SPARE_SZ(spare_reg));
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto free_oobwithstat;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ctx->oob_step_sz != SPARE_SZ(spare_reg)) {
|
||||||
|
dev_err(dev, "Wrong OOB configuration: %d != %d\n",
|
||||||
|
ctx->oob_step_sz, SPARE_SZ(spare_reg));
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto free_oobwithstat;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
free_oobwithstat:
|
||||||
|
kfree(ctx->oobwithstat);
|
||||||
|
cleanup_req_tweak:
|
||||||
|
nand_ecc_cleanup_req_tweaking(&ctx->req_ctx);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mxic_ecc_init_ctx_external(struct nand_device *nand)
|
||||||
|
{
|
||||||
|
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
|
||||||
|
struct device *dev = nand->ecc.engine->dev;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
dev_info(dev, "Macronix ECC engine in external mode\n");
|
||||||
|
|
||||||
|
ret = mxic_ecc_init_ctx(nand, dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Trigger each step manually */
|
||||||
|
writel(1, mxic->regs + CHUNK_CNT);
|
||||||
|
writel(BURST_TYP_INCREASING | ECC_PACKED | MEM2MEM,
|
||||||
|
mxic->regs + HC_CONFIG);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mxic_ecc_cleanup_ctx(struct nand_device *nand)
|
||||||
|
{
|
||||||
|
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
|
||||||
|
|
||||||
|
if (ctx) {
|
||||||
|
nand_ecc_cleanup_req_tweaking(&ctx->req_ctx);
|
||||||
|
kfree(ctx->oobwithstat);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mxic_ecc_data_xfer_wait_for_completion(struct mxic_ecc_engine *mxic)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (mxic->irq) {
|
||||||
|
reinit_completion(&mxic->complete);
|
||||||
|
mxic_ecc_enable_int(mxic);
|
||||||
|
ret = wait_for_completion_timeout(&mxic->complete,
|
||||||
|
msecs_to_jiffies(1000));
|
||||||
|
mxic_ecc_disable_int(mxic);
|
||||||
|
} else {
|
||||||
|
ret = readl_poll_timeout(mxic->regs + INTRPT_STS, val,
|
||||||
|
val & TRANS_CMPLT, 10, USEC_PER_SEC);
|
||||||
|
writel(val, mxic->regs + INTRPT_STS);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
dev_err(mxic->dev, "Timeout on data xfer completion\n");
|
||||||
|
return -ETIMEDOUT;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mxic_ecc_process_data(struct mxic_ecc_engine *mxic,
|
||||||
|
unsigned int direction)
|
||||||
|
{
|
||||||
|
unsigned int dir = (direction == NAND_PAGE_READ) ?
|
||||||
|
READ_NAND : WRITE_NAND;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
mxic_ecc_enable_engine(mxic);
|
||||||
|
|
||||||
|
/* Trigger processing */
|
||||||
|
writel(SDMA_STRT | dir, mxic->regs + SDMA_CTRL);
|
||||||
|
|
||||||
|
/* Wait for completion */
|
||||||
|
ret = mxic_ecc_data_xfer_wait_for_completion(mxic);
|
||||||
|
|
||||||
|
mxic_ecc_disable_engine(mxic);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mxic_ecc_extract_status_bytes(struct mxic_ecc_ctx *ctx)
|
||||||
|
{
|
||||||
|
u8 *buf = ctx->oobwithstat;
|
||||||
|
int next_stat_pos;
|
||||||
|
int step;
|
||||||
|
|
||||||
|
/* Extract the ECC status */
|
||||||
|
for (step = 0; step < ctx->steps; step++) {
|
||||||
|
next_stat_pos = ctx->oob_step_sz +
|
||||||
|
((STAT_BYTES + ctx->oob_step_sz) * step);
|
||||||
|
|
||||||
|
ctx->status[step] = buf[next_stat_pos];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mxic_ecc_reconstruct_oobbuf(struct mxic_ecc_ctx *ctx,
|
||||||
|
u8 *dst, const u8 *src)
|
||||||
|
{
|
||||||
|
int step;
|
||||||
|
|
||||||
|
/* Reconstruct the OOB buffer linearly (without the ECC status bytes) */
|
||||||
|
for (step = 0; step < ctx->steps; step++)
|
||||||
|
memcpy(dst + (step * ctx->oob_step_sz),
|
||||||
|
src + (step * (ctx->oob_step_sz + STAT_BYTES)),
|
||||||
|
ctx->oob_step_sz);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mxic_ecc_add_room_in_oobbuf(struct mxic_ecc_ctx *ctx,
|
||||||
|
u8 *dst, const u8 *src)
|
||||||
|
{
|
||||||
|
int step;
|
||||||
|
|
||||||
|
/* Add some space in the OOB buffer for the status bytes */
|
||||||
|
for (step = 0; step < ctx->steps; step++)
|
||||||
|
memcpy(dst + (step * (ctx->oob_step_sz + STAT_BYTES)),
|
||||||
|
src + (step * ctx->oob_step_sz),
|
||||||
|
ctx->oob_step_sz);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mxic_ecc_count_biterrs(struct mxic_ecc_engine *mxic,
|
||||||
|
struct nand_device *nand)
|
||||||
|
{
|
||||||
|
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
|
||||||
|
struct mtd_info *mtd = nanddev_to_mtd(nand);
|
||||||
|
struct device *dev = mxic->dev;
|
||||||
|
unsigned int max_bf = 0;
|
||||||
|
bool failure = false;
|
||||||
|
int step;
|
||||||
|
|
||||||
|
for (step = 0; step < ctx->steps; step++) {
|
||||||
|
u8 stat = ctx->status[step];
|
||||||
|
|
||||||
|
if (stat == NO_ERR) {
|
||||||
|
dev_dbg(dev, "ECC step %d: no error\n", step);
|
||||||
|
} else if (stat == ERASED_CHUNK) {
|
||||||
|
dev_dbg(dev, "ECC step %d: erased\n", step);
|
||||||
|
} else if (stat == UNCORR_ERR || stat > MAX_CORR_ERR) {
|
||||||
|
dev_dbg(dev, "ECC step %d: uncorrectable\n", step);
|
||||||
|
mtd->ecc_stats.failed++;
|
||||||
|
failure = true;
|
||||||
|
} else {
|
||||||
|
dev_dbg(dev, "ECC step %d: %d bits corrected\n",
|
||||||
|
step, stat);
|
||||||
|
max_bf = max_t(unsigned int, max_bf, stat);
|
||||||
|
mtd->ecc_stats.corrected += stat;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return failure ? -EBADMSG : max_bf;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* External ECC engine helpers */
|
||||||
|
static int mxic_ecc_prepare_io_req_external(struct nand_device *nand,
|
||||||
|
struct nand_page_io_req *req)
|
||||||
|
{
|
||||||
|
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
|
||||||
|
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
|
||||||
|
struct mtd_info *mtd = nanddev_to_mtd(nand);
|
||||||
|
int offset, nents, step, ret;
|
||||||
|
|
||||||
|
if (req->mode == MTD_OPS_RAW)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
nand_ecc_tweak_req(&ctx->req_ctx, req);
|
||||||
|
ctx->req = req;
|
||||||
|
|
||||||
|
if (req->type == NAND_PAGE_READ)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat,
|
||||||
|
ctx->req->oobbuf.out);
|
||||||
|
|
||||||
|
sg_set_buf(&ctx->sg[0], req->databuf.out, req->datalen);
|
||||||
|
sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
|
||||||
|
req->ooblen + (ctx->steps * STAT_BYTES));
|
||||||
|
|
||||||
|
nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
|
||||||
|
if (!nents)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
mutex_lock(&mxic->lock);
|
||||||
|
|
||||||
|
for (step = 0; step < ctx->steps; step++) {
|
||||||
|
writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
|
||||||
|
mxic->regs + SDMA_MAIN_ADDR);
|
||||||
|
writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
|
||||||
|
mxic->regs + SDMA_SPARE_ADDR);
|
||||||
|
ret = mxic_ecc_process_data(mxic, ctx->req->type);
|
||||||
|
if (ret)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_unlock(&mxic->lock);
|
||||||
|
|
||||||
|
dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
|
||||||
|
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Retrieve the calculated ECC bytes */
|
||||||
|
for (step = 0; step < ctx->steps; step++) {
|
||||||
|
offset = ctx->meta_sz + (step * ctx->oob_step_sz);
|
||||||
|
mtd_ooblayout_get_eccbytes(mtd,
|
||||||
|
(u8 *)ctx->req->oobbuf.out + offset,
|
||||||
|
ctx->oobwithstat + (step * STAT_BYTES),
|
||||||
|
step * ctx->parity_sz,
|
||||||
|
ctx->parity_sz);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mxic_ecc_finish_io_req_external(struct nand_device *nand,
|
||||||
|
struct nand_page_io_req *req)
|
||||||
|
{
|
||||||
|
struct mxic_ecc_engine *mxic = nand_to_mxic(nand);
|
||||||
|
struct mxic_ecc_ctx *ctx = nand_to_ecc_ctx(nand);
|
||||||
|
int nents, step, ret;
|
||||||
|
|
||||||
|
if (req->mode == MTD_OPS_RAW)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (req->type == NAND_PAGE_WRITE) {
|
||||||
|
nand_ecc_restore_req(&ctx->req_ctx, req);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Copy the OOB buffer and add room for the ECC engine status bytes */
|
||||||
|
mxic_ecc_add_room_in_oobbuf(ctx, ctx->oobwithstat, ctx->req->oobbuf.in);
|
||||||
|
|
||||||
|
sg_set_buf(&ctx->sg[0], req->databuf.in, req->datalen);
|
||||||
|
sg_set_buf(&ctx->sg[1], ctx->oobwithstat,
|
||||||
|
req->ooblen + (ctx->steps * STAT_BYTES));
|
||||||
|
nents = dma_map_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
|
||||||
|
if (!nents)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
mutex_lock(&mxic->lock);
|
||||||
|
|
||||||
|
for (step = 0; step < ctx->steps; step++) {
|
||||||
|
writel(sg_dma_address(&ctx->sg[0]) + (step * ctx->data_step_sz),
|
||||||
|
mxic->regs + SDMA_MAIN_ADDR);
|
||||||
|
writel(sg_dma_address(&ctx->sg[1]) + (step * (ctx->oob_step_sz + STAT_BYTES)),
|
||||||
|
mxic->regs + SDMA_SPARE_ADDR);
|
||||||
|
ret = mxic_ecc_process_data(mxic, ctx->req->type);
|
||||||
|
if (ret)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_unlock(&mxic->lock);
|
||||||
|
|
||||||
|
dma_unmap_sg(mxic->dev, ctx->sg, 2, DMA_BIDIRECTIONAL);
|
||||||
|
|
||||||
|
/* Extract the status bytes and reconstruct the buffer */
|
||||||
|
mxic_ecc_extract_status_bytes(ctx);
|
||||||
|
mxic_ecc_reconstruct_oobbuf(ctx, ctx->req->oobbuf.in, ctx->oobwithstat);
|
||||||
|
|
||||||
|
nand_ecc_restore_req(&ctx->req_ctx, req);
|
||||||
|
|
||||||
|
return mxic_ecc_count_biterrs(mxic, nand);
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct nand_ecc_engine_ops mxic_ecc_engine_external_ops = {
|
||||||
|
.init_ctx = mxic_ecc_init_ctx_external,
|
||||||
|
.cleanup_ctx = mxic_ecc_cleanup_ctx,
|
||||||
|
.prepare_io_req = mxic_ecc_prepare_io_req_external,
|
||||||
|
.finish_io_req = mxic_ecc_finish_io_req_external,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int mxic_ecc_probe(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
struct mxic_ecc_engine *mxic;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
mxic = devm_kzalloc(&pdev->dev, sizeof(*mxic), GFP_KERNEL);
|
||||||
|
if (!mxic)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
mxic->dev = &pdev->dev;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Both memory regions for the ECC engine itself and the AXI slave
|
||||||
|
* address are mandatory.
|
||||||
|
*/
|
||||||
|
mxic->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||||
|
if (IS_ERR(mxic->regs)) {
|
||||||
|
dev_err(&pdev->dev, "Missing memory region\n");
|
||||||
|
return PTR_ERR(mxic->regs);
|
||||||
|
}
|
||||||
|
|
||||||
|
mxic_ecc_disable_engine(mxic);
|
||||||
|
mxic_ecc_disable_int(mxic);
|
||||||
|
|
||||||
|
/* IRQ is optional yet much more efficient */
|
||||||
|
mxic->irq = platform_get_irq_byname_optional(pdev, "ecc-engine");
|
||||||
|
if (mxic->irq > 0) {
|
||||||
|
ret = devm_request_irq(&pdev->dev, mxic->irq, mxic_ecc_isr, 0,
|
||||||
|
"mxic-ecc", mxic);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
} else {
|
||||||
|
dev_info(dev, "Invalid or missing IRQ, fallback to polling\n");
|
||||||
|
mxic->irq = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
mutex_init(&mxic->lock);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* In external mode, the device is the ECC engine. In pipelined mode,
|
||||||
|
* the device is the host controller. The device is used to match the
|
||||||
|
* right ECC engine based on the DT properties.
|
||||||
|
*/
|
||||||
|
mxic->external_engine.dev = &pdev->dev;
|
||||||
|
mxic->external_engine.integration = NAND_ECC_ENGINE_INTEGRATION_EXTERNAL;
|
||||||
|
mxic->external_engine.ops = &mxic_ecc_engine_external_ops;
|
||||||
|
|
||||||
|
nand_ecc_register_on_host_hw_engine(&mxic->external_engine);
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, mxic);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mxic_ecc_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct mxic_ecc_engine *mxic = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
nand_ecc_unregister_on_host_hw_engine(&mxic->external_engine);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id mxic_ecc_of_ids[] = {
|
||||||
|
{
|
||||||
|
.compatible = "mxicy,nand-ecc-engine-rev3",
|
||||||
|
},
|
||||||
|
{ /* sentinel */ },
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, mxic_ecc_of_ids);
|
||||||
|
|
||||||
|
static struct platform_driver mxic_ecc_driver = {
|
||||||
|
.driver = {
|
||||||
|
.name = "mxic-nand-ecc-engine",
|
||||||
|
.of_match_table = mxic_ecc_of_ids,
|
||||||
|
},
|
||||||
|
.probe = mxic_ecc_probe,
|
||||||
|
.remove = mxic_ecc_remove,
|
||||||
|
};
|
||||||
|
module_platform_driver(mxic_ecc_driver);
|
||||||
|
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
|
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
|
||||||
|
MODULE_DESCRIPTION("Macronix NAND hardware ECC controller");
|
||||||
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