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MAINTAINERS:

Browse Source 
- drop Ben as he retired from nouveau
 
 core:
 - drm_mm test fixes
 
 fbdev:
 - Kconfig fixes
 
 ivpu:
 - IRQ-handling fixes
 
 meson:
 - Fix memory leak in HDMI EDID code
 
 nouveau:
 - Correct type casting
 - Fix memory leak in scheduler
 - u_memcpya() fixes
 
 i915:
 - Prevent error pointer dereference
 - Fix PMU busyness values when using GuC mode
 
 amdgpu:
 - MST fix
 - Vbios part number reporting fix
 - Fix a possible memory leak in an error case in the RAS code
 - Fix low resolution modes on eDP
 
 amdkfd:
 - Fix GPU address for user queue wptr when GART is not at 0
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Merge tag 'drm-fixes-2023-09-22-2' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Ben Skeggs is stepping away from nouveau and Red Hat for personal
  reasons, he'll be missed and we intend to fill the gaps in the
  upcoming time with Danilo and Lyude stepping in for now.

  Otherwise i915, nouveau, amdgpu with a few each and some misc spread
  around.

  MAINTAINERS:
   - drop Ben as he retired from nouveau

  core:
   - drm_mm test fixes

  fbdev:
   - Kconfig fixes

  ivpu:
   - IRQ-handling fixes

  meson:
   - Fix memory leak in HDMI EDID code

  nouveau:
   - Correct type casting
   - Fix memory leak in scheduler
   - u_memcpya() fixes

  i915:
   - Prevent error pointer dereference
   - Fix PMU busyness values when using GuC mode

  amdgpu:
   - MST fix
   - Vbios part number reporting fix
   - Fix a possible memory leak in an error case in the RAS code
   - Fix low resolution modes on eDP

  amdkfd:
   - Fix GPU address for user queue wptr when GART is not at 0"

* tag 'drm-fixes-2023-09-22-2' of git://anongit.freedesktop.org/drm/drm:
  MAINTAINERS: remove myself as nouveau maintainer
  fbdev/sh7760fb: Depend on FB=y
  drm/amdkfd: Use gpu_offset for user queue's wptr
  drm/amd/display: fix the ability to use lower resolution modes on eDP
  drm/amdgpu: fix a memory leak in amdgpu_ras_feature_enable
  Revert "drm/amdgpu: Report vbios version instead of PN"
  drm/amd/display: Fix MST recognizes connected displays as one
  drm/virtio: clean out_fence on complete_submit
  i915/pmu: Move execlist stats initialization to execlist specific setup
  drm/i915/gt: Prevent error pointer dereference
  drm/meson: fix memory leak on ->hpd_notify callback
  accel/ivpu/40xx: Fix buttress interrupt handling
  nouveau/u_memcpya: fix NULL vs error pointer bug
  nouveau/u_memcpya: use vmemdup_user
  drm/nouveau: sched: fix leaking memory of timedout job
  drm/nouveau: fence: fix type cast warning in nouveau_fence_emit()
  drm: fix up fbdev Kconfig defaults
  drm/tests: Fix incorrect argument in drm_test_mm_insert_range
This commit is contained in:
Linus Torvalds 2023-09-22 09:18:51 -07:00
commit 48bb67d3f1
23 changed files with 61 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -6645,7 +6645,6 @@ F: Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml
F: drivers/gpu/drm/panel/panel-novatek-nt36672a.c
DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS
M: Ben Skeggs <bskeggs@redhat.com>
M: Karol Herbst <kherbst@redhat.com>
M: Lyude Paul <lyude@redhat.com>
L: dri-devel@lists.freedesktop.org

9
drivers/accel/ivpu/ivpu_hw_40xx.c
View File

@ -1046,7 +1046,8 @@ static irqreturn_t ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
if (status == 0)
return IRQ_NONE;
REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);
/* Disable global interrupt before handling local buttress interrupts */
REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x1);
if (REG_TEST_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE, status))
ivpu_dbg(vdev, IRQ, "FREQ_CHANGE");
@ -1092,6 +1093,12 @@ static irqreturn_t ivpu_hw_40xx_irqb_handler(struct ivpu_device *vdev, int irq)
schedule_recovery = true;
}
/* This must be done after interrupts are cleared at the source. */
REGB_WR32(VPU_40XX_BUTTRESS_INTERRUPT_STAT, status);
/* Re-enable global interrupt */
REGB_WR32(VPU_40XX_BUTTRESS_GLOBAL_INT_MASK, 0x0);
if (schedule_recovery)
ivpu_pm_schedule_recovery(vdev);

2
drivers/gpu/drm/Kconfig
View File

@ -136,7 +136,7 @@ config DRM_FBDEV_EMULATION
bool "Enable legacy fbdev support for your modesetting driver"
depends on DRM
select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE
default y
default FB
help
Choose this option if you have a need for the legacy fbdev
support. Note that this support also provides the linux console

2
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
View File

@ -1776,7 +1776,7 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
struct amdgpu_device *adev = drm_to_adev(ddev);
struct atom_context *ctx = adev->mode_info.atom_context;
return sysfs_emit(buf, "%s\n", ctx->vbios_ver_str);
return sysfs_emit(buf, "%s\n", ctx->vbios_pn);
}
static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,

1
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
View File

@ -801,6 +801,7 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
enable ? "enable":"disable",
get_ras_block_str(head),
amdgpu_ras_is_poison_mode_supported(adev), ret);
kfree(info);
return ret;
}

2
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
View File

@ -216,7 +216,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
if (q->wptr_bo) {
wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1);
queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off;
queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->wptr_bo) + wptr_addr_off;
}
queue_input.is_kfd_process = 1;

4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -6098,8 +6098,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
if (recalculate_timing)
drm_mode_set_crtcinfo(&saved_mode, 0);
else if (!old_stream)
drm_mode_set_crtcinfo(&mode, 0);
/*
* If scaling is enabled and refresh rate didn't change
@ -6661,6 +6659,8 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec
goto fail;
}
drm_mode_set_crtcinfo(mode, 0);
stream = create_validate_stream_for_sink(aconnector, mode,
to_dm_connector_state(connector->state),
NULL);

30
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1178,12 +1178,15 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
dto_params.otg_inst = tg->inst;
dto_params.timing = &pipe_ctx->stream->timing;
dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se)
if (dccg) {
dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);
}
} else if (dccg && dccg->funcs->disable_symclk_se) {
dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
link_enc->transmitter - TRANSMITTER_UNIPHY_A);
}
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
/* TODO: This looks like a bug to me as we are disabling HPO IO when
@ -2658,11 +2661,11 @@ void dce110_prepare_bandwidth(
struct clk_mgr *dccg = dc->clk_mgr;
dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
dccg->funcs->update_clocks(
dccg,
context,
false);
if (dccg)
dccg->funcs->update_clocks(
dccg,
context,
false);
}
void dce110_optimize_bandwidth(
@ -2673,10 +2676,11 @@ void dce110_optimize_bandwidth(
dce110_set_displaymarks(dc, context);
dccg->funcs->update_clocks(
dccg,
context,
true);
if (dccg)
dccg->funcs->update_clocks(
dccg,
context,
true);
}
static void dce110_program_front_end_for_pipe(

8
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View File

@ -2692,8 +2692,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
struct dce_hwseq *hws = dc->hwseq;
unsigned int k1_div = PIXEL_RATE_DIV_NA;
unsigned int k2_div = PIXEL_RATE_DIV_NA;
struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
if (dc->hwseq->funcs.setup_hpo_hw_control)
@ -2713,10 +2711,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
dto_params.timing = &pipe_ctx->stream->timing;
dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);
dccg->funcs->set_dtbclk_dto(dccg, &dto_params);
} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se)
dccg->funcs->enable_symclk_se(dccg,
stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A);
} else {
}
if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);

2
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c
View File

@ -75,7 +75,7 @@ void mpc32_power_on_blnd_lut(
if (power_on) {
REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0);
REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5);
} else {
} else if (!mpc->ctx->dc->debug.disable_mem_low_power) {
ASSERT(false);
/* TODO: change to mpc
* dpp_base->ctx->dc->optimized_required = true;

1
drivers/gpu/drm/i915/gt/intel_engine_cs.c
View File

@ -558,7 +558,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
DRIVER_CAPS(i915)->has_logical_contexts = true;
ewma__engine_latency_init(&engine->latency);
seqcount_init(&engine->stats.execlists.lock);
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);

2
drivers/gpu/drm/i915/gt/intel_execlists_submission.c
View File

@ -3550,6 +3550,8 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
logical_ring_default_vfuncs(engine);
logical_ring_default_irqs(engine);
seqcount_init(&engine->stats.execlists.lock);
if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
rcs_submission_override(engine);

5
drivers/gpu/drm/i915/gt/intel_lrc.c
View File

@ -1094,6 +1094,9 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj)) {
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
return ERR_CAST(obj);
/*
* Wa_22016122933: For Media version 13.0, all Media GT shared
* memory needs to be mapped as WC on CPU side and UC (PAT
@ -1102,8 +1105,6 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
if (intel_gt_needs_wa_22016122933(engine->gt))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
}
if (IS_ERR(obj))
return ERR_CAST(obj);
vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
if (IS_ERR(vma)) {

2
drivers/gpu/drm/meson/meson_encoder_hdmi.c
View File

@ -334,6 +334,8 @@ static void meson_encoder_hdmi_hpd_notify(struct drm_bridge *bridge,
return;
cec_notifier_set_phys_addr_from_edid(encoder_hdmi->cec_notifier, edid);
kfree(edid);
} else
cec_notifier_phys_addr_invalidate(encoder_hdmi->cec_notifier);
}

19
drivers/gpu/drm/nouveau/nouveau_drv.h
View File

@ -189,21 +189,12 @@ u_free(void *addr)
static inline void *
u_memcpya(uint64_t user, unsigned int nmemb, unsigned int size)
{
void *mem;
void __user *userptr = (void __force __user *)(uintptr_t)user;
void __user *userptr = u64_to_user_ptr(user);
size_t bytes;
size *= nmemb;
mem = kvmalloc(size, GFP_KERNEL);
if (!mem)
return ERR_PTR(-ENOMEM);
if (copy_from_user(mem, userptr, size)) {
u_free(mem);
return ERR_PTR(-EFAULT);
}
return mem;
if (unlikely(check_mul_overflow(nmemb, size, &bytes)))
return ERR_PTR(-EOVERFLOW);
return vmemdup_user(userptr, bytes);
}
#include <nvif/object.h>

2
drivers/gpu/drm/nouveau/nouveau_exec.c
View File

@ -213,7 +213,7 @@ nouveau_exec_job_timeout(struct nouveau_job *job)
nouveau_sched_entity_fini(job->entity);
return DRM_GPU_SCHED_STAT_ENODEV;
return DRM_GPU_SCHED_STAT_NOMINAL;
}
static struct nouveau_job_ops nouveau_exec_job_ops = {

2
drivers/gpu/drm/nouveau/nouveau_fence.c
View File

@ -207,7 +207,7 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha
int
nouveau_fence_emit(struct nouveau_fence *fence)
{
struct nouveau_channel *chan = fence->channel;
struct nouveau_channel *chan = unrcu_pointer(fence->channel);
struct nouveau_fence_chan *fctx = chan->fence;
struct nouveau_fence_priv *priv = (void*)chan->drm->fence;
int ret;

12
drivers/gpu/drm/nouveau/nouveau_sched.c
View File

@ -375,14 +375,20 @@ nouveau_sched_run_job(struct drm_sched_job *sched_job)
static enum drm_gpu_sched_stat
nouveau_sched_timedout_job(struct drm_sched_job *sched_job)
{
struct drm_gpu_scheduler *sched = sched_job->sched;
struct nouveau_job *job = to_nouveau_job(sched_job);
enum drm_gpu_sched_stat stat = DRM_GPU_SCHED_STAT_NOMINAL;
NV_PRINTK(warn, job->cli, "Job timed out.\n");
drm_sched_stop(sched, sched_job);
if (job->ops->timeout)
return job->ops->timeout(job);
stat = job->ops->timeout(job);
else
NV_PRINTK(warn, job->cli, "Generic job timeout.\n");
return DRM_GPU_SCHED_STAT_ENODEV;
drm_sched_start(sched, true);
return stat;
}
static void

2
drivers/gpu/drm/tests/drm_mm_test.c
View File

@ -939,7 +939,7 @@ static void drm_test_mm_insert_range(struct kunit *test)
KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size, 0, max - 1));
KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size, 0, max / 2));
KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size,
max / 2, max / 2));
max / 2, max));
KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size,
max / 4 + 1, 3 * max / 4 - 1));

1
drivers/gpu/drm/virtio/virtgpu_submit.c
View File

@ -361,7 +361,6 @@ static void virtio_gpu_complete_submit(struct virtio_gpu_submit *submit)
submit->buf = NULL;
submit->buflist = NULL;
submit->sync_file = NULL;
submit->out_fence = NULL;
submit->out_fence_fd = -1;
}

1
drivers/video/console/Kconfig
View File

@ -73,6 +73,7 @@ config DUMMY_CONSOLE_ROWS
config FRAMEBUFFER_CONSOLE
bool "Framebuffer Console support"
depends on FB_CORE && !UML
default DRM_FBDEV_EMULATION
select VT_HW_CONSOLE_BINDING
select CRC32
select FONT_SUPPORT

2
drivers/video/fbdev/Kconfig
View File

@ -1762,7 +1762,7 @@ config FB_COBALT
config FB_SH7760
bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
depends on FB=y && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
|| CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
select FB_IOMEM_HELPERS
help

2
drivers/video/fbdev/core/Kconfig
View File

@ -28,7 +28,7 @@ config FIRMWARE_EDID
config FB_DEVICE
bool "Provide legacy /dev/fb* device"
depends on FB_CORE
default y
default FB
help
Say Y here if you want the legacy /dev/fb* device file and
interfaces within sysfs anc procfs. It is only required if you