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sh_eth: TSU_QTAG0/1 registers the same as TSU_QTAGM0/1
The TSU_QTAG0/1 registers found in the Gigabit Ether controllers actually
have the same long name as the TSU_QTAGM0/1 registers in the early Ether
controllers: Qtag Addition/Deletion Set Register (Port 0/1 to 1/0); thus
there's no need to make a difference in sh_eth_tsu_init() between those
controllers. Unfortunately, we can't just remove TSU_QTAG0/1 from the
register *enum* because that would break the ethtool register dump...
Fixes: b0ca2a21f7
("sh_eth: Add support of SH7763 to sh_eth")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
3adc1c63e2
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@ -123,8 +123,8 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
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[TSU_FWSL0] = 0x0030,
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[TSU_FWSL1] = 0x0034,
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[TSU_FWSLC] = 0x0038,
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[TSU_QTAG0] = 0x0040,
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[TSU_QTAG1] = 0x0044,
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[TSU_QTAGM0] = 0x0040,
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[TSU_QTAGM1] = 0x0044,
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[TSU_FWSR] = 0x0050,
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[TSU_FWINMK] = 0x0054,
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[TSU_ADQT0] = 0x0048,
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@ -2097,8 +2097,6 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
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add_tsu_reg(TSU_FWSL0);
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add_tsu_reg(TSU_FWSL1);
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add_tsu_reg(TSU_FWSLC);
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add_tsu_reg(TSU_QTAG0);
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add_tsu_reg(TSU_QTAG1);
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add_tsu_reg(TSU_QTAGM0);
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add_tsu_reg(TSU_QTAGM1);
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add_tsu_reg(TSU_FWSR);
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@ -2934,13 +2932,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp)
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sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
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sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
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sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
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if (sh_eth_is_gether(mdp)) {
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sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
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sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
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} else {
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sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
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sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
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}
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sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
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sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
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sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
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sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
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sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
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@ -118,8 +118,8 @@ enum {
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TSU_FWSL0,
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TSU_FWSL1,
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TSU_FWSLC,
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TSU_QTAG0,
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TSU_QTAG1,
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TSU_QTAG0, /* Same as TSU_QTAGM0 */
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TSU_QTAG1, /* Same as TSU_QTAGM1 */
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TSU_QTAGM0,
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TSU_QTAGM1,
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TSU_FWSR,
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