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bus: mhi: ep: Add support for managing MHI state machine
Add support for managing the MHI state machine by controlling the state transitions. Only the following MHI state transitions are supported: 1. Ready state 2. M0 state 3. M3 state 4. SYS_ERR state Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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@ -1,2 +1,2 @@
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obj-$(CONFIG_MHI_BUS_EP) += mhi_ep.o
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mhi_ep-y := main.o mmio.o ring.o
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mhi_ep-y := main.o mmio.o ring.o sm.o
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@ -146,6 +146,11 @@ struct mhi_ep_event {
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struct mhi_ep_ring ring;
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};
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struct mhi_ep_state_transition {
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struct list_head node;
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enum mhi_state state;
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};
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struct mhi_ep_chan {
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char *name;
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struct mhi_ep_device *mhi_dev;
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@ -200,5 +205,11 @@ void mhi_ep_mmio_update_ner(struct mhi_ep_cntrl *mhi_cntrl);
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/* MHI EP core functions */
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int mhi_ep_send_state_change_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state state);
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int mhi_ep_send_ee_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_ee_type exec_env);
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bool mhi_ep_check_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state cur_mhi_state,
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enum mhi_state mhi_state);
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int mhi_ep_set_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state mhi_state);
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int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl);
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int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl);
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int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl);
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#endif
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@ -105,6 +105,43 @@ static int mhi_ep_send_cmd_comp_event(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_e
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return mhi_ep_send_event(mhi_cntrl, 0, &event, 0);
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}
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static void mhi_ep_state_worker(struct work_struct *work)
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{
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struct mhi_ep_cntrl *mhi_cntrl = container_of(work, struct mhi_ep_cntrl, state_work);
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struct device *dev = &mhi_cntrl->mhi_dev->dev;
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struct mhi_ep_state_transition *itr, *tmp;
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unsigned long flags;
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LIST_HEAD(head);
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int ret;
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spin_lock_irqsave(&mhi_cntrl->list_lock, flags);
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list_splice_tail_init(&mhi_cntrl->st_transition_list, &head);
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spin_unlock_irqrestore(&mhi_cntrl->list_lock, flags);
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list_for_each_entry_safe(itr, tmp, &head, node) {
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list_del(&itr->node);
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dev_dbg(dev, "Handling MHI state transition to %s\n",
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mhi_state_str(itr->state));
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switch (itr->state) {
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case MHI_STATE_M0:
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ret = mhi_ep_set_m0_state(mhi_cntrl);
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if (ret)
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dev_err(dev, "Failed to transition to M0 state\n");
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break;
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case MHI_STATE_M3:
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ret = mhi_ep_set_m3_state(mhi_cntrl);
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if (ret)
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dev_err(dev, "Failed to transition to M3 state\n");
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break;
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default:
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dev_err(dev, "Invalid MHI state transition: %d\n", itr->state);
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break;
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}
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kfree(itr);
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}
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}
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static void mhi_ep_release_device(struct device *dev)
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{
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struct mhi_ep_device *mhi_dev = to_mhi_ep_device(dev);
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@ -314,6 +351,17 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,
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goto err_free_ch;
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}
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INIT_WORK(&mhi_cntrl->state_work, mhi_ep_state_worker);
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mhi_cntrl->wq = alloc_workqueue("mhi_ep_wq", 0, 0);
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if (!mhi_cntrl->wq) {
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ret = -ENOMEM;
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goto err_free_cmd;
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}
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INIT_LIST_HEAD(&mhi_cntrl->st_transition_list);
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spin_lock_init(&mhi_cntrl->state_lock);
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spin_lock_init(&mhi_cntrl->list_lock);
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mutex_init(&mhi_cntrl->event_lock);
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/* Set MHI version and AMSS EE before enumeration */
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@ -323,7 +371,7 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *mhi_cntrl,
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/* Set controller index */
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ret = ida_alloc(&mhi_ep_cntrl_ida, GFP_KERNEL);
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if (ret < 0)
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goto err_free_cmd;
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goto err_destroy_wq;
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mhi_cntrl->index = ret;
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@ -351,6 +399,8 @@ err_put_dev:
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put_device(&mhi_dev->dev);
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err_ida_free:
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ida_free(&mhi_ep_cntrl_ida, mhi_cntrl->index);
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err_destroy_wq:
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destroy_workqueue(mhi_cntrl->wq);
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err_free_cmd:
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kfree(mhi_cntrl->mhi_cmd);
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err_free_ch:
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@ -364,6 +414,8 @@ void mhi_ep_unregister_controller(struct mhi_ep_cntrl *mhi_cntrl)
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{
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struct mhi_ep_device *mhi_dev = mhi_cntrl->mhi_dev;
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destroy_workqueue(mhi_cntrl->wq);
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kfree(mhi_cntrl->mhi_cmd);
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kfree(mhi_cntrl->mhi_chan);
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136
drivers/bus/mhi/ep/sm.c
Normal file
136
drivers/bus/mhi/ep/sm.c
Normal file
@ -0,0 +1,136 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <linux/errno.h>
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#include <linux/mhi_ep.h>
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#include "internal.h"
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bool __must_check mhi_ep_check_mhi_state(struct mhi_ep_cntrl *mhi_cntrl,
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enum mhi_state cur_mhi_state,
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enum mhi_state mhi_state)
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{
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if (mhi_state == MHI_STATE_SYS_ERR)
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return true; /* Allowed in any state */
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if (mhi_state == MHI_STATE_READY)
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return cur_mhi_state == MHI_STATE_RESET;
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if (mhi_state == MHI_STATE_M0)
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return cur_mhi_state == MHI_STATE_M3 || cur_mhi_state == MHI_STATE_READY;
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if (mhi_state == MHI_STATE_M3)
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return cur_mhi_state == MHI_STATE_M0;
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return false;
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}
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int mhi_ep_set_mhi_state(struct mhi_ep_cntrl *mhi_cntrl, enum mhi_state mhi_state)
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{
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struct device *dev = &mhi_cntrl->mhi_dev->dev;
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if (!mhi_ep_check_mhi_state(mhi_cntrl, mhi_cntrl->mhi_state, mhi_state)) {
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dev_err(dev, "MHI state change to %s from %s is not allowed!\n",
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mhi_state_str(mhi_state),
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mhi_state_str(mhi_cntrl->mhi_state));
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return -EACCES;
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}
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/* TODO: Add support for M1 and M2 states */
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if (mhi_state == MHI_STATE_M1 || mhi_state == MHI_STATE_M2) {
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dev_err(dev, "MHI state (%s) not supported\n", mhi_state_str(mhi_state));
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return -EOPNOTSUPP;
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}
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mhi_ep_mmio_masked_write(mhi_cntrl, EP_MHISTATUS, MHISTATUS_MHISTATE_MASK, mhi_state);
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mhi_cntrl->mhi_state = mhi_state;
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if (mhi_state == MHI_STATE_READY)
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mhi_ep_mmio_masked_write(mhi_cntrl, EP_MHISTATUS, MHISTATUS_READY_MASK, 1);
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if (mhi_state == MHI_STATE_SYS_ERR)
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mhi_ep_mmio_masked_write(mhi_cntrl, EP_MHISTATUS, MHISTATUS_SYSERR_MASK, 1);
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return 0;
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}
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int mhi_ep_set_m0_state(struct mhi_ep_cntrl *mhi_cntrl)
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{
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struct device *dev = &mhi_cntrl->mhi_dev->dev;
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enum mhi_state old_state;
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int ret;
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spin_lock_bh(&mhi_cntrl->state_lock);
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old_state = mhi_cntrl->mhi_state;
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ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M0);
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spin_unlock_bh(&mhi_cntrl->state_lock);
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if (ret)
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return ret;
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/* Signal host that the device moved to M0 */
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ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M0);
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if (ret) {
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dev_err(dev, "Failed sending M0 state change event\n");
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return ret;
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}
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if (old_state == MHI_STATE_READY) {
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/* Send AMSS EE event to host */
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ret = mhi_ep_send_ee_event(mhi_cntrl, MHI_EE_AMSS);
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if (ret) {
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dev_err(dev, "Failed sending AMSS EE event\n");
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return ret;
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}
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}
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return 0;
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}
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int mhi_ep_set_m3_state(struct mhi_ep_cntrl *mhi_cntrl)
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{
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struct device *dev = &mhi_cntrl->mhi_dev->dev;
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int ret;
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spin_lock_bh(&mhi_cntrl->state_lock);
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ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
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spin_unlock_bh(&mhi_cntrl->state_lock);
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if (ret)
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return ret;
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/* Signal host that the device moved to M3 */
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ret = mhi_ep_send_state_change_event(mhi_cntrl, MHI_STATE_M3);
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if (ret) {
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dev_err(dev, "Failed sending M3 state change event\n");
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return ret;
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}
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return 0;
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}
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int mhi_ep_set_ready_state(struct mhi_ep_cntrl *mhi_cntrl)
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{
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struct device *dev = &mhi_cntrl->mhi_dev->dev;
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enum mhi_state mhi_state;
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int ret, is_ready;
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spin_lock_bh(&mhi_cntrl->state_lock);
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/* Ensure that the MHISTATUS is set to RESET by host */
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mhi_state = mhi_ep_mmio_masked_read(mhi_cntrl, EP_MHISTATUS, MHISTATUS_MHISTATE_MASK);
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is_ready = mhi_ep_mmio_masked_read(mhi_cntrl, EP_MHISTATUS, MHISTATUS_READY_MASK);
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if (mhi_state != MHI_STATE_RESET || is_ready) {
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dev_err(dev, "READY state transition failed. MHI host not in RESET state\n");
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spin_unlock_bh(&mhi_cntrl->state_lock);
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return -EIO;
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}
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ret = mhi_ep_set_mhi_state(mhi_cntrl, MHI_STATE_READY);
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spin_unlock_bh(&mhi_cntrl->state_lock);
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return ret;
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}
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@ -67,6 +67,11 @@ struct mhi_ep_db_info {
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* @cmd_ctx_host_pa: Physical address of host command context data structure
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* @chdb: Array of channel doorbell interrupt info
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* @event_lock: Lock for protecting event rings
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* @list_lock: Lock for protecting state transition and channel doorbell lists
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* @state_lock: Lock for protecting state transitions
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* @st_transition_list: List of state transitions
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* @wq: Dedicated workqueue for handling rings and state changes
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* @state_work: State transition worker
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* @raise_irq: CB function for raising IRQ to the host
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* @alloc_map: CB function for allocating memory in endpoint for storing host context and mapping it
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* @unmap_free: CB function to unmap and free the allocated memory in endpoint for storing host context
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@ -100,6 +105,13 @@ struct mhi_ep_cntrl {
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struct mhi_ep_db_info chdb[4];
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struct mutex event_lock;
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spinlock_t list_lock;
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spinlock_t state_lock;
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struct list_head st_transition_list;
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struct workqueue_struct *wq;
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struct work_struct state_work;
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void (*raise_irq)(struct mhi_ep_cntrl *mhi_cntrl, u32 vector);
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int (*alloc_map)(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, phys_addr_t *phys_ptr,
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