mirror of
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synced 2024-11-15 16:41:58 +00:00
Our usual number of patches to improve the Allwinner Device Tree
support, including: - CPUFreq / Thermal throttling support for the H5 - Touchscreen support for the Pinephone - New boards: PinePhone v1.2 -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXxWlZAAKCRDj7w1vZxhR xft/AQCaR2CkyOVyK32yPUX0ZF2nS+LYzalJIUpOuLhy37GQVwEA+vlQTa7fKdtW 4IX58peBkRD8FwTszrwR/tImDPd8Rwg= =z8pA -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Our usual number of patches to improve the Allwinner Device Tree support, including: - CPUFreq / Thermal throttling support for the H5 - Touchscreen support for the Pinephone - New boards: PinePhone v1.2 * tag 'sunxi-dt-for-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: h5: bananapi-m2-plus-v1.2: Tie in CPU OPPs arm64: dts: allwinner: h5: libretech-all-h3-cc: Tie in CPU OPPs arm64: dts: allwinner: h5: Add CPU Operating Performance Points table arm64: dts: allwinner: h5: Add trip and cooling maps to CPU thermal zones arm64: dts: allwinner: h5: Add clock to CPU cores ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltages ARM: dts: sunxi: bananapi-m2-plus-v1.2: Add regulator supply to all CPU cores ARM: dts: sunxi: libretech-all-h3-cc: Add regulator supply to all CPU cores arm64: dts: sun50i-pinephone: dldo4 must not be >= 1.8V arm64: dts: allwinner: Add support for PinePhone revision 1.2 dt-bindings: arm: sunxi: Add PinePhone 1.2 bindings arm64: dts: sun50i-a64-pinephone: Add touchscreen support arm64: dts: sun50i-a64-pinephone: Enable LCD support on PinePhone ARM: dts: orange-pi-zero-plus2: add leds configuration ARM: dts: orange-pi-zero-plus2: enable USB OTG port Link: https://lore.kernel.org/r/fa48ffcb-3404-41bb-b065-a16717cf5688.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
4828f45708
@ -657,6 +657,11 @@ properties:
|
||||
- const: pine64,pinephone-1.1
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PinePhone (1.2)
|
||||
items:
|
||||
- const: pine64,pinephone-1.2
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineTab
|
||||
items:
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- const: pine64,pinetab
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||||
|
||||
@ -70,6 +70,21 @@
|
||||
};
|
||||
};
|
||||
|
||||
leds {
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||||
compatible = "gpio-leds";
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||||
|
||||
pwr {
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||||
label = "orangepi:green:pwr";
|
||||
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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||||
};
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||||
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||||
status {
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||||
label = "orangepi:red:status";
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||||
gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
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||||
};
|
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};
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||||
|
||||
reg_vcc3v3: vcc3v3 {
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||||
compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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@ -88,6 +103,10 @@
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status = "okay";
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||||
};
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||||
|
||||
&ehci0 {
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status = "okay";
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||||
};
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||||
|
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&hdmi {
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status = "okay";
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};
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@ -132,8 +151,27 @@
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status = "okay";
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||||
};
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||||
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&ohci0 {
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status = "okay";
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||||
};
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||||
&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pa_pins>;
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status = "okay";
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||||
};
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||||
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&usb_otg {
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/*
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* According to schematics CN1 MicroUSB port can be used to take
|
||||
* external 5V to power up the board VBUS. On the contrary CN1 MicroUSB
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* port cannot provide power externally even if the board is powered
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* via GPIO pins. It thus makes sense to force peripheral mode.
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*/
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dr_mode = "peripheral";
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status = "okay";
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};
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&usbphy {
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status = "okay";
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};
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@ -16,15 +16,27 @@
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regulator-type = "voltage";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1300000>;
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regulator-min-microvolt = <1108475>;
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regulator-max-microvolt = <1308475>;
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regulator-ramp-delay = <50>; /* 4ms */
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gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
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gpios-states = <0x1>;
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states = <1100000 0>, <1300000 1>;
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states = <1108475 0>, <1308475 1>;
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};
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};
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&cpu0 {
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cpu-supply = <®_vdd_cpux>;
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};
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&cpu1 {
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cpu-supply = <®_vdd_cpux>;
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};
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&cpu2 {
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cpu-supply = <®_vdd_cpux>;
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};
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|
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&cpu3 {
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cpu-supply = <®_vdd_cpux>;
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};
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@ -128,6 +128,18 @@
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cpu-supply = <®_vdd_cpux>;
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};
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&cpu1 {
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cpu-supply = <®_vdd_cpux>;
|
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};
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||||
|
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&cpu2 {
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cpu-supply = <®_vdd_cpux>;
|
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};
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|
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&cpu3 {
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cpu-supply = <®_vdd_cpux>;
|
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};
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&de {
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status = "okay";
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};
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@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
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@ -9,3 +9,22 @@
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model = "Pine64 PinePhone Braveheart (1.1)";
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compatible = "pine64,pinephone-1.1", "allwinner,sun50i-a64";
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};
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&backlight {
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power-supply = <®_ldo_io0>;
|
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/*
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* PWM backlight circuit on this PinePhone revision was changed since
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* 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
|
||||
* being off is around 20%. Duty cycle for the lowest brightness level
|
||||
* also varries quite a bit between individual boards, so the lowest
|
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* value here was chosen as a safe default.
|
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*/
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brightness-levels = <
|
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774 793 814 842
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882 935 1003 1088
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1192 1316 1462 1633
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1830 2054 2309 2596
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2916 3271 3664 4096>;
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num-interpolated-steps = <50>;
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default-brightness-level = <400>;
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};
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40
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
Normal file
40
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
Normal file
@ -0,0 +1,40 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
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/dts-v1/;
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||||
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||||
#include "sun50i-a64-pinephone.dtsi"
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|
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/ {
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model = "Pine64 PinePhone (1.2)";
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compatible = "pine64,pinephone-1.2", "allwinner,sun50i-a64";
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};
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||||
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||||
&backlight {
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||||
power-supply = <®_ldo_io0>;
|
||||
/*
|
||||
* PWM backlight circuit on this PinePhone revision was changed since 1.0,
|
||||
* and the lowest PWM duty cycle that doesn't lead to backlight being off
|
||||
* is around 10%. Duty cycle for the lowest brightness level also varries
|
||||
* quite a bit between individual boards, so the lowest value here was
|
||||
* chosen as a safe default.
|
||||
*/
|
||||
brightness-levels = <
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5000 5248 5506 5858 6345
|
||||
6987 7805 8823 10062 11543
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||||
13287 15317 17654 20319 23336
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||||
26724 30505 34702 39335 44427
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||||
50000
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||||
>;
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||||
num-interpolated-steps = <50>;
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||||
default-brightness-level = <500>;
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||||
};
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||||
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||||
&lis3mdl {
|
||||
/*
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||||
* Board revision 1.2 fixed routing of the interrupt to DRDY pin,
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||||
* enable interrupts.
|
||||
*/
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <1 1 IRQ_TYPE_EDGE_RISING>; /* PB1 */
|
||||
};
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||||
@ -16,6 +16,13 @@
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serial0 = &uart0;
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||||
};
|
||||
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||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
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pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
|
||||
enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
|
||||
/* Backlight configuration differs per PinePhone revision. */
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
@ -84,6 +91,28 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&de {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
vcc-dsi-supply = <®_dldo1>;
|
||||
status = "okay";
|
||||
|
||||
panel@0 {
|
||||
compatible = "xingbangda,xbd599";
|
||||
reg = <0>;
|
||||
reset-gpios = <&pio 3 23 GPIO_ACTIVE_LOW>; /* PD23 */
|
||||
iovcc-supply = <®_dldo2>;
|
||||
vcc-supply = <®_ldo_io0>;
|
||||
backlight = <&backlight>;
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -92,11 +121,28 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
touchscreen@5d {
|
||||
compatible = "goodix,gt917s";
|
||||
reg = <0x5d>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <7 4 IRQ_TYPE_LEVEL_HIGH>; /* PH4 */
|
||||
irq-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
|
||||
reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
|
||||
AVDD28-supply = <®_ldo_io0>;
|
||||
VDDIO-supply = <®_ldo_io0>;
|
||||
touchscreen-size-x = <720>;
|
||||
touchscreen-size-y = <1440>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
/* Magnetometer */
|
||||
lis3mdl@1e {
|
||||
lis3mdl: lis3mdl@1e {
|
||||
compatible = "st,lis3mdl-magn";
|
||||
reg = <0x1e>;
|
||||
vdd-supply = <®_dldo1>;
|
||||
@ -188,6 +234,10 @@
|
||||
*/
|
||||
};
|
||||
|
||||
&r_pwm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&r_rsb {
|
||||
status = "okay";
|
||||
|
||||
@ -279,7 +329,7 @@
|
||||
|
||||
®_dldo4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc-wifi-io";
|
||||
};
|
||||
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun50i-h5.dtsi"
|
||||
#include "sun50i-h5-cpu-opp.dtsi"
|
||||
#include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
|
||||
|
||||
/ {
|
||||
|
||||
79
arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
Normal file
79
arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
Normal file
@ -0,0 +1,79 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
|
||||
|
||||
/ {
|
||||
cpu_opp_table: cpu-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-408000000 {
|
||||
opp-hz = /bits/ 64 <408000000>;
|
||||
opp-microvolt = <1000000 1000000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-648000000 {
|
||||
opp-hz = /bits/ 64 <648000000>;
|
||||
opp-microvolt = <1040000 1040000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-816000000 {
|
||||
opp-hz = /bits/ 64 <816000000>;
|
||||
opp-microvolt = <1080000 1080000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-912000000 {
|
||||
opp-hz = /bits/ 64 <912000000>;
|
||||
opp-microvolt = <1120000 1120000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-microvolt = <1160000 1160000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-1008000000 {
|
||||
opp-hz = /bits/ 64 <1008000000>;
|
||||
opp-microvolt = <1200000 1200000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <1240000 1240000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-1104000000 {
|
||||
opp-hz = /bits/ 64 <1104000000>;
|
||||
opp-microvolt = <1260000 1260000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
|
||||
opp-1152000000 {
|
||||
opp-hz = /bits/ 64 <1152000000>;
|
||||
opp-microvolt = <1300000 1300000 1310000>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
};
|
||||
@ -4,6 +4,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
#include "sun50i-h5.dtsi"
|
||||
#include "sun50i-h5-cpu-opp.dtsi"
|
||||
#include <arm/sunxi-libretech-all-h3-cc.dtsi>
|
||||
|
||||
/ {
|
||||
|
||||
@ -30,6 +30,21 @@
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pwr {
|
||||
label = "orangepi:green:pwr";
|
||||
gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
status {
|
||||
label = "orangepi:red:status";
|
||||
gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_vcc3v3: vcc3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3";
|
||||
@ -48,6 +63,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "okay";
|
||||
};
|
||||
@ -92,6 +111,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pa_pins>;
|
||||
@ -103,3 +126,18 @@
|
||||
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
||||
/*
|
||||
* According to schematics CN1 MicroUSB port can be used to take
|
||||
* external 5V to power up the board VBUS. On the contrary CN1 MicroUSB
|
||||
* port cannot provide power externally even if the board is powered
|
||||
* via GPIO pins. It thus makes sense to force peripheral mode.
|
||||
*/
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -3,6 +3,8 @@
|
||||
|
||||
#include <arm/sunxi-h3-h5.dtsi>
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@ -13,6 +15,9 @@
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
@ -20,6 +25,9 @@
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
@ -27,6 +35,9 @@
|
||||
device_type = "cpu";
|
||||
reg = <2>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
@ -34,6 +45,9 @@
|
||||
device_type = "cpu";
|
||||
reg = <3>;
|
||||
enable-method = "psci";
|
||||
clocks = <&ccu CLK_CPUX>;
|
||||
clock-latency-ns = <244144>; /* 8 32k periods */
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -165,6 +179,30 @@
|
||||
polling-delay-passive = <0>;
|
||||
polling-delay = <0>;
|
||||
thermal-sensors = <&ths 0>;
|
||||
|
||||
trips {
|
||||
cpu_hot_trip: cpu-hot {
|
||||
temperature = <80000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
cpu_very_hot_trip: cpu-very-hot {
|
||||
temperature = <100000>;
|
||||
hysteresis = <0>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
cpu-hot-limit {
|
||||
trip = <&cpu_hot_trip>;
|
||||
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpu_thermal {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user