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iommu/amd: Store the nid in io_pgtable_cfg instead of the domain
We already have memory in the union here that is being wasted in AMD's case, use it to store the nid. Putting the nid here further isolates the io_pgtable code from the struct protection_domain. Fixup protection_domain_alloc so that the NID from the device is provided, at this point dev is never NULL for AMD so this will now allocate the first table pointer on the correct NUMA node. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Link: https://lore.kernel.org/r/8-v2-831cdc4d00f3+1a315-amd_iopgtbl_jgg@nvidia.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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977fc27ca7
commit
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@ -45,7 +45,7 @@ extern enum io_pgtable_fmt amd_iommu_pgtable;
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extern int amd_iommu_gpt_level;
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/* Protection domain ops */
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struct protection_domain *protection_domain_alloc(unsigned int type);
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struct protection_domain *protection_domain_alloc(unsigned int type, int nid);
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void protection_domain_free(struct protection_domain *domain);
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struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev,
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struct mm_struct *mm);
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@ -571,7 +571,6 @@ struct protection_domain {
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struct amd_io_pgtable iop;
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spinlock_t lock; /* mostly used to lock the page table*/
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u16 id; /* the domain id written to the device table */
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int nid; /* Node ID */
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enum protection_domain_mode pd_mode; /* Track page table type */
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bool dirty_tracking; /* dirty tracking is enabled in the domain */
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unsigned dev_cnt; /* devices assigned to this domain */
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@ -141,11 +141,12 @@ static bool increase_address_space(struct protection_domain *domain,
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unsigned long address,
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gfp_t gfp)
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{
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struct io_pgtable_cfg *cfg = &domain->iop.pgtbl.cfg;
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unsigned long flags;
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bool ret = true;
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u64 *pte;
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pte = iommu_alloc_page_node(domain->nid, gfp);
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pte = iommu_alloc_page_node(cfg->amd.nid, gfp);
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if (!pte)
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return false;
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@ -181,6 +182,7 @@ static u64 *alloc_pte(struct protection_domain *domain,
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gfp_t gfp,
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bool *updated)
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{
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struct io_pgtable_cfg *cfg = &domain->iop.pgtbl.cfg;
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int level, end_lvl;
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u64 *pte, *page;
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@ -232,7 +234,7 @@ static u64 *alloc_pte(struct protection_domain *domain,
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if (!IOMMU_PTE_PRESENT(__pte) ||
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pte_level == PAGE_MODE_NONE) {
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page = iommu_alloc_page_node(domain->nid, gfp);
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page = iommu_alloc_page_node(cfg->amd.nid, gfp);
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if (!page)
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return NULL;
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@ -559,7 +561,7 @@ static struct io_pgtable *v1_alloc_pgtable(struct io_pgtable_cfg *cfg, void *coo
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{
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struct amd_io_pgtable *pgtable = io_pgtable_cfg_to_data(cfg);
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pgtable->root = iommu_alloc_page(GFP_KERNEL);
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pgtable->root = iommu_alloc_page_node(cfg->amd.nid, GFP_KERNEL);
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if (!pgtable->root)
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return NULL;
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pgtable->mode = PAGE_MODE_3_LEVEL;
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@ -251,7 +251,7 @@ static int iommu_v2_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
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while (mapped_size < size) {
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map_size = get_alloc_page_size(pgsize);
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pte = v2_alloc_pte(pdom->nid, pdom->iop.pgd,
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pte = v2_alloc_pte(cfg->amd.nid, pdom->iop.pgd,
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iova, map_size, gfp, &updated);
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if (!pte) {
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ret = -EINVAL;
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@ -359,10 +359,9 @@ static void v2_free_pgtable(struct io_pgtable *iop)
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static struct io_pgtable *v2_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
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{
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struct amd_io_pgtable *pgtable = io_pgtable_cfg_to_data(cfg);
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struct protection_domain *pdom = (struct protection_domain *)cookie;
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int ias = IOMMU_IN_ADDR_BIT_SIZE;
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pgtable->pgd = iommu_alloc_page_node(pdom->nid, GFP_KERNEL);
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pgtable->pgd = iommu_alloc_page_node(cfg->amd.nid, GFP_KERNEL);
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if (!pgtable->pgd)
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return NULL;
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@ -2023,6 +2023,7 @@ static int do_attach(struct iommu_dev_data *dev_data,
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struct protection_domain *domain)
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{
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struct amd_iommu *iommu = get_amd_iommu_from_dev_data(dev_data);
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struct io_pgtable_cfg *cfg = &domain->iop.pgtbl.cfg;
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int ret = 0;
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/* Update data structures */
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@ -2030,8 +2031,8 @@ static int do_attach(struct iommu_dev_data *dev_data,
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list_add(&dev_data->list, &domain->dev_list);
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/* Update NUMA Node ID */
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if (domain->nid == NUMA_NO_NODE)
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domain->nid = dev_to_node(dev_data->dev);
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if (cfg->amd.nid == NUMA_NO_NODE)
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cfg->amd.nid = dev_to_node(dev_data->dev);
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/* Do reference counting */
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domain->dev_iommu[iommu->index] += 1;
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@ -2266,7 +2267,7 @@ void protection_domain_free(struct protection_domain *domain)
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kfree(domain);
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}
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struct protection_domain *protection_domain_alloc(unsigned int type)
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struct protection_domain *protection_domain_alloc(unsigned int type, int nid)
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{
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struct io_pgtable_ops *pgtbl_ops;
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struct protection_domain *domain;
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@ -2283,7 +2284,7 @@ struct protection_domain *protection_domain_alloc(unsigned int type)
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spin_lock_init(&domain->lock);
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INIT_LIST_HEAD(&domain->dev_list);
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INIT_LIST_HEAD(&domain->dev_data_list);
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domain->nid = NUMA_NO_NODE;
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domain->iop.pgtbl.cfg.amd.nid = nid;
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switch (type) {
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/* No need to allocate io pgtable ops in passthrough mode */
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@ -2360,7 +2361,8 @@ static struct iommu_domain *do_iommu_domain_alloc(unsigned int type,
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if (dirty_tracking && !amd_iommu_hd_support(iommu))
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return ERR_PTR(-EOPNOTSUPP);
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domain = protection_domain_alloc(type);
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domain = protection_domain_alloc(type,
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dev ? dev_to_node(dev) : NUMA_NO_NODE);
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if (!domain)
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return ERR_PTR(-ENOMEM);
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@ -181,7 +181,7 @@ struct iommu_domain *amd_iommu_domain_alloc_sva(struct device *dev,
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struct protection_domain *pdom;
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int ret;
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pdom = protection_domain_alloc(IOMMU_DOMAIN_SVA);
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pdom = protection_domain_alloc(IOMMU_DOMAIN_SVA, dev_to_node(dev));
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if (!pdom)
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return ERR_PTR(-ENOMEM);
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@ -171,6 +171,10 @@ struct io_pgtable_cfg {
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u64 ttbr[4];
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u32 n_ttbrs;
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} apple_dart_cfg;
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struct {
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int nid;
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} amd;
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};
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};
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